CN113299735A - 一种带有斜坡的半导体器件终端结构及其制造方法 - Google Patents
一种带有斜坡的半导体器件终端结构及其制造方法 Download PDFInfo
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- CN113299735A CN113299735A CN202110515569.1A CN202110515569A CN113299735A CN 113299735 A CN113299735 A CN 113299735A CN 202110515569 A CN202110515569 A CN 202110515569A CN 113299735 A CN113299735 A CN 113299735A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- Condensed Matter Physics & Semiconductors (AREA)
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Citations (13)
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US4532005A (en) * | 1984-05-21 | 1985-07-30 | At&T Bell Laboratories | Device lithography using multi-level resist systems |
WO2007002059A1 (en) * | 2005-06-28 | 2007-01-04 | Micron Technology, Inc. | Process for creating tilted microlens |
CN103353209A (zh) * | 2013-06-20 | 2013-10-16 | 京东方科技集团股份有限公司 | 一种真空干燥装置及光刻工艺 |
CN103579073A (zh) * | 2012-07-20 | 2014-02-12 | 上海华虹Nec电子有限公司 | 深沟槽填充方法 |
CN104576345A (zh) * | 2013-10-29 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | 功率器件中斜坡场板结构的制备方法 |
CN104681681A (zh) * | 2013-12-03 | 2015-06-03 | 上海蓝光科技有限公司 | 一种用于ⅲ-ⅴ族氮化物生长的衬底结构及其制备方法 |
CN106504981A (zh) * | 2016-10-14 | 2017-03-15 | 电子科技大学 | 一种制备角度可控缓坡微结构的方法 |
CN107275382A (zh) * | 2017-06-20 | 2017-10-20 | 中国科学院微电子研究所 | 一种基于台面多区复合jte终端结构的器件及其制作方法 |
CN107706108A (zh) * | 2017-10-11 | 2018-02-16 | 中国科学院微电子研究所 | 一种碳化硅器件结终端制作方法 |
CN108346688A (zh) * | 2018-01-25 | 2018-07-31 | 中国科学院微电子研究所 | 具有CSL输运层的SiC沟槽结势垒肖特基二极管及其制作方法 |
US20190131446A1 (en) * | 2017-10-27 | 2019-05-02 | Infineon Technologies Ag | Semiconductor Device with Junction Termination Zone |
CN109814329A (zh) * | 2018-12-14 | 2019-05-28 | 浙江大学 | 一种渐变光刻版图及其半导体表面制造方法 |
CN112201686A (zh) * | 2020-09-08 | 2021-01-08 | 浙江大学 | 一种超级结器件及终端 |
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2021
- 2021-05-12 CN CN202110515569.1A patent/CN113299735B/zh active Active
Patent Citations (13)
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US4532005A (en) * | 1984-05-21 | 1985-07-30 | At&T Bell Laboratories | Device lithography using multi-level resist systems |
WO2007002059A1 (en) * | 2005-06-28 | 2007-01-04 | Micron Technology, Inc. | Process for creating tilted microlens |
CN103579073A (zh) * | 2012-07-20 | 2014-02-12 | 上海华虹Nec电子有限公司 | 深沟槽填充方法 |
CN103353209A (zh) * | 2013-06-20 | 2013-10-16 | 京东方科技集团股份有限公司 | 一种真空干燥装置及光刻工艺 |
CN104576345A (zh) * | 2013-10-29 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | 功率器件中斜坡场板结构的制备方法 |
CN104681681A (zh) * | 2013-12-03 | 2015-06-03 | 上海蓝光科技有限公司 | 一种用于ⅲ-ⅴ族氮化物生长的衬底结构及其制备方法 |
CN106504981A (zh) * | 2016-10-14 | 2017-03-15 | 电子科技大学 | 一种制备角度可控缓坡微结构的方法 |
CN107275382A (zh) * | 2017-06-20 | 2017-10-20 | 中国科学院微电子研究所 | 一种基于台面多区复合jte终端结构的器件及其制作方法 |
CN107706108A (zh) * | 2017-10-11 | 2018-02-16 | 中国科学院微电子研究所 | 一种碳化硅器件结终端制作方法 |
US20190131446A1 (en) * | 2017-10-27 | 2019-05-02 | Infineon Technologies Ag | Semiconductor Device with Junction Termination Zone |
CN108346688A (zh) * | 2018-01-25 | 2018-07-31 | 中国科学院微电子研究所 | 具有CSL输运层的SiC沟槽结势垒肖特基二极管及其制作方法 |
CN109814329A (zh) * | 2018-12-14 | 2019-05-28 | 浙江大学 | 一种渐变光刻版图及其半导体表面制造方法 |
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HU LONG: "Single-Mask Implantation-Free Technique Based on Aperture Density Modulation for Termination in High-Voltage SiC Thyristors", 《IEEE》 * |
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