CN113271421A - Photoelectric array detector reading circuit - Google Patents
Photoelectric array detector reading circuit Download PDFInfo
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- CN113271421A CN113271421A CN202110522512.4A CN202110522512A CN113271421A CN 113271421 A CN113271421 A CN 113271421A CN 202110522512 A CN202110522512 A CN 202110522512A CN 113271421 A CN113271421 A CN 113271421A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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Abstract
The invention relates to the technical field of photoelectric array reading, in particular to a photoelectric array detector reading circuit, which comprises a photoelectric array, a signal processing circuit PCB and an FPGA development board; the photoelectric array is connected with the signal processing circuit PCB board through a board-to-board connector or a flexible flat cable, and the signal processing circuit PCB board is connected with the FPGA development board through a board-to-board connector or a flexible flat cable; the signal processing circuit PCB is integrated with a power supply module, a DAC module, a gating module, a signal amplification module, a filtering module and an ADC module; the invention can directly carry out high-gain and low-noise I-V conversion on photoelectric current generated by the photoelectric array and complete data acquisition.
Description
Technical Field
The invention relates to the technical field of photoelectric array reading, in particular to a photoelectric array detector reading circuit.
Background
The semiconductor photoelectric detector is an ideal detector of a light source due to small volume, light weight, high response speed and high sensitivity, is easy to integrate with other semiconductor devices, and can be widely applied to the aspects of imaging, optical communication, solar energy collection, remote sensing, photoelectric memories, environmental monitoring, military reconnaissance and the like. In recent years, optoelectronic materials such as organic materials, nanomaterials and nanocomposites have shown great potential in simple, low cost, flexible, large area photodetectors.
At present, a digital image sensor that directly captures image information as a digital signal is a main technique of image sensing, and a photodetection technique can detect, in principle, all non-electric quantities that can affect the quantity of light and the light characteristics, but requires a photoelectric readout circuit with good performance. However, as the photo array is larger and larger, the photo current generated by the photo module is smaller and smaller, even as low as several nanoamperes, in the existing scheme, the multichannel weak current measurement of the photo array is basically performed in a capacitance integration mode, and in order to improve the sensitivity of weak current measurement, the integration capacitance should be reduced or the integration time should be increased. However, due to the influence of distributed capacitance caused by wiring, the capacitance cannot be infinitely reduced, the sensitivity of the amplifying circuit can be improved only by prolonging the integration time, the real-time performance of the measuring system is reduced, and signals cannot be rapidly measured. For example, the invention patent "readout circuit and application method of photodiode imaging array" (application number: 202110013558.3) applies multiple integrator channels; the utility model discloses a device for improving weak current signal amplifier circuit bandwidth (publication No. CN204272033U) processes weak current signal after converting into voltage signal through the form of capacitance integration.
Disclosure of Invention
In order to solve the above problems, the present invention provides a readout circuit of a photo array detector with good performance and stable readout, which can directly perform high-gain and low-noise I-V conversion on the photo current generated by the photo array and complete data acquisition.
The technical scheme for solving the problems is as follows:
a photoelectric array detector reading circuit comprises a photoelectric array, a signal processing circuit PCB and an FPGA development board; the photoelectric array is connected with the signal processing circuit PCB board through a board-to-board connector or a flexible flat cable, and the signal processing circuit PCB board is connected with the FPGA development board through a board-to-board connector or a flexible flat cable;
the signal processing circuit PCB is integrated with a power supply module, a DAC module, a gating module, a signal amplification module, a filtering module and an ADC module; the power supply module adjusts the voltage provided by the external voltage-stabilized power supply into the required stable output voltage so as to supply power to the whole circuit; the DAC module converts a digital quantity signal input by the FPGA development board into an analog quantity signal for output by taking reference voltage as reference so as to provide bias voltage required by the photoelectric array; the gating module completes gating output of any array point in the photoelectric array under the control of the FPGA development board; the signal amplification module realizes I-V conversion on the photo-generated current output by the gating module, namely, the current signal is converted into a voltage signal, and the voltage signal is amplified; the filtering module is used for filtering the voltage signal obtained by conversion and amplification of the signal amplification module; the ADC module converts the filtered voltage signal into a digital signal and transmits the digital signal to the FPGA development board through a serial port, and the acquisition time and frequency of the ADC module are controlled by the FPGA development board.
The photovoltaic array may be a single point array or a cross array.
When the photoelectric array is a single-point array, the gating module is positioned at the output end of the photoelectric array and consists of a multiplexer, and the multiplexer controls the states of an address line and an enabling pin by an FPGA development board so as to open or close any channel; when the photoelectric array is a cross array, the gating module is positioned at the input end and the output end of the photoelectric array and consists of a multiplexer and a single-pole multi-throw switch, the multiplexer is positioned at the input end and the output end of the photoelectric array and used for signal gating, and the single-pole multi-throw switch is positioned at the input end and the output end of the photoelectric array, connected with the multiplexer in parallel and used for charge discharge; the multiplexer and the single-pole multi-throw switch control the states of an address line and an enabling pin by an FPGA development board, so that any channel is opened or closed, and the gating output of any array point in the photoelectric array is completed.
The signal amplification module comprises an analog ground, a trans-impedance amplifier and a feedback resistor; the photo-generated current output by the gating module is input to the inverting input end of the transimpedance amplifier, the non-inverting input end of the transimpedance amplifier is connected to the analog ground, and the transimpedance amplifier forces all the current to flow through the feedback resistor to form a negative feedback effect, so that the current signal is converted into a voltage signal.
The filtering module is an RC low-pass filter consisting of a resistor and a capacitor.
The invention has the beneficial effects that:
1. the invention adopts the modularized design idea, each board card and each module can be used independently and can be combined to form the whole system, thereby increasing the flexibility and the expansibility of the system.
2. The power module, the DAC module, the gating module, the signal amplification module, the filtering module and the ADC module of the signal processing circuit are integrated on one PCB, and the noise of the whole system can be reduced through proper layout and wiring.
3. The gating module of the invention can not only complete the gating output of the photoelectric array points, but also eliminate the influence of charge accumulation by using a multiplexer and a single-pole multi-throw switch, thereby avoiding the mutual interference between the array points.
4. The method can complete gating output of any array point in the photoelectric array for the single-point array and the cross array, and can be applied to signal acquisition and reading in multiple aspects such as a photoelectric image sensor, a memristor array and the like.
5. The invention can realize the gating output and reading of the current signal as small as nano-ampere, and the whole system can be applied to the field of extremely weak current signals such as neural signal reading and the like through proper improvement and expansion.
Drawings
FIG. 1 is a block diagram of a single-point array readout circuit according to the present invention.
Fig. 2 is a schematic diagram of a cross array readout circuit framework of the present invention.
Fig. 3 is a block diagram of a single-point array readout circuit of the present invention.
FIG. 4 is a schematic diagram of a crossbar array gating module of the present invention.
In the figure: the circuit comprises a 1-FPGA development board, a 2-DAC module, a 3-photoelectric array, a 4-multiplexer, 5-analog ground, a 6-trans-impedance amplifier, 7-feedback resistors, 8-resistors R, 9-capacitors C, a 10-ADC module and 11-single-pole multi-throw switches.
Detailed Description
The following further describes a specific embodiment of the present invention with reference to the drawings and technical solutions.
The invention relates to a photoelectric array detector reading circuit, which comprises a photoelectric array 3, a signal processing circuit PCB and an FPGA development board 1; the power supply module, the DAC module 2, the gating module, the signal amplification module, the filtering module and the ADC module 10 are integrated on a signal processing circuit PCB board through proper layout and wiring. The power supply modules of the FPGA development board 1 and the signal processing circuit PCB need to be powered by an external stabilized voltage power supply. When the FPGA development system works, the FPGA development board 1 is connected with an acquisition card through a Camera Link interface, and the acquisition card is installed on a mainboard of an upper computer.
FPGA development board 1 for commercial FPGA development board, by hardware resources such as logic cell, RAM, multiplier constitution, FPGA development board 1 by constant voltage power supply, board-mounted 50M's active crystal oscillator provides stable clock source for development board, FPGA development board 1 have SDRAM, SPIFLASH, JTAG mouth, USB interface, VGA interface and abundant extension mouth.
The power supply module is powered by a stabilized voltage supply and is converted into stable output voltage through a low-noise linear voltage stabilizer, so that the power supply module supplies power to the whole system. The power module needs to have good load regulation characteristics, and any circuit is started at any time to cause load increase, so that the voltage cannot be reduced due to the increase of current.
The DAC module 2 is composed of a high-performance digital-to-analog converter and a precise reference voltage source, the digital-to-analog converter needs to guarantee monotonicity and has the characteristic of low noise, an input signal of the digital-to-analog converter is controlled by the FPGA development board 1, and the reference voltage source needs to keep stable output voltage in a wide working current and temperature range.
When the photoelectric array 3 is a single-point array, the gating module is positioned at the output end of the photoelectric array and consists of a multiplexer 4, and the multiplexer controls the states of an address line and an enabling pin by the FPGA development board 1 so as to open or close any channel; when the photoelectric array 3 is a cross array, the gating module is positioned at the input end and the output end of the photoelectric array 3, the gating module is composed of a multiplexer 4 and a single-pole multi-throw switch 11, the multiplexer 4 is positioned at the input end and the output end of the photoelectric array 3 and used for signal gating, and the single-pole multi-throw switch 11 is positioned at the input end and the output end of the photoelectric array 3, connected with the multiplexer 4 in parallel and used for charge discharge; the multiplexer 4 and the single-pole multi-throw switch 11 control the states of an address line and an enabling pin by the FPGA development board 1, so as to open or close any channel, and further complete the gating output of any array point in the photoelectric array 3.
The signal amplification module can comprehensively apply amplification circuits such as T-type network amplification, transimpedance amplification, multistage amplification and the like, a transimpedance amplifier 6 in the signal amplification module needs to have low noise and very low characteristics of offset, drift and bias current, and can amplify and convert a weak current signal into a voltage signal and output the voltage signal to a subsequent module for processing.
The filtering module is an RC low-pass filter consisting of a resistor 8 and a capacitor 9, and the low-pass filter can reduce the amount of broadband noise mixed into a baseband and is beneficial to attenuating the recoil influence of a switch capacitor in the input end of the ADC module 10; under the condition of not introducing large noise, the filtering module only needs to be capable of reasonably filtering the noise.
The ADC module 10 is composed of a Successive Approximation Register (SAR) a/D converter and a precision reference voltage source, the a/D converter can be programmed for operation conversion based on an external serial clock SCLK, the a/D converter is controlled by the FPGA development board 1 to collect signals and transmit the collected signals to the FPGA development board 1 through quantization and programming, and the reference voltage source needs to have excellent temperature stability and low output noise.
With reference to fig. 1 and 3, when a bias voltage of a certain magnitude is applied to the photo-electric single-point array, the photo-electric array 3 generates a photo-generated current proportional to the luminous flux irradiated to the array point, and the magnitude of the current can be as low as nA level at the minimum. The DAC module 2 can provide bias voltage required by the photoelectric array 3 under the control of the FPGA development board 1, photogenerated current output by the photoelectric array 3 is sequentially gated and output through the multiplexer 4, the multiplexer 4 is a combined circuit and can select one input from multiple inputs and directly transmit information to an output end, and which input line is selected and controlled by the FPGA development board 1. The gated and output photo-generated current is input to the inverting input end of the transimpedance amplifier 6, the non-inverting input end of the transimpedance amplifier 6 is connected to the analog ground 5, the transimpedance amplifier 6 forces all the current to flow through the feedback resistor 7 to form a negative feedback effect, and therefore I-V conversion of photo-generated current with high gain and low noise is completed. The converted voltage enters an ADC module 10 after being filtered by an RC filter consisting of a resistor 8 and a capacitor 9, analog voltage signals are converted into digital signals after sampling, holding, quantifying and programming, the digital signals are transmitted to an FPGA development board 1, and then the digital signals are transmitted to a collection card through a Camera Link interface, so that the signal collection of the photoelectric array detector is completed.
For the optoelectronic crossbar array, referring to fig. 2, fig. 3 and fig. 4, the difference between the signal processing process and the single-point array is that gating modules are added at two ends of the optoelectronic crossbar array, and the gating modules 4 are formed by a multiplexer and a single-pole multi-throw switch 11. When the photoelectric array detector is a cross array, mutual interference can be generated between each array point due to the accumulation of charges on the array points and the multiplexer, and further effective output and reading of signals are influenced, and the gating module combines the multiplexer 4 and the single-pole multi-throw switch 11 together to solve the problem. Taking the array points a and b in fig. 4 as an example, firstly, the FPGA development board 1 controls the multiplexer 4 to further enable the row and column channels corresponding to the array point a to be non-conductive, and at the same time, the FPGA development board 1 controls the single-pole multi-throw switch 11 to be in a state of not being connected to the analog ground, so that the gated output of the photo-generated current of the array point a can be completed, and after the data acquisition of the array point a is completed, the FPGA development board 1 controls the single-pole multi-throw switch 11 to be in a state of being connected to the analog ground, so that the charges on the array point a and the corresponding multiplexer row and column channels are discharged to the ground. After the charge is completely discharged, the FPGA development board 1 controls the single-pole multi-throw switch 11 to be in a state of not being connected with the analog ground, and simultaneously controls the multiplexer 4 to further enable the row-column channel corresponding to the array point b to be conducted, and other row-column channels to be not conducted, so that the gating output and data acquisition of all the photoelectric array points are completed in a circulating manner.
Claims (5)
1. The photoelectric array detector reading circuit is characterized by comprising a photoelectric array, a signal processing circuit PCB and an FPGA development board; the photoelectric array is connected with the signal processing circuit PCB board through a board-to-board connector or a flexible flat cable, and the signal processing circuit PCB board is connected with the FPGA development board through a board-to-board connector or a flexible flat cable;
the signal processing circuit PCB is integrated with a power supply module, a DAC module, a gating module, a signal amplification module, a filtering module and an ADC module; the power supply module adjusts the voltage provided by the external voltage-stabilized power supply into the required stable output voltage so as to supply power to the whole circuit; the DAC module converts a digital quantity signal input by the FPGA development board into an analog quantity signal for output by taking reference voltage as reference so as to provide bias voltage required by the photoelectric array; the gating module completes gating output of any array point in the photoelectric array under the control of the FPGA development board; the signal amplification module realizes I-V conversion on the photo-generated current output by the gating module, namely, the current signal is converted into a voltage signal, and the voltage signal is amplified; the filtering module is used for filtering the voltage signal obtained by conversion and amplification of the signal amplification module; the ADC module converts the filtered voltage signal into a digital signal and transmits the digital signal to the FPGA development board through a serial port, and the acquisition time and frequency of the ADC module are controlled by the FPGA development board.
2. A photo array detector readout circuit according to claim 1 wherein the photo array is a single point array or a cross array.
3. A photo array detector readout circuit according to claim 1, wherein the signal amplification module comprises an analog ground, a transimpedance amplifier and a feedback resistor; the photo-generated current output by the gating module is input to the inverting input end of the transimpedance amplifier, the non-inverting input end of the transimpedance amplifier is connected to the analog ground, and the transimpedance amplifier forces all the current to flow through the feedback resistor to form a negative feedback effect, so that the current signal is converted into a voltage signal.
4. A photo array detector readout circuit according to claim 1 wherein the filtering module is an RC low pass filter consisting of a resistor and a capacitor.
5. A reading circuit of a photoelectric array detector as claimed in claim 1, 2, 3 or 4, wherein when the photoelectric array is a single-point array, the gating module is located at the output end of the photoelectric array, the gating module is composed of a multiplexer, the multiplexer controls the state of an address line and an enable pin by an FPGA development board, and further opens or closes any channel; when the photoelectric array is a cross array, the gating module is positioned at the input end and the output end of the photoelectric array and consists of a multiplexer and a single-pole multi-throw switch, the multiplexer is positioned at the input end and the output end of the photoelectric array and used for signal gating, and the single-pole multi-throw switch is positioned at the input end and the output end of the photoelectric array, connected with the multiplexer in parallel and used for charge discharge; the multiplexer and the single-pole multi-throw switch control the states of an address line and an enabling pin by an FPGA development board, so that any channel is opened or closed, and the gating output of any array point in the photoelectric array is completed.
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| CN202110522512.4A CN113271421B (en) | 2021-05-13 | 2021-05-13 | Photoelectric array detector reading circuit |
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| CN202110522512.4A CN113271421B (en) | 2021-05-13 | 2021-05-13 | Photoelectric array detector reading circuit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2916462A1 (en) * | 2012-11-01 | 2015-09-09 | ZTE Corporation | Intermediate-frequency analogue-to-digital conversion device |
| CN207947781U (en) * | 2018-01-22 | 2018-10-09 | 深圳市希锐光通讯有限公司 | The photoelectric converter of integration packaging |
| CN109143171A (en) * | 2018-08-24 | 2019-01-04 | 天津市海为科技发展有限公司 | Modular array acoustical signal real time processing system |
| CN110279416A (en) * | 2019-05-20 | 2019-09-27 | 南京航空航天大学 | A kind of portable impedance imaging system and its working method based on FPGA |
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2021
- 2021-05-13 CN CN202110522512.4A patent/CN113271421B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2916462A1 (en) * | 2012-11-01 | 2015-09-09 | ZTE Corporation | Intermediate-frequency analogue-to-digital conversion device |
| CN207947781U (en) * | 2018-01-22 | 2018-10-09 | 深圳市希锐光通讯有限公司 | The photoelectric converter of integration packaging |
| CN109143171A (en) * | 2018-08-24 | 2019-01-04 | 天津市海为科技发展有限公司 | Modular array acoustical signal real time processing system |
| CN110279416A (en) * | 2019-05-20 | 2019-09-27 | 南京航空航天大学 | A kind of portable impedance imaging system and its working method based on FPGA |
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| CN113271421B (en) | 2022-02-15 |
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