CN113194635B - Impedance line manufacturing method, impedance line and circuit board - Google Patents
Impedance line manufacturing method, impedance line and circuit board Download PDFInfo
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- CN113194635B CN113194635B CN202110273953.5A CN202110273953A CN113194635B CN 113194635 B CN113194635 B CN 113194635B CN 202110273953 A CN202110273953 A CN 202110273953A CN 113194635 B CN113194635 B CN 113194635B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The application relates to an impedance line manufacturing method, an impedance line and a circuit board, wherein the impedance line manufacturing method comprises the following steps: manufacturing a first impedance line and a second impedance line on the first conductive layer and the second conductive layer respectively; the tail ends of the first impedance line and the second impedance line are provided with bonding pads; pressing and manufacturing blind holes at corresponding positions of the bonding pads, and removing the medium on the bonding pads; removing gumming residues, cleaning and drying; and (5) electroplating to fill the blind holes with metal copper to form metal blind holes. According to the manufacturing method of the impedance line, the impedance line is moved into the inner layer through changing the circuit board structure, and then the blind hole is manufactured and electroplating is performed, so that the impedance line of the inner layer can extend to the outer layer through the blind hole to form a contact point, and impedance measurement is facilitated. In the whole process, the flow is less, the process is simple, and the impedance line of the inner layer can be effectively prevented from being interfered by the external environment due to the protection effect of the dielectric layer on the impedance line of the inner layer, so that the stability of the impedance of the circuit board can be maintained in the testing and using processes.
Description
Technical Field
The application relates to the technical field of printed circuit board processing, in particular to a manufacturing method of an impedance line, the impedance line and a circuit board.
Background
The printed circuit board (Printed Circuit Board, PCB), short circuit board, is made by electronic printing technology. The circuit board is not only a carrier for providing the circuit, but also a carrier for providing the electrical signal. Certain circuit boards in the communication, medical and industrial control industries have certain requirements on impedance, and an impedance line is required to be manufactured so as to facilitate subsequent impedance tests.
The copper thickness of the impedance line has a direct effect on the impedance value. In the traditional impedance line manufacturing method, the impedance line is manufactured by adopting a selective electroplating mode of local protection re-electroplating, and the processes of dry film manufacturing, exposure, development, film stripping and the like are needed, so that the process is complex, the materials are used too much, and the cost is increased. And because of the use of selective plating, the thickness of the resistance wire copper is easily thinner than that of other wires, i.e. the position of the resistance wire is recessed. When the solder resist or the covering film is manufactured later, the thickness of the solder resist is overlarge or the covering film is not firmly attached, so that the process quality of the circuit board is affected, and the impedance performance of the circuit board is also affected.
Therefore, the traditional golden finger manufacturing method has the problems of complex process and poor impedance performance.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method for manufacturing an impedance line, and a circuit board, which are simple in process and have good impedance performance.
In a first aspect of the present application, a method for manufacturing an impedance line is provided, including:
taking an inner core plate, wherein the inner core plate comprises a first conductive layer and a second conductive layer;
manufacturing an inner layer pattern on the inner layer core board, wherein manufacturing the inner layer pattern comprises manufacturing a first impedance line and a second impedance line on the first conductive layer and the second conductive layer respectively; the tail ends of the first impedance line and the second impedance line are provided with bonding pads;
sequentially stacking a first dielectric layer and a first copper foil on the first conductive layer;
sequentially superposing a second dielectric layer and a second copper foil on the second conductive layer;
and pressing;
after the lamination, blind holes are formed in the positions of the first copper foil and the second copper foil, which correspond to the bonding pads respectively, and the first dielectric layer and the second dielectric layer on the bonding pads are removed respectively;
then removing the gumming slag, cleaning and drying;
electroplating to fill the blind holes with metal copper to form metal blind holes;
the size of the blind hole is 100% -110% of the size of the bonding pad;
the manufacturing method of the blind hole is carbon dioxide laser ablation;
the electroplating treatment comprises the steps of copper deposition, full-plate electroplating and image electroplating.
In a second aspect of the present application, there is provided an impedance line manufactured using the impedance line manufacturing method described above.
In a third aspect of the present application, a circuit board is provided, comprising an impedance line as described above.
According to the manufacturing method of the impedance line, the impedance line is moved into the inner layer through changing the circuit board structure, and then the blind hole is manufactured and electroplating is performed, so that the impedance line of the inner layer can extend to the outer layer through the blind hole to form a contact point, and impedance measurement is facilitated. In the whole process, the flow is less, the process is simple, and the impedance line of the inner layer can be effectively prevented from being interfered by the external environment due to the protection effect of the dielectric layer on the impedance line of the inner layer, so that the stability of the impedance of the circuit board can be maintained in the testing and using processes.
Drawings
FIG. 1 is a flow chart of a method for fabricating an impedance line according to an embodiment;
FIG. 2 is a schematic diagram of a structure after blind holes are formed in an embodiment;
FIG. 3 is a top view of the structure of FIG. 2;
FIG. 4 is a schematic diagram of an embodiment of the electroplating process in which blind holes are filled with copper metal to form blind metal holes;
fig. 5 is a top view of the structure of fig. 4.
Reference numerals illustrate: 10-first conductive layer, 11-first impedance line, 20-inner dielectric, 30-second conductive layer, 31-second impedance line, 40-first dielectric layer, 41-first blind via, 50-first copper foil, 51-first outer layer line, 52-first electroplated layer, 60-second dielectric layer, 61-second blind via, 70-second copper foil, 71-second outer layer line, 72-second electroplated layer.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
Furthermore, in this patent application, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be a direct contact of the first and second features, or an indirect contact of the first and second features through an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
As previously described, the copper thickness of the impedance line has a direct effect on the impedance value. On the other hand, if the impedance requirement of the circuit board is strict, the copper thickness control requirement of the impedance line in the processing process is also strict. In the processing process of the circuit board, a pattern electroplating process is needed, and the copper thickness of the circuit is increased. If the impedance circuit is also subjected to pattern plating at the same time, the copper thickness of the impedance circuit is easily too thick, and the impedance value is influenced; if the mode of selectively electroplating other circuits is adopted for locally protecting the impedance line, the processes of dry film, exposure, development, film stripping and the like are needed, so that the process is complex, the materials are used too much, and the cost is high. And selective plating can result in a thinner resistive wire copper than other wires, with a recess in the resistive wire. When the solder resist or the covering film is manufactured later, the thickness of the solder resist is overlarge or the covering film is not firmly attached due to the recession, so that the quality and the impedance performance of a product are affected.
On the other hand, the impedance line is generally located on the surface layer of the circuit board, after the product is finished, the surface of the impedance line is only covered with one layer of solder mask or covering film, if the external environment affects the surface of the solder mask or covering film, the impedance line is easily interfered, the measurement accuracy of impedance characteristics is affected, and the subsequent use of the circuit board is also affected.
Based on the above, the application provides a manufacturing method of an impedance line, which is used for solving the problems that the manufacturing difficulty of the impedance line is high and the impedance performance is easily influenced by the outside.
In a first aspect of the present application, referring to fig. 1, a method for fabricating an impedance line is provided, and in one embodiment, the method includes steps S10 to S40.
Step S10: taking an inner core plate, wherein the inner core plate comprises a first conductive layer and a second conductive layer; manufacturing an inner layer pattern on the inner layer core board, wherein manufacturing the inner layer pattern comprises manufacturing a first impedance line and a second impedance line on the first conductive layer and the second conductive layer respectively; the tail ends of the first impedance line and the second impedance line are provided with bonding pads;
step S20: sequentially stacking a first dielectric layer and a first copper foil on the first conductive layer; sequentially superposing a second dielectric layer and a second copper foil on the second conductive layer; and pressing; after lamination, blind holes are formed in the positions of the first copper foil and the second copper foil, which correspond to the bonding pads respectively, and the first dielectric layer and the second dielectric layer on the bonding pads are removed respectively;
step S30: then removing the gumming slag, cleaning and drying;
step S40: and electroplating to fill the blind holes with metal copper and form metal blind holes.
According to the manufacturing method of the impedance line, the impedance line is moved into the inner layer through changing the circuit board structure, and then the blind hole is manufactured and electroplating is performed, so that the impedance line of the inner layer can extend to the outer layer through the blind hole to form a contact point, and impedance measurement is facilitated. In the whole process, the flow is less, the process is simple, and the impedance line of the inner layer can be effectively prevented from being interfered by the external environment due to the protection effect of the dielectric layer on the impedance line of the inner layer, so that the stability of the impedance of the circuit board can be maintained in the testing and using processes.
The following detailed description refers to the accompanying drawings.
As shown in fig. 2, an inner core board is taken, and a first impedance line 11 and a second impedance line 31 are respectively manufactured on a first conductive layer 10 and a second conductive layer 30 of the inner core board. It will be appreciated that the first impedance line 11 is not a single line, but rather a generic term for all impedance lines on the first conductive layer 10 of the inner core. Similarly, the second resistive wire 31 is a generic term for all resistive wires on the second conductive layer 30 of the inner core. Further, when the circuit board is a multi-layer board with more than two layers, the first impedance line 11 and the second impedance line 31 are manufactured simultaneously with the inner layer pattern, so as to reduce the manufacturing process and save the cost. When the circuit board is a single-sided board or a double-sided board, the dielectric layer of the circuit board is changed into an inner core board, namely a sandwich structure of a conductive layer-dielectric layer-conductive layer, and the redundant conductive material of the conductive layer of the inner core board is removed through an inner pattern process flow, so that the inner dielectric 20 is exposed, and the required first impedance line 11 and second impedance line 31 are manufactured. The ends of the first impedance line 11 and the second impedance line 31 are designed with pads, and the pad positions are the contact points of the probes during impedance test. Preferably, the conductive material of the first conductive layer 10 and the second conductive layer 30 is copper.
After the impedance line is manufactured, please continue to refer to fig. 2, a first dielectric layer 40 and a first copper foil 50 are sequentially stacked on the first conductive layer 10, and a second dielectric layer 60 and a second copper foil 70 are sequentially stacked on the second conductive layer 30, and are pressed. And then, manufacturing a first blind hole 41 and a second blind hole 61 at the corresponding positions of the terminal pads of the impedance lines on the outer copper foil, namely the first copper foil 50 and the second copper foil 70, and removing the medium on the terminal pads of the impedance lines. Preferably, the first blind hole 41 and the second blind hole 61 are formed by carbon dioxide laser ablation. After the blind holes are formed, the circuit board semi-finished product is subjected to glue removal, cleaning and drying treatment, and residual glue residues of the first medium layer 40 and the second medium layer 60 are removed, so that the glue residues are prevented from affecting subsequent process steps. As shown in fig. 3, which is a top view of fig. 2, the terminal pads of the first resistance wire 11 are exposed through the first blind holes 41. Preferably, the size of the blind hole is 100% -110% of the designed size of the impedance line end pad to ensure that the impedance line end pad is fully exposed.
After the blind holes are manufactured, electroplating treatment is carried out, so that the blind holes are filled with metal copper, and metal blind holes are formed, thereby facilitating impedance testing. In one embodiment, the electroplating process comprises the steps of copper deposition, full-plate electroplating and pattern electroplating, wherein a layer of copper is deposited on the walls of the blind holes through the copper deposition step to realize hole wall conduction, and then metal copper is completely filled in the blind holes through the full-plate electroplating step and the pattern electroplating step. As shown in fig. 4 and 5, after the electroplating treatment, the first blind hole 41 and the second blind hole 61 are filled with metal copper, so that the terminal pads of the first impedance line 11 and the second impedance line 31 extend to the surface of the outer layer of the circuit board, and contact points of probes during impedance test are formed, so that the impedance test can be performed without changing the original impedance test mode, and the compatibility of the technology is improved. Furthermore, the electroplating treatment can be the electroplating treatment flow of the circuit board, and the electroplating of the blind holes and the thickening of the outer layer circuit are completed on the basis of not adding additional flow. As shown in fig. 4, the blind holes are filled up, and the first plating layer 52 and the second plating layer 72 are formed on the first outer layer line 51 and the second outer layer line 71, so that thickening of the outer layer lines is achieved.
According to the manufacturing method of the impedance line, the impedance line is moved into the inner layer through changing the circuit board structure, so that the copper thickness uniformity of the impedance line can be improved, the impedance line can be fully protected by the medium, the impedance line can be effectively prevented from being interfered by the external environment, and the stability of the impedance of the circuit board can be maintained in the testing and using processes. And then, the blind holes are manufactured and electroplated, so that the impedance lines of the inner layer can extend to the outer layer to form contact points through the blind holes, and thus, the impedance test can be carried out in the same mode as the original mode without changing the measurement mode and terminal data, thereby being beneficial to improving the working efficiency and reducing the cost. In the whole process, the original processing flow of the circuit board is fully utilized, the number of newly added flows is reduced to the greatest extent, the complex operation can be avoided, and the manufacturing cost is reduced. The technology fully utilizes the structure of the circuit board and the original processing flow of the circuit board, can effectively prevent the impedance line from being interfered by the external environment due to the protection effect of the dielectric layer, and has the advantages of simple process and stable impedance performance.
In a second aspect of the present application, there is provided an impedance line manufactured using the impedance line manufacturing method in the above embodiment. For specific limitation of the impedance line, please refer to the impedance line manufacturing method section, and detailed description thereof is omitted herein.
In a third aspect of the present application, a circuit board is provided, which includes the impedance line in the above embodiment. Specifically, the circuit board can be a single-sided board or a double-sided board, or can be a multi-layer board; can be a soft board, a hard board or a soft and hard combined board. The number of the impedance lines in the circuit board can be one or a plurality of. In summary, the number of layers, types of circuit boards, and the number of design of impedance lines in the circuit boards are not limited in this embodiment. It will be appreciated that other structures of the circuit board may be fabricated using other process steps to complete the overall circuit fabrication of the circuit board, before and/or after the impedance lines are fabricated, depending on the actual circuit design.
According to the circuit board, when the impedance line is manufactured, the impedance line is moved into the inner layer by changing the circuit board structure, so that the impedance line is fully protected by the medium, the impedance line can be effectively prevented from being interfered by the external environment, and the stability of the impedance of the circuit board can be maintained in the testing and using processes. And then, the blind holes are manufactured and electroplated, so that the impedance lines of the inner layer can extend to the outer layer to form contact points through the blind holes, and thus, the impedance test can be carried out in the same mode as the original mode without changing the measurement mode and terminal data, thereby being beneficial to improving the working efficiency and reducing the cost. In the whole process, the original processing flow of the circuit board is fully utilized, the number of newly added flows is reduced to the greatest extent, the complex operation can be avoided, and the manufacturing cost is reduced. The technology fully utilizes the structure of the circuit board and the original processing flow of the circuit board, can effectively prevent the impedance line from being interfered by the external environment due to the protection effect of the dielectric layer, and has the advantages of simple process and stable impedance performance.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples represent only a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (3)
1. A method of manufacturing an impedance line, comprising:
taking an inner core plate, wherein the inner core plate comprises a first conductive layer and a second conductive layer;
manufacturing an inner layer pattern on the inner layer core board, wherein manufacturing the inner layer pattern comprises manufacturing a first impedance line and a second impedance line on the first conductive layer and the second conductive layer respectively; the tail ends of the first impedance line and the second impedance line are provided with bonding pads;
sequentially stacking a first dielectric layer and a first copper foil on the first conductive layer;
sequentially superposing a second dielectric layer and a second copper foil on the second conductive layer;
and pressing;
after the lamination, blind holes are formed in the positions of the first copper foil and the second copper foil, which correspond to the bonding pads respectively, and the first dielectric layer and the second dielectric layer on the bonding pads are removed respectively;
then removing the gumming slag, cleaning and drying;
electroplating to fill the blind holes with metal copper to form metal blind holes;
the size of the blind hole is 100% -110% of the size of the bonding pad;
the manufacturing method of the blind hole is carbon dioxide laser ablation;
the electroplating treatment comprises the steps of copper deposition, full-plate electroplating and image electroplating.
2. An impedance line, characterized in that the impedance line is manufactured by the impedance line manufacturing method according to claim 1.
3. A circuit board comprising the impedance line of claim 2.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110273953.5A CN113194635B (en) | 2021-03-15 | 2021-03-15 | Impedance line manufacturing method, impedance line and circuit board |
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| CN202110273953.5A CN113194635B (en) | 2021-03-15 | 2021-03-15 | Impedance line manufacturing method, impedance line and circuit board |
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| CN113194635B true CN113194635B (en) | 2023-05-26 |
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| CN116033657B (en) * | 2022-12-26 | 2023-11-03 | 广东依顿电子科技股份有限公司 | Method, device and storage medium for automatically selecting double-line impedance line |
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| US10917968B1 (en) * | 2019-12-18 | 2021-02-09 | Google Llc | Package to printed circuit board transition |
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| JPH03129795A (en) * | 1989-03-20 | 1991-06-03 | Hitachi Seiko Ltd | Printed board and manufacture thereof |
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Address after: 341000 south of Weibang Road, industrial park, Xinfeng County, Ganzhou City, Jiangxi Province Patentee after: Ganzhou Kexiang electronic technology second factory Co.,Ltd. Address before: 341000 south of Weibang Road, industrial park, Xinfeng County, Ganzhou City, Jiangxi Province Patentee before: Jiangxi Yurui Electronic Technology Co.,Ltd. |