CN106340461A - Processing method of ultra-thin coreless encapsulation substrate and ultra-thin coreless encapsulation substrate structure - Google Patents
Processing method of ultra-thin coreless encapsulation substrate and ultra-thin coreless encapsulation substrate structure Download PDFInfo
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- CN106340461A CN106340461A CN201610864315.XA CN201610864315A CN106340461A CN 106340461 A CN106340461 A CN 106340461A CN 201610864315 A CN201610864315 A CN 201610864315A CN 106340461 A CN106340461 A CN 106340461A
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- 239000000758 substrate Substances 0.000 title claims abstract description 138
- 238000003672 processing method Methods 0.000 title abstract description 11
- 238000005538 encapsulation Methods 0.000 title abstract description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 80
- 239000011889 copper foil Substances 0.000 claims abstract description 74
- 238000000034 method Methods 0.000 claims abstract description 53
- 230000008093 supporting effect Effects 0.000 claims abstract description 43
- 229910000679 solder Inorganic materials 0.000 claims abstract description 20
- 238000000576 coating method Methods 0.000 claims abstract description 19
- 239000002131 composite material Substances 0.000 claims abstract description 17
- 239000011248 coating agent Substances 0.000 claims abstract description 15
- 238000004806 packaging method and process Methods 0.000 claims description 52
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 238000011282 treatment Methods 0.000 claims description 13
- 239000000853 adhesive Substances 0.000 claims description 12
- 230000001070 adhesive effect Effects 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910000831 Steel Inorganic materials 0.000 claims description 4
- 239000010959 steel Substances 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 239000011230 binding agent Substances 0.000 claims 1
- 238000005086 pumping Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 4
- 238000005728 strengthening Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 162
- 230000008569 process Effects 0.000 description 29
- 239000000047 product Substances 0.000 description 21
- 238000005530 etching Methods 0.000 description 18
- 238000009713 electroplating Methods 0.000 description 9
- 230000002787 reinforcement Effects 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000005553 drilling Methods 0.000 description 4
- 238000012858 packaging process Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000011152 fibreglass Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Geometry (AREA)
- Laminated Bodies (AREA)
Abstract
The invention relates to a processing method of an ultra-thin coreless encapsulation substrate. The method includes the following steps that: a laminated plate structure is provided, wherein the laminated plate structure comprise a central dielectric layer located at the middle of the laminated plate structure, as well as a composite copper foil layer, an insulating layer and an outer copper foil layer which are sequentially distributed from the central dielectric layer to the outer side of the laminated plate structure, wherein the composite copper foil layer comprises a supporting base layer and a detachable ultra-thin copper foil layer; via holes are produced, a first circuit layer is produced on the outer copper foil layer; solder resisting and surface coating processing are performed on the first circuit layer; the composite copper foil layer is separated, so that the ultra-thin coreless encapsulation substrate can be obtained; a supporting plate is bonded; a second circuit layer is produced on the ultra-thin copper foil layer, the second circuit layer is electrically connected with the first circuit layer through the via holes; and solder resisting and surface coating processing are performed on the second circuit layer. The present invention also provides a corresponding ultra-thin coreless encapsulation substrate structure. According to the processing method of the ultra-thin coreless encapsulation substrate provided by the technical schemes of the invention, by means of the protection and strengthening effects of the supporting plate, problems such as product fracture and damage caused by high possibility of deformation and warping due to insufficient strength of an ultra-thin coreless encapsulation substrate in the prior art can be solved.
Description
The present application claims priority from the chinese patent application entitled "method and structure for processing ultra-thin coreless package substrates" filed by the chinese patent office at 22/7/2016 under the serial No. 201610583868.8, the entire contents of which are incorporated herein by reference.
Technical Field
The invention relates to the technical field of packaging substrates, in particular to a processing method and a structure of an ultrathin coreless packaging substrate.
Background
The thinning of the electronic product promotes the growth of a coreless packaging substrate which is thinner than a cored packaging substrate and has more excellent electrical performance. Unlike the coreless package substrate, which does not include a core plate in the middle for supporting, high-density wiring is realized through a build-up process using only an insulating layer and a copper foil layer.
At present, the coreless packaging substrate sheet is mainly processed by a coreless substrate process, which generally comprises the following steps:
s1, manufacturing a bearing plate, wherein the surface layer of the bearing plate is a composite copper foil layer, and the composite copper foil layer comprises two separable structures, namely a supporting basal layer and an ultrathin copper foil layer;
s2, manufacturing two or more circuit layers on the surface of the ultrathin copper foil layer of the bearing plate through a layer adding process, and then separating two separable structures contained in the composite copper foil layer to obtain an ultrathin substrate structure comprising the ultrathin copper foil layer and the two or more circuit layers;
and S3, carrying out subsequent processing treatments such as etching, solder resisting, surface coating and the like on the ultrathin substrate structure to finally obtain a coreless packaging substrate finished product.
Practice shows that the existing coreless substrate process mainly has the following defects:
the ultrathin substrate structure obtained after separation is an ultrathin plate and is not supported by a core plate, so that the ultrathin substrate structure is insufficient in strength and easy to deform and warp, batch breakage is easily caused in subsequent solder resist manufacturing and surface coating processes, and the yield of products is influenced; and breakage occurs during the manufacturing process of the package substrate and the subsequent packaging process.
Disclosure of Invention
The embodiment of the invention provides a processing method of an ultrathin coreless packaging substrate and an ultrathin coreless packaging substrate structure, which are beneficial to solving the problems of product breakage and the like caused by insufficient strength and easy deformation and warping of the ultrathin coreless packaging substrate in the prior art.
The invention provides a processing method of an ultrathin coreless packaging substrate, which comprises the following steps: providing a laminated plate structure with symmetrical middle, wherein the laminated plate structure comprises a central dielectric layer positioned in the middle, a composite copper foil layer, an insulating layer and an outer copper foil layer which are sequentially arranged from the central dielectric layer to the outer side, and the composite copper foil layer comprises a supporting basal layer contacted with the central dielectric layer and an ultrathin copper foil layer contacted with the insulating layer and separated from the supporting basal layer; manufacturing a via hole, and manufacturing a first circuit layer on the outer copper foil layer, wherein the first circuit layer is electrically connected with the ultrathin copper foil layer through the via hole; carrying out solder mask and surface coating treatment on the first circuit layer; separating the ultrathin copper foil layer from the support substrate layer to obtain an ultrathin coreless packaging substrate, wherein the ultrathin coreless packaging substrate comprises the ultrathin copper foil layer, the insulating layer and the first circuit layer; bonding a supporting plate on the ultrathin coreless packaging substrate, wherein the supporting plate is positioned on the surface where the first circuit layer is positioned; manufacturing a second circuit layer on the ultrathin copper foil layer, wherein the second circuit layer is electrically connected with the first circuit layer through the via hole; and carrying out solder mask and surface coating treatment on the second circuit layer.
A second aspect of the present invention provides an ultra-thin coreless package substrate structure, comprising: the package comprises an ultrathin coreless package substrate and a support plate bonded on the ultrathin coreless package substrate; the coreless packaging substrate comprises an insulating layer, a first circuit layer and a second circuit layer, wherein the first circuit layer and the second circuit layer are arranged on two sides of the insulating layer, and the second circuit layer is electrically connected with the first circuit layer through a via hole; the supporting plate is located on the surface where the first circuit layer is located.
As can be seen from the above, in some feasible embodiments of the present invention, after the composite copper foil layer is separated, the support plate is bonded to the obtained ultra-thin coreless package substrate, and the support effect of the support plate is utilized to improve the strength of the ultra-thin coreless package substrate, so as to prevent the substrate from deforming and warping. Therefore, in the subsequent micro-etching, solder resist and surface coating, as well as the manufacturing of the packaging substrate and the subsequent packaging process, the problems of plate breakage, yield reduction and the like caused by the reasons of over-thin substrate, over-low strength, easy deformation and warping and the like can be avoided or reduced.
In summary, the method provided by the embodiment of the invention utilizes the protection and reinforcement effects of the supporting plate, and is helpful for solving the problems of product breakage and the like caused by insufficient strength and easy deformation and warping of the ultrathin coreless packaging substrate in the prior art. The ultrathin coreless packaging substrate structure provided by the embodiment of the invention has the advantages of convenience in processing, convenience in transportation and storage and the like due to the protection and the reinforcement of the supporting plate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Figure 1 is a flow chart illustrating a method of processing an ultra-thin coreless package substrate according to an embodiment of the present invention;
FIGS. 2a-2i are schematic diagrams of various stages in processing an ultra-thin coreless package substrate according to an embodiment of the present invention;
figure 2j is a schematic diagram of an ultra-thin coreless package substrate structure according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a processing method of an ultrathin coreless packaging substrate, which is beneficial to solving the problems of product breakage and the like caused by insufficient strength and easy deformation and warping of the ultrathin coreless packaging substrate in the prior art. The embodiment of the invention also provides a corresponding ultrathin coreless packaging substrate structure.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following are detailed descriptions of the respective embodiments.
The first embodiment,
Referring to fig. 1, an embodiment of the invention provides a method for processing an ultra-thin coreless package substrate, which is applied in the field of package substrates, including but not limited to the field of integrated circuit packages such as memory modules and micro-electro-mechanical systems. The method of the embodiment of the invention is beneficial to improving the processing capacity of the coreless packaging substrate product, can be used for processing the coreless packaging substrate product with the thickness of more than 100 microns, and particularly can be used for processing the coreless packaging substrate product with the thickness of less than 100 microns, is beneficial to reducing the product breakage, improves the product yield and meets the requirement of mass production.
Referring to fig. 1, a method according to an embodiment of the invention may include:
101. the laminated plate structure comprises a central dielectric layer positioned in the middle, and a composite copper foil layer, an insulating layer and an outer copper foil layer are sequentially arranged on the outer side of the central dielectric layer, wherein the composite copper foil layer comprises a supporting basal layer in contact with the central dielectric layer and an ultrathin copper foil layer which is in contact with the insulating layer and can be separated from the supporting basal layer.
Referring to fig. 2a, in the embodiment, a prepreg (PP sheet) and a copper foil may be used for lamination to manufacture a stacked structure. The laminated plate structure takes the central medium layer 21 as the center and is of a middle symmetrical structure, and can comprise the following components from the outer side to the inner side in sequence: outer copper foil layer 24, insulating layer 23, composite copper foil layer 22, central dielectric layer 21.
Both the central dielectric layer 21 and the insulating layer 23 may be prepregs, and optionally, the central dielectric layer may also be a glass fiber board. Alternatively, the insulating layer 23 may be a prepreg having a thickness of not more than 30 μm. Alternatively, the outer copper foil layer 24 may be a copper foil layer having a thickness of about 1/3 ounces (Oz), or a copper foil layer having a thickness of no more than 15 μm or 10 μm.
Wherein the composite copper foil layer 22 comprises two separable structures, a support substrate layer 2201 and an ultra-thin copper foil layer 2202. Wherein the support substrate layer 2201 is in contact with the central dielectric layer 21 and the ultra-thin copper foil layer 2202 is in contact with the insulating layer 23. The support substrate layer 2201 and ultra-thin copper foil layer 2202 may then be separated as desired. Alternatively, the ultra-thin copper foil layer 2202 may be a copper foil layer having a thickness of not more than 10 μm or even not more than 5 μm.
102. And manufacturing a through hole.
In this step, a via hole for interlayer conduction is formed, and as shown in fig. 2b, a via hole 25 may be formed on the inner layer at the side where the outer copper foil layer 24 is located, so that the outer copper foil layer 24 and the ultra-thin copper foil layer 2202 may be electrically connected through the via hole 25.
In some embodiments, the via hole 25 may be formed by a laser drilling and hole metallization process, which may specifically include: firstly, a blind hole reaching the ultra-thin copper foil layer 2202 is processed from a design position on one surface of the outer copper foil layer 24 by using a laser drilling process, wherein the design position may be firstly subjected to etching windowing, the insulating layer 23 is exposed and then subjected to laser drilling, or the design position may be directly subjected to laser drilling. Then, a thin copper deposition layer is formed on the wall of the blind hole by a copper deposition process to serve as the basis of electroplating; finally, filling and electroplating are carried out on the blind holes to prepare conducting holes 25; wherein, the hole filling electroplating can adopt a full-plate electroplating process or a pattern electroplating process. Alternatively, one or more through holes 25 may be formed in this step.
103. And manufacturing a first circuit layer on the outer copper foil layer, wherein the first circuit layer is electrically connected with the ultrathin copper foil layer through a via hole.
In this step, an etching process is used to process the circuit layer, as shown in fig. 2c, the etching process may be used to perform etching on the outer copper foil layer 24 to form the first circuit layer 26, and the specific processing process may include: pasting a film, exposing, developing, etching and removing the film; wherein,
a film formed by attaching a resist film, such as a dry film resist, to the surface of the outer copper foil layer 24;
exposing, namely transferring the circuit pattern on the film or other transparent materials to the corrosion resistant film by using ultraviolet rays emitted by an exposure machine;
developing, namely, removing the non-photopolymerized resist film by using a developing solution for treatment, and defining a circuit pattern on the surface of the outer copper foil layer 24 by using the residual resist film;
etching, namely etching and removing the outer copper foil layer 24 which is not protected by the corrosion-resistant mold;
the film removal is to remove the resist film by using a chemical solution.
Through the above steps, the portion of the outer copper foil layer 24 that is not etched away forms the first circuit layer 26.
Optionally, the height of the first circuit pattern 26 is between 10 μm and 15 μm; alternatively, the first line pattern 26 may be a fine line having a line width of not more than 15 μm and a line pitch of not more than 15 μm.
104. And carrying out solder mask and surface coating treatment on the first circuit layer.
As shown in fig. 2d, in this step, the first circuit pattern 26 may be subjected to a solder resist process and a surface coating process; wherein the solder resist process is to dispose a solder resist layer 27, such as green oil, over the first circuit pattern 26 to protect the first circuit pattern 26 and the insulating layer 23; the surface coating process is to form a film layer on the portion of the first circuit pattern 26, which needs to be exposed, to improve the surface performance, such as electroplating hard gold or soft gold to form a gold plating layer on the surface of the pad, or electroplating to form a palladium plating layer.
105. And separating the ultrathin copper foil layer from the supporting basal layer to obtain the ultrathin coreless packaging substrate.
In this step, interlayer separation of the composite copper foil layer is performed, that is, the ultra-thin copper foil layer is separated from the support substrate layer, so as to obtain the ultra-thin coreless package substrate 30 shown in fig. 2e, where the ultra-thin coreless package substrate 30 is also a semi-finished product. As shown in fig. 2e, the semi-finished ultra-thin coreless package substrate 30 includes the ultra-thin copper foil layer 2202, the insulation layer 23, and the first circuit layer 26; the method can also comprise the following steps: a via 25 connecting the first wiring layer 26 and the ultra-thin copper foil layer 2202.
Next, the ultra-thin copper foil layer 2202 needs to be removed by microetching, the first circuit layer 26 is exposed, and the finished ultra-thin coreless package substrate 30 can be obtained after the solder mask and the surface coating treatment are performed on the first circuit layer 26. However, since the ultra-thin coreless package substrate 30 is too thin, for example, not more than 100 μm, and has no core support, it is easy to warp and deform, and it is very easy to break in the subsequent processing steps such as micro-etching, solder resist and surface coating, and the subsequent packaging and transportation processes, and even the subsequent processes cannot be performed.
106. And bonding a supporting plate on the ultrathin coreless packaging substrate, wherein the supporting plate is positioned on the surface where the first circuit layer is positioned.
To solve the above problem, the supporting board 40 is used to reinforce and protect the ultra-thin coreless package substrate 30 in the embodiment of the present invention. Thus, in this step, as shown in fig. 2f and 2g, a support plate 40 may be bonded to the ultra-thin coreless package substrate 30, the support plate 40 being located on a side of the first circuit layer 26, referred to herein as the backside of the ultra-thin coreless package substrate 30 for ease of description; that is, the support plate 40 is bonded to the backside of the ultra-thin coreless package substrate 30 for backside reinforcement and protection.
In the specific implementation process, the ultra-thin coreless package substrate 30 is first separated into two parts, the edge auxiliary pattern area 31 of the ultra-thin coreless package substrate 30 product is used for arranging the adhesive 50 after being turned over, or the edge auxiliary pattern area 31 is sealed by the adhesive 50, then the support plate 40 is used for carrying, the support plate 40 is bonded on the ultra-thin coreless package substrate 30 by the adhesive, the ultra-thin coreless package substrate and the support plate are bonded into a whole, and the bonding positions of the ultra-thin coreless package substrate and the support plate are located in the peripheral edge auxiliary pattern area 31.
Optionally, the thickness of the adhesive 50 used is between 5 and 15 μm; alternatively, the adhesive completely seals the edge auxiliary pattern region 31 of the back surface of the substrate; optionally, the bonding process of the supporting plate 40 is performed under a high temperature and high pressure vacuum condition, wherein a high temperature condition with a temperature below 200 degrees, such as 100 to 200 degrees, can be used to ensure that the bottom supporting plate 40 and the ultra-thin coreless packaging substrate 30 are tightly attached without bubbles.
Wherein the adhesive bonding areas are not used during the encapsulation process and can be removed when the product is cut into individual pieces. Optionally, the supporting plate is a copper-clad plate, a steel plate or a copper plate, or other sheet materials with strength, rigidity and expansion coefficient matched with a Printed Circuit Board (PCB); that is, whether a conductor or an insulator, the circuit board may be considered as a support plate as long as the expansion coefficient and strength are sufficient and the circuit board supports a sheet-like material that can be processed. Optionally, the adhesive is an adhesive based on epoxy resin or polyimide.
107. And manufacturing a second circuit layer on the ultrathin copper foil layer, wherein the second circuit layer is electrically connected with the first circuit layer through a via hole.
In this step, an etching process is used for processing the outer layer pattern, as shown in fig. 2h, the etching process may be used for etching the ultra-thin copper foil layer 2202 to form the second circuit layer 28, and the specific processing process may include: pasting a film, exposing, developing, etching and removing the film; wherein,
a film formed by attaching a resist film, such as a dry film resist, to the surface of the ultra-thin copper foil layer 2202;
exposing, namely transferring the circuit pattern on the film or other transparent materials to the corrosion resistant film by using ultraviolet rays emitted by an exposure machine;
developing, namely, removing the non-photopolymerized resist film by using a developer solution for treatment, and defining a line pattern on the surface of the ultrathin copper foil layer 2202 by using the residual resist film;
etching, which is to etch and remove the ultra-thin copper foil layer 2202 not protected by the resist mask;
the film removal is to remove the resist film by using a chemical solution.
Through the above steps, the portion of the ultra-thin copper foil layer 2202 that is not removed by etching forms the second circuit layer 28.
Optionally, the height of the second circuit layer 28 is between 10 μm and 15 μm; alternatively, the second wiring layer 28 may be a fine wiring having a line width of not more than 15 μm and a line pitch of not more than 15 μm.
In the step, as the support plate is arranged for processing, the whole plate has enough strength and thickness, and cannot be easily deformed or warped, so that the plate can be prevented or reduced from being broken and damaged, and the yield is improved.
108. And performing resistance welding and surface coating treatment on the second circuit layer.
In this step, as shown in fig. 2i, the second circuit layer 28 may be subjected to solder resist treatment and surface coating treatment; wherein the solder resist process is to dispose a solder resist layer 27, such as green oil, on the second circuit layer 28 to protect the second circuit layer 28 and the insulating layer 23; the surface coating process is to form a film layer on the portion of the second circuit layer 28, which needs to be exposed, to improve the surface performance, such as electroplating hard gold or soft gold to form a gold plating layer on the surface of the pad, or electroplating to form a palladium plating layer. In the step, as the support plate is arranged for processing, the whole plate has enough strength and thickness, and cannot be easily deformed or warped, so that the plate can be prevented or reduced from being broken and damaged, and the yield is improved.
Through the above steps, the processing of the ultra-thin coreless package substrate is basically completed. Unlike cored package substrates, cored package substrates have a core sheet, such as a fiberglass sheet, in the center, while ultra-thin coreless package substrates have only a thin insulating layer, such as a prepreg, in the center.
In the actual processing process, a makeup process is usually adopted, that is, a plurality of small package substrates are combined on one large substrate, for this reason, the method in the embodiment of the present invention may optionally further include the following steps:
and processing one or more positioning holes penetrating through the ultrathin coreless packaging substrate and the supporting plate in the edge auxiliary pattern area of the ultrathin coreless packaging substrate.
As shown in fig. 2j, in this step, a hole 60 may be drilled in the bonding area, i.e., the edge assist pattern area, and machined into a predetermined shape by a milling machine for use in the packaging factory, and the hole 60 is typically a plurality of holes, typically extending through the ultra-thin coreless package substrate and the support plate.
The mosaic structure can be subsequently cut based on the positioning holes 60 to obtain a single finished ultrathin coreless package substrate 30, wherein the support plate 40 can be automatically removed by dropping when the product is cut into single finished products.
The method of the embodiment of the present invention is described above by taking the processing of the double-sided board as an example with reference to the drawings. The method can be used for processing double-sided boards, namely ultrathin coreless packaging substrates comprising two circuit layers; the method can also be used for processing multilayer boards, namely ultrathin coreless packaging substrates comprising multilayer circuit layers; the method can ensure the strength of the product in the processing process, improve the processing yield, reduce the product breakage and realize the functions of the product.
Taking the processing of double-sided boards as an example, the method of the embodiment of the invention can be used for processing ultra-thin coreless packaging substrate products with the thickness of less than 100 μm, such as ultra-thin coreless packaging substrate products with the thickness of less than 80 μm. Alternatively, the ultra-thin coreless package substrate described herein may be a coreless package substrate having a thickness of no more than 100 μm, or no more than 80 μm. However, the coreless package substrate with a thickness of about 100 μm or less cannot be processed by the conventional processing method because of its thinness, too low strength, and severe deformation and warpage, and the conventional processing method can only process the coreless package substrate with a thickness of several hundreds of micrometers, cannot ensure the level of breakage, and has a low yield.
As can be seen, in some possible embodiments of the present invention, after the composite copper foil layer is separated, the support plate is bonded to the obtained ultra-thin coreless package substrate, so as to provide a novel ultra-thin coreless package substrate structure with the support plate. The supporting effect of the supporting plate is utilized, the strength of the ultrathin coreless packaging substrate is improved, and the substrate can be prevented from deforming and warping. Therefore, in the subsequent treatment processes of micro-etching, solder resistance, surface coating and the like, the protection and the reinforcement of the supporting plate in the manufacturing process of the packaging substrate and the subsequent packaging process, the problems of plate breakage, yield reduction and the like caused by the reason that the substrate is too thin, the strength is too low, the substrate is easy to deform and warp and the like can be avoided or reduced.
In summary, the method provided by the embodiment of the invention utilizes the protection and reinforcement effects of the supporting plate, and is helpful for solving the problems of product breakage and the like caused by insufficient strength and easy deformation and warping of the ultrathin coreless packaging substrate in the prior art. The ultrathin coreless packaging substrate structure provided by the embodiment of the invention has the advantages of convenience in processing, convenience in transportation and storage and the like due to the protection and the reinforcement of the supporting plate.
Example II,
Referring to fig. 2j, a second embodiment of the invention further provides an ultra-thin coreless package substrate structure, which can be processed by the first embodiment of the invention.
As shown in fig. 2j, the ultra-thin coreless package substrate structure may include:
an ultra-thin coreless package substrate 30, and a support plate 40 bonded to the ultra-thin coreless package substrate;
the coreless package substrate 30 comprises an insulating layer 23, and a first circuit layer 26 and a second circuit layer 28 which are arranged on two sides of the insulating layer, wherein the second circuit layer 28 is electrically connected with the first circuit layer 26 through a via hole 25; the supporting board 40 is located on the side of the first circuit layer 26.
Optionally, the supporting plate is a copper-clad plate, a steel plate or a copper plate, or other materials with strength and expansion coefficient matched with the ultra-thin coreless packaging substrate 30.
Optionally, the ultra-thin coreless package substrate 30 and the supporting plate 40 are bonded by an adhesive, which is an adhesive based on epoxy resin or polyimide.
Optionally, the ultra-thin coreless package substrate has a thickness of no greater than 100 microns or no greater than 80 microns.
Optionally, the thickness of the first circuit layer 26 is not greater than 15 microns, the thickness of the second circuit layer 28 is not greater than 15 microns, and the thickness of the insulating layer 23 is not greater than 25 or 30 microns.
In the above, the ultra-thin coreless package substrate structure provided by the embodiment of the present invention is introduced, and reference may be made to the description in the first embodiment for a more detailed description of the ultra-thin coreless package substrate structure.
In view of the above, some possible embodiments of the present invention provide a new ultra-thin coreless package substrate structure with a support plate. The supporting effect of the supporting plate is utilized, the strength of the ultrathin coreless packaging substrate is improved, and the substrate can be prevented from deforming and warping. Therefore, in the processing processes of micro-etching, solder resistance, surface coating and the like, the manufacturing process of the packaging substrate and the subsequent packaging process, due to the protection and the reinforcement of the supporting plate, the problems of plate breakage, yield reduction and the like caused by the reason that the substrate is too thin, the strength is too low, the substrate is easy to deform and warp and the like can be avoided or reduced. In summary, the ultra-thin coreless package substrate structure provided by the embodiment of the invention has the advantages of high strength, difficulty in deformation and warpage, convenience in processing, convenience in transportation and storage and the like due to the protection and the reinforcement of the supporting plate.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.
The processing method and structure of the ultra-thin coreless package substrate provided by the embodiment of the present invention are described in detail, but the above description of the embodiment is only for assisting understanding of the method and the core idea of the present invention, and should not be construed as limiting the present invention. Those skilled in the art should also appreciate that various modifications and substitutions can be made without departing from the scope of the present invention.
Claims (10)
1. A method for processing an ultra-thin coreless package substrate, comprising:
providing a laminated plate structure with symmetrical middle, wherein the laminated plate structure comprises a central dielectric layer positioned in the middle, a composite copper foil layer, an insulating layer and an outer copper foil layer which are sequentially arranged from the central dielectric layer to the outer side, and the composite copper foil layer comprises a supporting basal layer contacted with the central dielectric layer and an ultrathin copper foil layer contacted with the insulating layer and separated from the supporting basal layer;
manufacturing a via hole, and manufacturing a first circuit layer on the outer copper foil layer, wherein the first circuit layer is electrically connected with the ultrathin copper foil layer through the via hole;
carrying out solder mask and surface coating treatment on the first circuit layer;
separating the ultrathin copper foil layer from the support substrate layer to obtain an ultrathin coreless packaging substrate, wherein the ultrathin coreless packaging substrate comprises the ultrathin copper foil layer, the insulating layer and the first circuit layer;
bonding a supporting plate on the ultrathin coreless packaging substrate, wherein the supporting plate is positioned on the surface where the first circuit layer is positioned;
manufacturing a second circuit layer on the ultrathin copper foil layer, wherein the second circuit layer is electrically connected with the first circuit layer through the via hole;
and carrying out solder mask and surface coating treatment on the second circuit layer.
2. The method of claim 1, wherein bonding a support plate on the ultra-thin coreless package substrate comprises:
and arranging an adhesive in the auxiliary pattern area at the edge of the ultrathin coreless packaging substrate, and adhering a support plate on the ultrathin coreless packaging substrate by using the adhesive.
3. The method of claim 2,
the operation of bonding the supporting plate is carried out under the condition of high temperature and high pressure vacuum pumping.
4. The method of claim 1, further comprising:
and processing a positioning hole penetrating through the ultrathin coreless packaging substrate and the supporting plate in the edge auxiliary pattern area of the ultrathin coreless packaging substrate.
5. The method of claim 1,
the supporting plate is a copper-clad plate, a steel plate or a copper plate.
6. The method of claim 1,
the binder is an adhesive based on epoxy resin or polyimide.
7. The method of claim 1, wherein:
the thickness of the ultra-thin coreless packaging substrate is not more than 100 microns.
8. An ultra-thin coreless package substrate structure, comprising:
the package comprises an ultrathin coreless package substrate and a support plate bonded on the ultrathin coreless package substrate;
the coreless packaging substrate comprises an insulating layer, a first circuit layer and a second circuit layer, wherein the first circuit layer and the second circuit layer are arranged on two sides of the insulating layer, and the second circuit layer is electrically connected with the first circuit layer through a via hole;
the supporting plate is located on the surface where the first circuit layer is located.
9. The ultra-thin coreless package substrate structure of claim 8, wherein:
the supporting plate is a copper-clad plate, a steel plate or a copper plate.
10. The ultra-thin coreless package substrate structure of claim 8, wherein:
the thickness of the ultra-thin coreless packaging substrate is not more than 100 microns.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107089641A (en) * | 2017-03-07 | 2017-08-25 | 深南电路股份有限公司 | The preparation method and Related product of a kind of ultra-thin packed substrate |
| CN108269766A (en) * | 2017-12-20 | 2018-07-10 | 深南电路股份有限公司 | A kind of ultra-thin packed substrate structure and its processing method |
| CN112385022A (en) * | 2018-07-06 | 2021-02-19 | 高通股份有限公司 | High density interconnect in Embedded Trace Substrate (ETS) including core layer |
| CN113194635A (en) * | 2021-03-15 | 2021-07-30 | 江西宇睿电子科技有限公司 | Impedance line manufacturing method, impedance line and circuit board |
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| CN114464720A (en) * | 2022-01-27 | 2022-05-10 | 广东芯华微电子技术有限公司 | LED substrate structure, preparation method thereof and micro LED packaging structure |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090236135A1 (en) * | 2008-03-19 | 2009-09-24 | Shinko Electric Industries Co., Ltd. | Multilayer wiring substrate and method of manufacturing the same |
| CN102054710A (en) * | 2009-11-06 | 2011-05-11 | 欣兴电子股份有限公司 | Coreless layer capsulation substrate and manufacturing method thereof |
| CN104168726A (en) * | 2013-05-17 | 2014-11-26 | 深南电路有限公司 | Coreless substrate processing method |
| CN204792778U (en) * | 2015-02-17 | 2015-11-18 | 日月光半导体制造股份有限公司 | Semiconductor substrate structure and semiconductor package |
| CN105493269A (en) * | 2013-08-30 | 2016-04-13 | 苹果公司 | Ultra fine pitch PoP coreless package |
-
2016
- 2016-09-28 CN CN201610864315.XA patent/CN106340461B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090236135A1 (en) * | 2008-03-19 | 2009-09-24 | Shinko Electric Industries Co., Ltd. | Multilayer wiring substrate and method of manufacturing the same |
| CN102054710A (en) * | 2009-11-06 | 2011-05-11 | 欣兴电子股份有限公司 | Coreless layer capsulation substrate and manufacturing method thereof |
| CN104168726A (en) * | 2013-05-17 | 2014-11-26 | 深南电路有限公司 | Coreless substrate processing method |
| CN105493269A (en) * | 2013-08-30 | 2016-04-13 | 苹果公司 | Ultra fine pitch PoP coreless package |
| CN204792778U (en) * | 2015-02-17 | 2015-11-18 | 日月光半导体制造股份有限公司 | Semiconductor substrate structure and semiconductor package |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107089641A (en) * | 2017-03-07 | 2017-08-25 | 深南电路股份有限公司 | The preparation method and Related product of a kind of ultra-thin packed substrate |
| CN108269766A (en) * | 2017-12-20 | 2018-07-10 | 深南电路股份有限公司 | A kind of ultra-thin packed substrate structure and its processing method |
| CN112385022A (en) * | 2018-07-06 | 2021-02-19 | 高通股份有限公司 | High density interconnect in Embedded Trace Substrate (ETS) including core layer |
| CN112385022B (en) * | 2018-07-06 | 2021-11-30 | 高通股份有限公司 | High density interconnect in Embedded Trace Substrate (ETS) including core layer |
| CN113194635A (en) * | 2021-03-15 | 2021-07-30 | 江西宇睿电子科技有限公司 | Impedance line manufacturing method, impedance line and circuit board |
| CN113194635B (en) * | 2021-03-15 | 2023-05-26 | 江西宇睿电子科技有限公司 | Impedance line manufacturing method, impedance line and circuit board |
| CN114464721A (en) * | 2022-01-27 | 2022-05-10 | 广东芯华微电子技术有限公司 | LED substrate structure, preparation method thereof and micro LED packaging structure |
| CN114464720A (en) * | 2022-01-27 | 2022-05-10 | 广东芯华微电子技术有限公司 | LED substrate structure, preparation method thereof and micro LED packaging structure |
| CN114464722A (en) * | 2022-01-27 | 2022-05-10 | 广东芯华微电子技术有限公司 | LED substrate structure, preparation method thereof and micro LED packaging structure |
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