CN113192842A - CoolMOS device manufacturing method - Google Patents
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- CN113192842A CN113192842A CN202110545584.0A CN202110545584A CN113192842A CN 113192842 A CN113192842 A CN 113192842A CN 202110545584 A CN202110545584 A CN 202110545584A CN 113192842 A CN113192842 A CN 113192842A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 77
- 229920005591 polysilicon Polymers 0.000 claims abstract description 51
- 238000002347 injection Methods 0.000 claims abstract description 22
- 239000007924 injection Substances 0.000 claims abstract description 22
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 14
- 239000001301 oxygen Substances 0.000 claims abstract description 14
- 238000001259 photo etching Methods 0.000 claims abstract description 13
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000001465 metallisation Methods 0.000 claims abstract description 8
- 238000012545 processing Methods 0.000 claims abstract description 7
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 4
- 239000013256 coordination polymer Substances 0.000 claims abstract description 4
- 230000008021 deposition Effects 0.000 claims abstract description 4
- 238000010992 reflux Methods 0.000 claims abstract description 4
- 238000012360 testing method Methods 0.000 claims abstract description 4
- 230000000903 blocking effect Effects 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 238000002161 passivation Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 210000003371 toe Anatomy 0.000 claims 2
- PDOITGSYNUEMCR-UHFFFAOYSA-N tetraethylazanium;silicate Chemical compound [O-][Si]([O-])([O-])[O-].CC[N+](CC)(CC)CC.CC[N+](CC)(CC)CC.CC[N+](CC)(CC)CC.CC[N+](CC)(CC)CC PDOITGSYNUEMCR-UHFFFAOYSA-N 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 7
- 238000000407 epitaxy Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 2
- HWCKGOZZJDHMNC-UHFFFAOYSA-M tetraethylammonium bromide Chemical compound [Br-].CC[N+](CC)(CC)CC HWCKGOZZJDHMNC-UHFFFAOYSA-M 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The invention discloses a CoolMOS device manufacturing method, which comprises the following steps of 1) field oxide growth, opening a voltage division ring and injecting and annealing the voltage division ring; 2) opening an active region; 3) processing a deep groove in the active region; 4) growing gate oxide, depositing polysilicon gate, photoetching and etching; 5) performing PWELL well layer injection annealing; 6) performing source region N + photoetching, N + injection and annealing; 7) TEOS deposition, growth of passivating borophosphosilicate glass under aluminum, and reflux; 8) photoetching and etching lead holes; 9) front side metallization is formed; 10) thinning; 11) back metallization is formed; 12) and (6) CP testing and warehousing. The invention belongs to the technical field of semiconductor manufacturing, and particularly provides a CoolMOS device manufacturing method for etching a deep trench in a PWELL, depositing TEOS (tetraethyl orthosilicate) thick oxygen in the trench, and realizing high-voltage output and internal resistance reduction under a thick epitaxial condition by utilizing a polycrystalline field plate shielding principle and a bottom PN junction principle.
Description
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a method for manufacturing a CoolMOS device.
Background
The prior COOLMOS structure design mainly comprises two types, one type is a P column structure formed by adopting a processing technology of multiple epitaxy and multiple photoetching, the other type is a P column structure formed by adopting deep groove filling and allowing P type epitaxy, the two methods have the characteristics, the prior two methods realize high-voltage VDMOS (vertical double-diffused metal oxide semiconductor) of a thick epitaxy layer by utilizing a P column and N type current channel charge balancing method, the aim of low internal resistance is realized, but the common characteristic is epitaxial growth, the cost is high, the processing period is long, the requirement on a production line is high, only a plurality of domestic production lines can process the VDMOS, strict patent protection is provided, and the design and processing threshold is higher.
Disclosure of Invention
In order to solve the existing problems, the invention provides a CoolMOS device manufacturing method which comprises the steps of etching a deep groove in a PWELL, depositing TEOS (tetraethyl orthosilicate) thick oxygen in the deep groove, etching out a TOES (tungsten-oxygen-doped silicon) film at the bottom of the deep groove by adopting plasma etching, then injecting a P-type impurity at the bottom, depositing polycrystalline silicon, etching back the polycrystalline silicon, opening a hole of the polycrystalline silicon and a PWELL well layer to form short circuit, equivalently, short circuit between the polycrystalline silicon in the groove and a source electrode S is grounded, and realizing high-voltage output under a thick epitaxial condition and reducing internal resistance by utilizing a polycrystalline field plate shielding principle and a bottom PN junction principle.
The technical scheme adopted by the invention is as follows: a CoolMOS device manufacturing method comprises the following steps:
1) growing field oxygen, opening a voltage division ring, and injecting and annealing the voltage division ring;
2) opening an active region;
3) processing a deep groove in the active region, depositing TEOS (tetraethyl orthosilicate) thick oxygen in the deep groove to form a TOES (tungsten-doped silicon) film, growing and curing the TOES film, carrying out plasma etching, injecting P-type impurities at the bottom of the deep groove, depositing a source groove polysilicon gate in the deep groove, and etching back the source groove polysilicon gate;
4) growing gate oxide, depositing a polysilicon gate, photoetching the polysilicon gate and etching the polysilicon gate;
5) performing PWELL well layer injection annealing;
6) performing source region N + photoetching, N + injection and annealing;
7) TEOS deposition, growth of passivating borophosphosilicate glass under aluminum, and reflux;
8) photoetching and etching lead holes;
9) front side metallization is formed;
10) thinning;
11) back metallization is formed;
12) and (6) CP testing and warehousing.
A CoolMOS device sequentially comprises a back metal layer, an N + substrate layer, an N-type high-concentration current layer, an insulating layer and a front metal layer from bottom to top, wherein the upper surface of the N-type high-concentration current layer comprises a polycrystalline silicon gate region and a polycrystalline OPEN region which are sequentially arranged at intervals, contact holes are formed in the lower surface of the front metal layer and are arranged at the lower surface of the front metal layer at intervals, an aluminum lower passivation layer is arranged on the inner upper wall of each contact hole, a polycrystalline silicon gate layer is filled in the aluminum lower passivation layer and is arranged in the polycrystalline silicon gate region, PWELL well layers are embedded in the upper surface of the N-type high-concentration current layer, the PWELL well layers are arranged at the upper surface of the N-type high-concentration current layer at equal intervals, the middle of each PWELL well layer is arranged in the polycrystalline OPEN region, two sides of each polycrystalline silicon gate layer are arranged in the polycrystalline silicon gate region, each polycrystalline silicon gate layer is arranged between two adjacent PWELL well layers, and gate oxide layers are arranged between each PWELL well layer and the N well layers, the polysilicon OPEN region is internally provided with a plurality of groups of opening regions, the opening regions are internally provided with N + injection blocking regions, the PWELL well layer is penetrated and provided with a deep groove, the lower end of the deep groove extends into the N-type high-concentration current layer, the deep groove is arranged at the N + injection blocking region and is internally filled with a source groove polysilicon gate, TEOS (tetraethyl orthosilicate) thick oxygen is arranged between the source groove polysilicon gate and the deep groove, the source groove polysilicon gates are uniformly distributed in the N + injection blocking regions at equal intervals, the N + layer is arranged outside the N + injection blocking region, the polysilicon OPEN region is opened through the opening regions, the opening regions contain the N-type high-concentration current layer, the PWELL well layer and the source groove polysilicon gate during opening, the bottom of the deep groove is provided with a P + layer, the upper wall of the P + layer penetrates through the deep groove polysilicon gate to be connected with the deep groove polysilicon gate, and the bottom wall of the P + layer is connected with the N-type high-concentration current layer, and the upper end of the deep groove is symmetrically provided with N + layers at one side close to the polysilicon gate layer, the N + layers are respectively connected with the source groove polysilicon gate and the PWELL well layer, and the source groove polysilicon gate is in short connection with the PWELL well layer.
Furthermore, two rows of deep trenches are arranged in each polycrystalline OPEN region, and the N + layers are symmetrically arranged on two sides of two adjacent rows of deep trenches.
By adopting the scheme, the invention has the following beneficial effects: the invention relates to a CoolMOS device manufacturing method, which comprises the steps of etching a deep groove in a PWELL well layer, depositing TEOS thick oxygen in the deep groove to form a TOES film, etching the bottom TOES film completely by adopting plasma etching, injecting bottom P-type impurities, depositing polycrystalline silicon, etching back the polycrystalline silicon, opening holes of the polycrystalline silicon and the PWELL well layer to form short circuits, equivalently, the polycrystalline silicon in the groove is in short circuit connection with a source electrode S to be grounded, and realizing high-voltage output under the condition of thick epitaxy and reducing internal resistance by utilizing a polycrystalline field plate shielding principle and a bottom PN junction principle.
Drawings
FIG. 1 is a schematic structural diagram of a CoolMOS device according to the present invention;
FIG. 2 is a schematic cross-sectional view of an N-type high-concentration current layer of a CoolMOS device according to the present invention.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings: 1. the structure of the solar cell comprises a back metal layer, a 2 and N + substrate layer, a 3 and N type high-concentration current layer, a 4, a gate oxide layer, a 5, a polycrystalline silicon gate region, a 6 polycrystalline OPEN region, a 7 and aluminum lower passivation layer, a 8 and polycrystalline silicon gate layer, a 9 and PWELL well layer, a 10 and lead hole edge layer, an 11 and opening region, a 12 and deep groove, a 13 and source groove polycrystalline silicon gate, a 14 and TEOS thick oxygen layer, a 15 and P + layer, a 16 and N + layer, a 17 and a front metal layer, and an 18 and N + injection blocking region.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A CoolMOS device manufacturing method comprises the following steps:
1) growing field oxygen, opening a voltage division ring, and injecting and annealing the voltage division ring;
2) opening an active region;
3) processing a deep groove 12 in an active region, depositing TEOS (tetraethylammonium bromide) thick oxygen 14 in the deep groove 12 to form a TOES (tetraethylammonium bromide) film, growing and curing the TOES film, carrying out plasma etching, injecting a P-type impurity at the bottom of the deep groove 12, depositing a source groove polysilicon gate 13 in the deep groove 12, and etching back a source groove polysilicon gate 13;
4) growing a gate oxide 4, depositing a polysilicon gate, photoetching the polysilicon gate and etching the polysilicon gate;
5) the PWELL well layer 9 is subjected to implantation annealing;
6) performing source region N + photoetching, N + injection and annealing;
7) TEOS deposition, growth of passivating borophosphosilicate glass under aluminum, and reflux;
8) photoetching and etching lead holes;
9) front side metallization is formed;
10) thinning;
11) back metallization is formed;
12) and (6) CP testing and warehousing.
As shown in fig. 1-2, a CoolMOS device sequentially includes, from bottom to top, a back metal layer 1, an N + substrate layer 2, an N-type high-concentration current layer 3, and a front metal layer 17, wherein an upper surface of the N-type high-concentration current layer 3 includes polysilicon gate regions 5 and polysilicon OPEN regions 6 arranged at intervals in sequence, a lower surface of the front metal layer 17 is provided with contact holes 10, the contact holes 10 are arranged at intervals at a lower surface of the front metal layer 17, an inner upper wall of the contact hole 10 is provided with an aluminum lower passivation layer 7, the aluminum lower passivation layer 7 is filled with a polysilicon gate layer 8, the polysilicon gate layer 8 is provided in the polysilicon gate region 5, PWELL well layers 9 are embedded in an upper surface of the N-type high-concentration current layer 3, the PWELL well layers 9 are arranged at equal intervals at an upper surface of the N-type high-concentration current layer 3, a middle portion of the PWELL well layer 9 is provided in the polysilicon OPEN region 6, and both sides of the PWELL well layers are provided in the polysilicon gate regions 5, the polysilicon gate layer 8 is arranged between two adjacent groups of PWELL well layers 9, the gate oxide layer 4 is arranged between the polysilicon gate layer 8 and the PWELL well layers 9, and between the polysilicon gate layer 8 and the N-type high-concentration current layer 3, a plurality of groups of opening regions 11 are arranged in the polysilicon OPEN region 6, an N + injection blocking region 18 is arranged in the opening region 11, a deep trench 12 is arranged on the PWELL well layers 9 in a penetrating manner, the lower end of the deep trench 12 extends into the N-type high-concentration current layer 3, the deep trench 12 is arranged at the N + injection blocking region 18, a source trench polysilicon gate 13 is filled in the deep trench 12, TEOS thick oxygen is arranged between the source trench polysilicon gate 13 and the deep trench 12, the source trench polysilicon gate 13 is uniformly distributed in the N + injection blocking region 18 at equal intervals, an N + layer 16 is arranged outside the N + injection blocking region 18, a P + layer 15 is arranged at the bottom of the deep trench 12, and the upper wall of the P + layer 15 penetrates through the deep trench 12 to be connected with the source polysilicon gate 13, the bottom wall of the P + layer 15 is connected with the N-type high-concentration current layer 3, an N + layer 16 is arranged on one side, close to the polycrystalline silicon gate layer, of the upper end of the deep groove 12, the N + layer 16 is connected with the source groove polycrystalline silicon gate 13 and the PWELL well layer 9 respectively, and the source groove polycrystalline silicon gate 13 is in short circuit with the PWELL well layer 9.
Two rows of deep grooves 12 are arranged in each polycrystalline OPEN region 6, and the N + layers 16 are symmetrically arranged on two sides of two adjacent rows of deep grooves;
through multiple experiments, the method develops 600V medium-high voltage plane VDMOS products, and compared with products with the same area, the internal resistance is reduced by 50%.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by the present specification, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (3)
1. A CoolMOS device manufacturing method is characterized by comprising the following steps:
1) growing field oxygen, opening a voltage division ring, and injecting and annealing the voltage division ring;
2) opening an active region;
3) processing a deep groove in the active region, depositing TEOS (tetraethyl orthosilicate) thick oxygen in the deep groove to form a TOES (tungsten-doped silicon) film, growing and curing the TOES film, carrying out plasma etching, injecting P-type impurities at the bottom of the deep groove, depositing a source groove polysilicon gate in the deep groove, and etching back the source groove polysilicon gate;
4) growing gate oxide, depositing a polysilicon gate, photoetching the polysilicon gate and etching the polysilicon gate;
5) performing PWELL well layer injection annealing;
6) performing source region N + photoetching, N + injection and annealing;
7) TEOS deposition, growth of passivating borophosphosilicate glass under aluminum, and reflux;
8) photoetching and etching lead holes;
9) front side metallization is formed;
10) thinning;
11) back metallization is formed;
12) and (6) CP testing and warehousing.
2. A CoolMOS device, comprising: the high-concentration current collector sequentially comprises a back metal layer, an N + substrate layer, an N-type high-concentration current layer, an insulating layer and a front metal layer from bottom to top, wherein the upper surface of the N-type high-concentration current layer comprises a polycrystalline silicon gate region and a polycrystalline OPEN region which are arranged at intervals in sequence, the lower surface of the front metal layer is provided with contact holes, the lower surface of the front metal layer is arranged at intervals, an aluminum lower passivation layer is arranged on the upper wall in the contact holes, a polycrystalline silicon gate layer is filled in the aluminum lower passivation layer and is arranged in the polycrystalline silicon gate region, PWELL well layers are embedded in the upper surface of the N-type high-concentration current layer, the PWELL well layers are arranged on the upper surface of the N-type high-concentration current layer at equal intervals, the middle of each PWELL well layer is arranged in the polycrystalline silicon gate region, two sides of each polycrystalline silicon gate layer are arranged between two adjacent PWELL well layers, and gate oxide layers are arranged between each PWELL well layer and between each polycrystalline silicon gate layer and the N-type high-concentration current layer, the polysilicon gate structure comprises a poly OPEN region, a PWELL well layer, a N + injection blocking region, a source trench polysilicon gate, a TEOS (tetraethylammonium orthosilicate) thick oxygen layer, N + injection blocking regions, N + layers and a P + layer, wherein a plurality of groups of opening regions are arranged in the poly OPEN region, an N + injection blocking region is arranged in the opening region, a deep trench penetrates through the PWELL well layer, the lower end of the deep trench extends into the N-type high-concentration current layer, the deep trench is arranged at the N + injection blocking region, the deep trench is internally filled with the source trench polysilicon gate, the TEOS thick oxygen is arranged between the source trench polysilicon gate and the deep trench, the source trench polysilicon gate is uniformly distributed in the N + injection blocking region at equal intervals, the N + layers are arranged outside the N + injection blocking region, the poly OPEN region is opened through the opening regions, the bottom of the deep trench is provided with the P + layer, the upper wall of the P + layer penetrates through the deep trench and is connected with the source trench polysilicon gate, the bottom wall of the P + layer is connected with the N-type high-concentration current layer, an N layer is arranged at one side of the upper end of the deep trench close to the polysilicon gate layer, and the N + layer, and the N + layer are respectively connected with the source trench polysilicon gate, And the PWELL well layer is connected, and the source groove polysilicon gate is in short circuit with the PWELL well layer.
3. The CoolMOS device of claim 2, wherein two deep trenches are provided in each poly OPEN region, and the N + layers are symmetrically provided at two sides of two adjacent deep trenches.
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