CN110429134B - IGBT device with asymmetric primitive cells and preparation method - Google Patents
IGBT device with asymmetric primitive cells and preparation method Download PDFInfo
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- CN110429134B CN110429134B CN201910711494.7A CN201910711494A CN110429134B CN 110429134 B CN110429134 B CN 110429134B CN 201910711494 A CN201910711494 A CN 201910711494A CN 110429134 B CN110429134 B CN 110429134B
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- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000010410 layer Substances 0.000 claims abstract description 103
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 238000002955 isolation Methods 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 36
- 229910052757 nitrogen Inorganic materials 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 238000002161 passivation Methods 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 3
- 238000009825 accumulation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The invention discloses an IGBT device with asymmetric primitive cells and a preparation method thereof, the IGBT device comprises a P-type collector, wherein an N-type substrate is arranged at the top of the P-type collector, a plurality of grooves are arranged on the N-type substrate, gate oxide layers are respectively arranged on the side walls and the bottom of the grooves, one half part of each groove belongs to an effective primitive cell, the other half part of each groove belongs to a virtual primitive cell, the thickness of the gate oxide layer at the bottom of each groove and the thickness of the gate oxide layer on the side wall of each groove in the virtual primitive cell are both larger than those of the gate oxide layers on the side walls of the grooves in the effective primitive cells, a polycrystalline silicon layer is arranged in each groove, a P-type well is arranged between every two adjacent grooves, a heavily doped P-type region and a heavily doped N-type region are arranged in each P-type well, the heavily doped N-type region belongs to an effective primitive cell, one half of the heavily doped P-type region belongs to an effective primitive cell, an interlayer isolation layer is arranged at the top of each groove, a contact hole is arranged on the interlayer isolation layer, and a collector metal layer is covered outside the interlayer isolation layer. The invention can reduce the Miller capacitance and keep the conduction voltage drop of the device unchanged.
Description
Technical Field
The invention relates to an IGBT device, in particular to an IGBT device with asymmetric primitive cells and a preparation method thereof.
Background
The structure of the IGBT device in the prior art is shown in fig. 1, where effective cells and virtual cells (dummy cells) are symmetrically distributed, and the thickness of the gate oxide layer at the bottom of the trench, the thickness of the gate oxide layer on the sidewall of the trench in the virtual cell, and the thickness of the gate oxide layer on the sidewall of the trench in the effective cell are the same. The part of the groove exceeding the P-type well is used as a device accumulation area, the length of the device accumulation area is closely related to the conduction voltage drop of the device and the Miller capacitance, the length of the device accumulation area is reduced, the Miller capacitance is reduced, and the conduction voltage drop of the device is increased. However, from an application point of view, it is desirable that the smaller the device turn-on voltage drop and the miller capacitance, the better. Therefore, the IGBT device in the prior art cannot achieve the reduction of miller capacitance while keeping the device on-voltage drop constant.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide an IGBT device with asymmetric primitive cells and a preparation method thereof, which can reduce Miller capacitance and keep the conduction voltage drop of the device unchanged.
The technical scheme is as follows: the invention relates to an IGBT device with asymmetric primitive cells, which comprises a P-type collector, wherein an N-type substrate is arranged at the top of the P-type collector, a plurality of grooves are arranged on the N-type substrate, gate oxide layers are arranged on the side walls and the bottom of the grooves, one half part of each groove belongs to an effective primitive cell, the other half part of each groove belongs to a virtual primitive cell, the thickness of the gate oxide layer at the bottom of each groove and the thickness of the gate oxide layer on the side wall of each groove in each virtual primitive cell are both larger than those of the gate oxide layers on the side walls of the grooves in the effective primitive cells, a polycrystalline silicon layer is arranged in each groove, a P-type well is arranged between every two adjacent grooves, a heavily doped P-type region and a heavily doped N-type region are arranged in each P-type well, the heavily doped N-type regions belong to the effective primitive cells, one half of the heavily doped P-type regions belong to the effective primitive cells, the other half of the virtual primitive cells are arranged at the tops of the grooves, interlayer isolation layers are provided with contact holes, and collector metal layers are covered outside the interlayer isolation layers.
Further, all the trenches are the same size.
Further, the thickness of the gate oxide layer at the bottom of the groove and the thickness of the gate oxide layer on the side wall of the groove in the virtual primitive cell are both larger than the thickness of the gate oxide layer on the side wall of the groove in the effective primitive cell, and the method is realized through the following steps: and injecting nitrogen elements into the side wall of the groove in the effective primitive cell, not injecting nitrogen elements into the bottom of the groove and the side wall of the groove in the virtual primitive cell, and then generating a gate oxide layer on the side wall of the groove in the effective primitive cell, the bottom of the groove and the side wall of the groove in the virtual primitive cell.
The method for preparing the IGBT device with the asymmetric primitive cells comprises the following steps:
s1: performing ring injection, growth and etching of a field oxide layer in the terminal area;
s2: generating an N-type substrate in the cell area;
s3: etching a plurality of grooves on the N-type substrate;
s4: injecting nitrogen element into the side wall of the groove in the effective primitive cell;
s5: growing gate oxide layers on the side wall of the groove in the effective primitive cell, the bottom of the groove and the side wall of the groove in the virtual primitive cell;
s6: depositing a polycrystalline silicon layer, and then etching the polycrystalline silicon layer outside the groove;
s7: injecting and annealing a P-type well between two adjacent grooves;
s8: forming a heavily doped P-type region and a heavily doped N-type region in a P-type well, wherein the heavily doped N-type region belongs to an effective cell, one half of the heavily doped P-type region belongs to the effective cell, and the other half of the heavily doped P-type region belongs to a virtual cell;
s9: depositing an interlayer isolation layer on the top of the trench;
s10: etching a contact hole on the interlayer isolation layer, wherein a contact hole is formed between two adjacent grooves;
s11: depositing a collector metal layer on the surface of the interlayer isolation layer;
s12: depositing a passivation layer on the surface of the collector metal layer and the terminal area, removing the passivation layer on the surface of the collector metal layer, and only keeping the passivation layer in the terminal area;
s13: and generating a P-type collector at the bottom of the N-type substrate.
Further, in the step S4, an included angle between the direction of nitrogen implantation and the symmetry axis of the trench is 20 ° to 75 °.
Further, in the step S4, the concentration of nitrogen element is 2X 10 13 ～1×10 15 atom/cm 2 The energy is 30KeV to 60KeV.
Has the beneficial effects that: the invention discloses an IGBT device with asymmetric primitive cells and a preparation method thereof.A gate oxide layer at the bottom of a groove and a gate oxide layer on the side wall of the groove in a virtual primitive cell are both set to be thicker than the gate oxide layer on the side wall of the groove in an effective primitive cell, so that the Miller capacitance can be greatly reduced without changing the length of an accumulation region of the device, and the conduction voltage drop of the device is kept unchanged.
Drawings
FIG. 1 is a schematic diagram of a prior art IGBT device;
FIG. 2 is a schematic diagram of an IGBT device according to an embodiment of the present invention;
FIG. 3 is a schematic illustration of nitrogen implantation in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a gate oxide layer after being formed according to an embodiment of the present invention;
fig. 5 is a schematic diagram after formation of a polysilicon layer in accordance with an embodiment of the present invention.
Detailed Description
The structure of the IGBT device in the prior art is shown in fig. 1, and includes a collector metal layer 11, a trench 12, an N-type substrate 13, a P-type collector 14, an interlayer isolation layer 15, a P-type well 16, a heavily doped N-type region 17, a heavily doped P-type region 18, an effective cell 101, a dummy cell 102, and a contact hole 19. It can be seen that the effective cell 101 and the dummy cell 102 are symmetrical, and the thickness of the gate oxide layer at the bottom of the trench 12, the thickness of the gate oxide layer on the sidewall of the trench 12 in the dummy cell 102, and the thickness of the gate oxide layer on the sidewall of the trench 12 in the effective cell 101 are the same.
The specific embodiment discloses an IGBT device with asymmetric primitive cells, as shown in fig. 2, including a P-type collector 24, an N-type substrate 23 is disposed on the top of the P-type collector 24, a plurality of trenches 22 are disposed on the N-type substrate 23, the sidewalls and the bottom of the trenches 22 are both provided with gate oxide layers, one half of one trench 22 belongs to an effective primitive cell 201, the other half belongs to a virtual primitive cell 202, the thickness of the gate oxide layer 221 on the bottom of the trench 22 and the thickness of the gate oxide layer 221 on the sidewall of the trench 22 in the virtual primitive cell 202 are both greater than the thickness of the gate oxide layer 221 on the sidewall of the trench 22 in the effective primitive cell 201, a polysilicon layer 222 is disposed in the trench 22, a P-type well 26 is disposed between two adjacent trenches 22, a heavily doped P-type region 28 and a heavily doped N-type region 27 are disposed in the P-type well 26, the heavily doped N-type region 27 belongs to the effective primitive cell 201, one half of the P-type region 28 belongs to an effective primitive cell contact hole, an interlayer insulating layer 202 is disposed on the top of the trench 22, an insulating layer 25, an insulating layer 201 is disposed between the virtual primitive cells, and an insulating layer 21 is covered with a collector layer. All trenches 22 are the same size.
The thickness of the gate oxide layer 221 at the bottom of the trench 22 and the thickness of the gate oxide layer 221 on the side wall of the trench 22 in the virtual cell 202 are both greater than the thickness of the gate oxide layer 221 on the side wall of the trench 22 in the effective cell 201, which is realized by the following method: and performing nitrogen element injection on the side wall of the trench 22 in the effective cell 201, not performing nitrogen element injection on the bottom of the trench 22 and the side wall of the trench 22 in the virtual cell 202, and then generating a gate oxide layer 221 on the side wall of the trench 22 in the effective cell 201, the bottom of the trench 22 and the side wall of the trench 22 in the virtual cell 202.
The specific embodiment also discloses a method for preparing the IGBT device with the asymmetric primitive cells, which comprises the following steps:
s1: performing ring injection, growth and etching of a field oxide layer in the terminal area;
s2: generating an N-type substrate 23 in the cell region;
s3: etching a plurality of grooves 22 on an N-type substrate 23;
s4: implanting nitrogen into the sidewalls of the trenches 22 in the active cell 201, as shown in FIG. 3; the included angle between the nitrogen element injection direction and the symmetrical axis of the groove 22 is 20 degrees to 75 degrees, and the concentration of the nitrogen element is 2 multiplied by 10 13 ～1×10 15 atom/cm 2 The energy is 30 KeV-60 KeV;
s5: growing a gate oxide layer 221 on the sidewalls of the trenches 22 in the effective cells 201, the bottom of the trenches 22 and the sidewalls of the trenches 22 in the dummy cells 202, as shown in fig. 4;
s6: depositing a polysilicon layer 222, and then etching the polysilicon layer 222 outside the trench 22, as shown in fig. 5;
s7: implanting and annealing the P-type well 26 between two adjacent trenches 22;
s8: forming a heavily doped P-type region 28 and a heavily doped N-type region 27 in the P-type well 26, wherein the heavily doped N-type region 27 belongs to the effective cell 201, half of the heavily doped P-type region 28 belongs to the effective cell 201, and the other half belongs to the dummy cell 202;
s9: depositing a spacer layer 25 on top of the trench 22;
s10: a contact hole 29 is etched on the interlayer isolation layer 25, and a contact hole 29 is formed between every two adjacent grooves 22;
s11: depositing a collector metal layer 21 on the surface of the interlayer isolation layer 25;
s12: depositing a passivation layer on the surface of the collector metal layer 21 and the terminal area, and then removing the passivation layer on the surface of the collector metal layer 21 and only keeping the passivation layer in the terminal area;
s13: a P-type collector 24 is formed at the bottom of the N-type substrate 23.
The reason why the nitrogen element is injected into the sidewall of the trench 22 in the effective cell 201 is that the growth rate of the gate oxide layer 221 will be slowed down after the nitrogen element is injected, so that the thickness of the gate oxide layer 221 at the bottom of the trench 22 and the thickness of the gate oxide layer 221 at the sidewall of the trench 22 in the virtual cell 202 are both greater than the thickness of the gate oxide layer 221 at the sidewall of the trench 22 in the effective cell 201.
Claims (4)
1. The utility model provides an IGBT device with asymmetric primitive cell, includes P type collector (24), and P type collector (24) top is equipped with N type substrate (23), is equipped with a plurality of slots (22) on N type substrate (23), and the lateral wall and the bottom of slot (22) all are equipped with gate oxide, its characterized in that: one half part of one groove (22) belongs to an effective primitive cell (201), the other half part belongs to a virtual primitive cell (202), the thickness of a gate oxide layer (221) at the bottom of the groove (22) and the thickness of the gate oxide layer (221) on the side wall of the groove (22) in the virtual primitive cell (202) are both larger than the thickness of the gate oxide layer (221) on the side wall of the groove (22) in the effective primitive cell (201), a polycrystalline silicon layer (222) is arranged in the groove (22), a P-type well (26) is arranged between every two adjacent grooves (22), a heavily doped P-type region (28) and a heavily doped N-type region (27) are arranged in the P-type well (26), the N-type region (27) belongs to the effective primitive cell (201), the other half part belongs to the virtual primitive cell (202), an interlayer isolation layer (25) is arranged at the top of the groove (22), a contact hole (29) is arranged on the interlayer isolation layer (25), and a collector metal layer (21) covers the interlayer isolation layer (25);
all the grooves (22) have the same size;
the thickness of the gate oxide layer (221) at the bottom of the groove (22) and the thickness of the gate oxide layer (221) on the side wall of the groove (22) in the virtual primitive cell (202) are both larger than the thickness of the gate oxide layer (221) on the side wall of the groove (22) in the effective primitive cell (201) and are realized through the following modes: and (2) performing nitrogen element injection on the side wall of the groove (22) in the effective primitive cell (201), not performing nitrogen element injection on the bottom of the groove (22) and the side wall of the groove (22) in the virtual primitive cell (202), and then generating a gate oxide layer (221) on the side wall of the groove (22) in the effective primitive cell (201), the bottom of the groove (22) and the side wall of the groove (22) in the virtual primitive cell (202).
2. The method of fabricating the IGBT device with asymmetric cells of claim 1, characterized in that: the method comprises the following steps:
s1: performing ring injection, growth and etching of a field oxide layer in the terminal area;
s2: generating an N-type substrate (23) in the cell region;
s3: etching a plurality of grooves (22) on an N-type substrate (23);
s4: implanting nitrogen into the sidewall of the trench (22) in the active cell (201);
s5: growing a gate oxide layer (221) on the side wall of the trench (22) in the effective cell (201), the bottom of the trench (22) and the side wall of the trench (22) in the virtual cell (202);
s6: depositing a polysilicon layer (222), and then etching the polysilicon layer (222) outside the groove (22) to be clean;
s7: injecting and annealing the P-type well (26) between two adjacent trenches (22);
s8: forming a heavily doped P-type region (28) and a heavily doped N-type region (27) in a P-type well (26), wherein the heavily doped N-type region (27) belongs to an effective cell (201), one half of the heavily doped P-type region (28) belongs to the effective cell (201), and the other half of the heavily doped P-type region belongs to a virtual cell (202);
s9: depositing a spacer layer (25) on top of the trench (22);
s10: etching a contact hole (29) on the interlayer isolation layer (25), wherein one contact hole (29) is arranged between two adjacent grooves (22);
s11: depositing a collector metal layer (21) on the surface of the interlayer isolation layer (25);
s12: depositing a passivation layer on the surface of the collector metal layer (21) and the terminal area, and then removing the passivation layer on the surface of the collector metal layer (21) and only keeping the passivation layer in the terminal area;
s13: and a P-type collector (24) is generated at the bottom of the N-type substrate (23).
3. The method of fabricating an IGBT device with asymmetric cells according to claim 2, characterized in that: in the step S4, an included angle between the nitrogen element injection direction and a symmetry axis of the groove (22) is 20-75 degrees.
4. The method of fabricating an IGBT device with asymmetric cells according to claim 2, characterized in that: in the step S4, the concentration of nitrogen element is 2 x 10 13 ~1×10 15 atom/cm 2 The energy was 30KeV to 60KeV.
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| CN113571575B (en) * | 2021-06-09 | 2023-01-10 | 松山湖材料实验室 | Silicon carbide power semiconductor device and field effect transistor |
| CN113394280A (en) * | 2021-06-15 | 2021-09-14 | 扬州国扬电子有限公司 | Grid-controlled power device with asymmetric primitive cell structure and preparation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030023189A (en) * | 2001-09-12 | 2003-03-19 | 페어차일드코리아반도체 주식회사 | MOS gated power semiconductor device and method for fabricating the same |
| KR20090049770A (en) * | 2007-11-14 | 2009-05-19 | 주식회사 하이닉스반도체 | Dual gate of semiconductor device and method for forming the same |
| CN103956379A (en) * | 2014-05-09 | 2014-07-30 | 常州中明半导体技术有限公司 | CSTBT device with optimized plugged cell structure |
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| US6580123B2 (en) * | 2000-04-04 | 2003-06-17 | International Rectifier Corporation | Low voltage power MOSFET device and process for its manufacture |
| US6489202B1 (en) * | 2001-05-29 | 2002-12-03 | Ememory Technology, Inc. | Structure of an embedded channel write-erase flash memory cell and fabricating method thereof |
| TWI278876B (en) * | 2006-01-03 | 2007-04-11 | Delta Electronics Inc | Transformer structure |
| JP2009070849A (en) * | 2007-09-10 | 2009-04-02 | Rohm Co Ltd | Semiconductor device |
| CN101246886B (en) * | 2008-03-19 | 2010-06-02 | 江苏宏微科技有限公司 | Power transistor with MOS structure and production method thereof |
| CN102456738A (en) * | 2010-10-29 | 2012-05-16 | 上海宏力半导体制造有限公司 | VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) transistor |
| US8637370B2 (en) * | 2012-01-19 | 2014-01-28 | Globalfoundries Singapore Pte. Ltd. | Integration of trench MOS with low voltage integrated circuits |
| TW201419532A (en) * | 2012-11-08 | 2014-05-16 | Anpec Electronics Corp | Semiconductor device with reduced miller capacitance and fabrication method thereof |
| CN209087841U (en) * | 2018-10-16 | 2019-07-09 | 扬州国扬电子有限公司 | Optimize the grid-controlled type power device of input capacitance |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030023189A (en) * | 2001-09-12 | 2003-03-19 | 페어차일드코리아반도체 주식회사 | MOS gated power semiconductor device and method for fabricating the same |
| KR20090049770A (en) * | 2007-11-14 | 2009-05-19 | 주식회사 하이닉스반도체 | Dual gate of semiconductor device and method for forming the same |
| CN103956379A (en) * | 2014-05-09 | 2014-07-30 | 常州中明半导体技术有限公司 | CSTBT device with optimized plugged cell structure |
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