CN113113480A - HEMT device with p-GaN cap layer and preparation method thereof - Google Patents

HEMT device with p-GaN cap layer and preparation method thereof Download PDF

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CN113113480A
CN113113480A CN202110313170.5A CN202110313170A CN113113480A CN 113113480 A CN113113480 A CN 113113480A CN 202110313170 A CN202110313170 A CN 202110313170A CN 113113480 A CN113113480 A CN 113113480A
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layer
gan
hemt device
dielectric layer
cap layer
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陈龙
程静云
商延卫
马旺
陈祖尧
袁理
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Juneng Jingyuan Qingdao Semiconductor Materials Co ltd
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Juneng Jingyuan Qingdao Semiconductor Materials Co ltd
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Publication of CN113113480A publication Critical patent/CN113113480A/en
Priority to PCT/CN2022/077458 priority patent/WO2022199309A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The invention provides an HEMT device with a p-GaN cap layer and a preparation method thereof, wherein H is2Annealing treatment is carried out in the atmosphere to expose the p-GaN layer and H2The p-GaN passivation layer is formed by reaction, so that the etching of the p-GaN layer can be avoided; passivating Mg in the p-GaN layer into Mg-H bonds, so that the hole concentration can be reduced, and the p-GaN layer is converted into a high-resistance p-GaN passivation layer to cut off a leakage channel of the p-GaN layer in the HEMT device and improve the gate control capability; the p-GaN passivation layer can release two-dimensional electron gas of a channel which is originally depleted and is positioned below the AlGaN/GaN heterojunction interface; the remained thick p-GaN passivation layer with high resistance is beneficial to reducing the current collapse of the HEMT device.

Description

HEMT device with p-GaN cap layer and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a HEMT device with a p-GaN cap layer and a preparation method thereof.
Background
As a representative third generation semiconductor material, gallium nitride (GaN) has many excellent characteristics such as wide band gap, excellent radiation noise resistance, high avalanche breakdown electric field, good thermal conductivity, and high electron drift rate under a strong field, and is widely used in the fields such as laser, LED, microwave, and radio frequency.
The existing power semiconductor market mainly comprises silicon power devices, and in the past 20 years, the power density of the silicon power devices is increased by 5-6 times every 10 years, but the power density of the silicon power devices is close to the theoretical limit, and the performance is difficult to be further improved. Compared with silicon or gallium arsenide, the GaN power semiconductor has the advantages of wide band gap, excellent thermal stability, high breakdown voltage, high electron saturation drift velocity and excellent radiation resistance, and compared with the silicon power semiconductor, the GaN power semiconductor also has low-temperature resistance, so that the GaN power semiconductor can reduce power conversion loss caused by the power semiconductor, and the power system and the power loss are minimized.
A High Electron Mobility Transistor (HEMT) is a heterojunction field effect transistor, and a High mobility two-dimensional electron gas (2DEG) exists in a heterojunction, so that the HEMT device has High frequency, High power, High temperature resistance, strong radiation resistance and other excellent performances. At present, the p-GaN enhanced HEMT device can reduce the power consumption and complexity of a system and improve the safety, so that the p-GaN enhanced HEMT device has wide application prospects in the fields of high-temperature and radio-frequency integrated circuits, high-speed switches, microwave monolithic integrated circuits and the like.
Currently, the mainstream technology for realizing the p-GaN enhancement type HEMT device is to introduce a p-GaN cap layer between a gate electrode and a barrier layer, wherein the p-GaN cap layer can partially or completely remove 2DEG below the gate electrode, so that the threshold voltage (Vth) is shifted in the forward direction. For the preparation of the p-GaN cap layer, the conventional method generally comprises the steps of depositing and forming the p-GaN layer, and then etching the p-GaN layer to form the p-GaN cap layer, however, due to the characteristics of the etching process, challenges are provided for the aspects of roughness, uniformity, selectivity, cavity control and the like, and the problems of uneven etching and etching damage are easily caused when the p-GaN cap layer is prepared by adopting an etching method. Thereby affecting device performance.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a HEMT device with a p-GaN cap layer and a method for manufacturing the HEMT device, which are used to solve the problems of non-uniform etching and etching damage of the p-GaN cap layer in the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating a HEMT device having a p-GaN cap layer, comprising the steps of:
providing an epitaxial structure, wherein the epitaxial structure comprises a GaN channel layer, an AlGaN barrier layer and a p-GaN layer;
forming a dielectric layer covering the p-GaN layer;
patterning the dielectric layer to expose part of the p-GaN layer;
at H2Annealing treatment is carried out in the atmosphere, and the p-GaN layer and the H layer are exposed in the p-GaN layer2Reacting to form Mg-H bonds to form a p-GaN passivation layer, and forming a p-GaN capping layer by the p-GaN layer covered by the dielectric layer.
Optionally, the thickness of the p-GaN layer is 70nm to 100 nm.
Optionally, the doping concentration of Mg ions in the p-GaN layer is 1 × E19cm-3～5×E19cm-3。
Optionally, the temperature of the annealing treatment is 800-950 ℃, and the time of the annealing treatment is 10-15 min.
Optionally, the dielectric layer is a silicon nitride layer, and the method for patterning the dielectric layer includes using CF4And carrying out plasma etching.
Optionally, the thickness of the dielectric layer is 100nm to 200 nm.
The invention also provides a HEMT device with a p-GaN cap layer, comprising:
a patterned dielectric layer;
the epitaxial structure comprises a GaN channel layer, an AlGaN barrier layer and a p-GaN layer, wherein the p-GaN layer comprises a p-GaN cap layer and a p-GaN passivation layer, the dielectric layer covers the p-GaN cap layer, and the p-GaN passivation layer is exposed out of the dielectric layer.
Optionally, the thickness of the p-GaN layer is 70nm to 100 nm.
Optionally, the doping concentration of Mg ions in the p-GaN layer is 1 × E19cm-3～5×E19cm-3。
Optionally, the dielectric layer is a silicon nitride layer, and the thickness of the dielectric layer is 100nm to 200 nm.
As mentioned above, the HEMT device with the p-GaN cap layer and the preparation method thereof provided by the invention are realized by the method in H2Annealing treatment is carried out in the atmosphere to expose the p-GaN layer and H2Reacting to form a p-GaN passivation layer, thereby avoiding etching the p-GaN layer and avoiding the problems of uneven etching and etching damage of the p-GaN cap layer; by reaction at H2Annealing treatment is carried out in the atmosphere, shallow level acceptor impurities Mg in the p-GaN layer can be passivated into Mg-H bonds, hole concentration is reduced, the p-GaN layer is converted into a high-resistance p-GaN passivation layer, and the high-resistance p-GaN passivation layer can cut off a leakage channel of the p-GaN layer in the HEMT device, so that grid control capability is improved; because Mg in the p-GaN layer is passivated, the concentration of holes in the p-GaN layer is sharply reduced, so that the p-GaN passivation layer can release two-dimensional electron gas of an originally depleted channel, which is positioned below an AlGaN/GaN heterojunction interface; and the p-GaN layer outside the gate electrode is converted into a high-resistance p-GaN passivation layer, so that the reserved thick high-resistance p-GaN passivation layer is beneficial to reducing the current collapse of the HEMT device.
Drawings
Fig. 1 shows a process flow diagram for fabricating a HEMT device with a p-GaN cap layer in accordance with the present invention.
Fig. 2 is a schematic structural view of an epitaxial structure according to the present invention.
Fig. 3 is a schematic structural diagram after forming an alignment mark according to the present invention.
Fig. 4 is a schematic structural diagram of the present invention after forming an isolation structure.
Fig. 5 is a schematic structural diagram of the patterned dielectric layer formed in the present invention.
FIG. 6 is a schematic view showing a structure after annealing treatment in the present invention.
Description of the element reference numerals
100 substrate
200 buffer layer
300 GaN channel layer
400 AlGaN barrier layer
500 p-GaN layer
501 p-GaN capping layer
502 p-GaN passivation layer
600 alignment mark
700 isolation structure
800 dielectric layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, this embodiment provides a method for manufacturing a HEMT device having a p-GaN cap layer, including the following steps:
providing an epitaxial structure, wherein the epitaxial structure comprises a GaN channel layer, an AlGaN barrier layer and a p-GaN layer;
forming a dielectric layer covering the p-GaN layer;
patterning the dielectric layer to expose part of the p-GaN layer;
at H2Annealing treatment is carried out in the atmosphere, and the p-GaN layer and the H layer are exposed in the p-GaN layer2Reacting to form Mg-H bonds to form a p-GaN passivation layer, and forming a p-GaN capping layer by the p-GaN layer covered by the dielectric layer.
This example is achieved by2Annealing treatment is carried out in the atmosphere to expose the p-GaN layer and H2Reacting to form p-GaN passivation layerThe etching of the p-GaN layer is avoided, and the problems of uneven etching and etching damage of the p-GaN cap layer are avoided; by reaction at H2Annealing treatment is carried out in the atmosphere, shallow level acceptor impurities Mg in the p-GaN layer can be passivated into Mg-H bonds, hole concentration is reduced, the p-GaN layer is converted into a high-resistance p-GaN passivation layer, and the high-resistance p-GaN passivation layer can cut off a leakage channel of the p-GaN layer in the HEMT device, so that grid control capability is improved; because Mg in the p-GaN layer is passivated, the concentration of holes in the p-GaN layer is sharply reduced, so that the p-GaN passivation layer can release two-dimensional electron gas of an originally depleted channel, which is positioned below an AlGaN/GaN heterojunction interface; the p-GaN layer outside the gate electrode is changed into a high-resistance p-GaN passivation layer, so that the reserved thick high-resistance p-GaN passivation layer is beneficial to reducing the current collapse of the HEMT device.
Specifically, referring to fig. 2 to 6, schematic structural diagrams formed in the process of manufacturing the HEMT device with the p-GaN cap layer are shown.
First, referring to fig. 2, an epitaxial structure is provided, which includes a GaN channel layer 300, an AlGaN barrier layer 400, and a p-GaN layer 500.
Specifically, the epitaxial structure includes a substrate 100, and a silicon (111) substrate is used in this embodiment, but the material of the substrate 100 is not limited thereto, and a silicon-on-insulator (SOI) substrate, a silicon carbide (SiC) substrate, or the like may be used as the substrate 100 as needed, and the specific material, structure, size, and the like of the substrate 100 are not limited herein.
As an example, a buffer layer 200 is preferably disposed between the substrate 100 and the GaN channel layer 300, and the buffer layer 200 is preferably a buffer stacked structure.
Specifically, when the GaN channel layer 300 is heteroepitaxially grown on the substrate 100, particularly when the silicon substrate with lower cost is used, the silicon substrate and the GaN material have lattice mismatch and thermal expansion coefficient mismatch problems, so that after the buffer layer 200 is introduced between the substrate 100 and the GaN channel layer 300, the buffer layer 200 can be used for adjusting stress, and then the GaN channel layer 300 and the AlGaN barrier layer are sequentially epitaxially grown on the buffer layer 200400 and a p-GaN layer 500. Wherein the buffer layer 200 may be AlxGa1-xN buffer lamination, wherein x is more than or equal to 0 and less than or equal to 1, namely the buffer layer 200 can comprise AlN layers and Al with gradually changed components which are sequentially overlapped from bottom to topxGa1-xN layers, e.g. Al0.3Ga0.7N layer, Al0.5Ga0.5N layers, etc., and the specific choice may be made according to the needs, and is not limited herein. It should be noted that the epitaxial structure may be configured with related functional layers as needed, and is not limited to the above example.
Referring to fig. 5, a dielectric layer 800 covering the p-GaN layer 500 is formed and the dielectric layer 800 is patterned to expose a portion of the p-GaN layer 500.
Referring to fig. 3, before forming the dielectric layer 800, a step of forming an alignment mark 600 is included.
Specifically, the alignment mark 600 is used as an etching reference point, which facilitates accurate etching in a subsequent process. Wherein, when the alignment mark 600 is formed, Cl may be used2And BCl3Plasma etching is performed to an etching depth of 50nm to 200nm, such as 50nm, 100nm, 150nm, 200nm, but not limited thereto, so as to define an alignment mark region for photo-etching alignment. The morphology, distribution, etc. of the alignment marks 600 are not overly limited herein.
Next, referring to fig. 4, after forming the alignment mark 600 and before forming the dielectric layer 800, a step of forming an isolation structure 700 is included.
Specifically, the HEMT device prepared in this embodiment is formed by connecting a plurality of small devices, and therefore the small devices need to be isolated from each other to block the flow of carriers between the single device and the device, so that each device is located in an isolation island surrounded by the isolation region. The device isolation generally has two methods, one is that ions are injected to form a high-resistance area to realize the isolation between devices, and the other is that mesa etching is used to realize the blocking of a conductive channel between devices. In order to avoid etching damage, in this embodiment, the isolation structure 700 is preferably formed by ion implantation, wherein the implanted ions may be F ions, and the ion concentration is 1 × E19cm-3～2×E20cm-3E.g. 1 XE19cm-3、1.5×E19cm-3、2×E19cm-3And the like. The bottom of the isolation structure 700 is preferably located at a depth of 40nm to 60nm, such as 40nm, 50nm, 60nm, etc., of the GaN channel layer 300, so as to block two-dimensional electron gas and reduce damage. The method for forming the isolation structure 700 is not limited thereto, and for example, mixed energy ion implantation may be used to ensure insulation, which is not limited herein.
Next, referring to fig. 5, the dielectric layer 800 is formed.
By way of example, the dielectric layer 800 may be a silicon nitride layer, and the method of patterning the dielectric layer 800 may include using CF4And carrying out plasma etching.
Specifically, a gate region may be defined by the patterned dielectric layer 800, so as to facilitate the subsequent formation of the p-GaN cap layer 501 through the coverage and protection of the dielectric layer 800, and the exposed p-GaN layer 500 may be conveniently converted into the p-GaN passivation layer 502 in the subsequent annealing process, thereby avoiding the etching of the p-GaN layer 500. In this embodiment, the dielectric layer 800 is preferably formed by PECVD to form a silicon nitride layer, and when the gate region is defined by patterning, CF is preferably used4And performing plasma etching to ensure that the dielectric layer 800 and the p-GaN cap layer 500 have a high selective etching ratio and avoid damaging the p-GaN cap layer 500. The thickness of the dielectric layer 800 is preferably 100nm to 200nm, such as any range of 100nm, 150nm, 200nm, but not limited thereto. The material, thickness, and preparation process of the dielectric layer 800 may be adaptively adjusted according to the requirement, but are not limited thereto.
Next, referring to FIG. 6, at H2Annealing treatment is carried out in the atmosphere, and the p-GaN layer 500 and H are exposed in the p-GaN layer 5002Reacting to form Mg-H bonds to form a p-GaN passivation layer 502, and the p-GaN layer 500 covered by the dielectric layer 800 forms a p-GaN capping layer 501.
By way of example, the annealing temperature is 800 ℃ to 950 ℃, such as 800 ℃, 850 ℃, 900 ℃, but not limited thereto; the time of the annealing treatment is 10min to 15min, such as 10min, 12min, 15min and the like, but is not limited thereto; so that the exposed p-GaN layer 500 is sufficiently passivated.
Specifically, by reacting at H2The annealing treatment is performed under the atmosphere, so that the exposed p-GaN layer 500 and H can be formed2And reacting to passivate the exposed shallow level acceptor impurity Mg in the p-GaN layer 500, and converting the shallow level acceptor impurity Mg into Mg-H bonds to form the p-GaN passivation layer 502, so that the p-GaN layer 500 can be prevented from being etched, that is, the p-GaN cap layer 501 and the p-GaN passivation layer 502 can be formed, and the problems of uneven etching and etching damage of the formed p-GaN cap layer 501 can be avoided. Among them, it is preferable that the doping concentration of Mg ions in the p-GaN layer 500 is 1 × E19cm-3～5×E19cm-3E.g. 1 XE19cm-3、3×E19cm-3、5×E19cm-3And the like, thereby providing enough Mg ions to facilitate the formation of Mg-H bonds to reduce the hole concentration, converting the exposed p-GaN layer 500 into the p-GaN passivation layer 502 with high resistance to cut off the leakage channel of the p-GaN layer 500 in the HEMT device so as to improve the gate control capability; and since Mg is passivated, the hole concentration decreases rapidly, so that the p-GaN passivation layer 502 can release the originally depleted channel two-dimensional electron gas located below the AlGaN/GaN heterojunction interface. Further, the thickness of the p-GaN layer 500 is preferably 70nm to 100nm, such as 70nm, 80nm, 100nm, etc., so that after the exposed p-GaN layer 500 is passivated, a thicker p-GaN passivation layer 502 with high resistance can be formed, which is beneficial to reducing the current collapse of the HEMT device.
Referring to fig. 6, the present embodiment further provides a HEMT device having a p-GaN cap layer, where the HEMT device may be fabricated by the above fabrication process, but is not limited thereto, and the fabrication method is directly employed in the present embodiment to fabricate the HEMT device, so that materials, fabrication processes, structures, and beneficial effects of the HEMT device may be referred to in the above embodiments.
Specifically, the HEMT device includes a patterned dielectric layer 800 and an epitaxial structure, the epitaxial structure includes a GaN channel layer 300, an AlGaN barrier layer 400 and a p-GaN layer 500, wherein the p-GaN layer 500 includes a p-GaN cap layer 501 and a p-GaN passivation layer 502, the dielectric layer 800 covers the p-GaN cap layer 501, and the p-GaN passivation layer 502 is exposed on the dielectric layer 800.
As an example, the p-GaN layer 500 has a thickness of 70nm to 100nm, such as 70nm, 80nm, 100nm, etc., so that after the exposed p-GaN layer 500 is passivated, the formed thicker p-GaN passivation layer 502 with high resistance is beneficial to reducing the current collapse of the HEMT device.
As an example, the doping concentration of Mg ions in the p-GaN layer 500 is 1 × E19cm-3～5×E19cm-3E.g. 1 XE19cm-3、3×E19cm-3、5×E19cm-3And the like, thereby providing enough Mg ions to facilitate the formation of Mg-H bonds to reduce the hole concentration, converting the exposed p-GaN layer 500 into the p-GaN passivation layer 502 with high resistance to cut off the leakage channel of the p-GaN layer 500 in the HEMT device so as to improve the gate control capability; and since Mg is passivated, the hole concentration decreases rapidly, so that the p-GaN passivation layer 502 can release the originally depleted channel two-dimensional electron gas located below the AlGaN/GaN heterojunction interface.
By way of example, the dielectric layer 800 is a silicon nitride layer, and the thickness of the dielectric layer is 100nm to 200 nm. A gate region may be defined by the patterned dielectric layer 800, so that the p-GaN cap layer 501 is conveniently formed by covering and protecting the dielectric layer 800, and the exposed p-GaN layer 500 may be conveniently converted into the p-GaN passivation layer 502 in an annealing process. Preferably, the dielectric layer 800 is a silicon nitride layer, so that a high selective etching ratio between the dielectric layer 800 and the p-GaN cap layer 500 can be ensured, and the p-GaN cap layer 500 is prevented from being damaged. The thickness of the dielectric layer 800 is preferably 100nm to 200nm, such as any range of 100nm, 150nm, 200nm, etc., but is not limited thereto.
To sum up the aboveThe HEMT device with the p-GaN cap layer and the preparation method thereof provided by the invention are characterized in that H is2Annealing treatment is carried out in the atmosphere to expose the p-GaN layer and H2Reacting to form a p-GaN passivation layer, thereby avoiding etching the p-GaN layer and avoiding the problems of uneven etching and etching damage of the p-GaN cap layer; by reaction at H2Annealing treatment is carried out in the atmosphere, shallow level acceptor impurities Mg in the p-GaN layer can be passivated into Mg-H bonds, hole concentration is reduced, the p-GaN layer is converted into a high-resistance p-GaN passivation layer, and the high-resistance p-GaN passivation layer can cut off a leakage channel of the p-GaN layer in the HEMT device, so that grid control capability is improved; because Mg in the p-GaN layer is passivated, the concentration of holes in the p-GaN layer is sharply reduced, so that the p-GaN passivation layer can release two-dimensional electron gas of an originally depleted channel, which is positioned below an AlGaN/GaN heterojunction interface; the p-GaN layer outside the gate electrode is changed into a high-resistance p-GaN passivation layer, so that the reserved thick high-resistance p-GaN passivation layer is beneficial to reducing the current collapse of the HEMT device.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A preparation method of an HEMT device with a p-GaN cap layer is characterized by comprising the following steps:
providing an epitaxial structure, wherein the epitaxial structure comprises a GaN channel layer, an AlGaN barrier layer and a p-GaN layer;
forming a dielectric layer covering the p-GaN layer;
patterning the dielectric layer to expose part of the p-GaN layer;
at H2Annealing treatment is carried out in the atmosphere, and the p-GaN layer and the H layer are exposed in the p-GaN layer2React to form Mg-H bonds to form p-GaN aN passivation layer, wherein the p-GaN layer covered by the dielectric layer forms a p-GaN cap layer.
2. The method of fabricating a HEMT device with a p-GaN cap layer according to claim 1, wherein: the thickness of the p-GaN layer is 70 nm-100 nm.
3. The method of fabricating a HEMT device with a p-GaN cap layer according to claim 1, wherein: the doping concentration of Mg ions in the p-GaN layer is 1 × E19cm-3～5×E19cm-3。
4. The method of fabricating a HEMT device with a p-GaN cap layer according to claim 1, wherein: the temperature of the annealing treatment is 800-950 ℃, and the time of the annealing treatment is 10-15 min.
5. The method of fabricating a HEMT device with a p-GaN cap layer according to claim 1, wherein: the dielectric layer is a silicon nitride layer, and the method for patterning the dielectric layer comprises the step of adopting CF4And carrying out plasma etching.
6. The method of fabricating a HEMT device with a p-GaN cap layer according to claim 1, wherein: the thickness of the dielectric layer is 100 nm-200 nm.
7. A HEMT device having a p-GaN cap layer, comprising:
a patterned dielectric layer;
the epitaxial structure comprises a GaN channel layer, an AlGaN barrier layer and a p-GaN layer, wherein the p-GaN layer comprises a p-GaN cap layer and a p-GaN passivation layer, the dielectric layer covers the p-GaN cap layer, and the p-GaN passivation layer is exposed out of the dielectric layer.
8. A HEMT device with a p-GaN cap layer according to claim 7, wherein: the thickness of the p-GaN layer is 70 nm-100 nm.
9. A HEMT device with a p-GaN cap layer according to claim 7, wherein: the doping concentration of Mg ions in the p-GaN layer is 1 × E19cm-3～5×E19cm-3。
10. A HEMT device with a p-GaN cap layer according to claim 7, wherein: the dielectric layer is a silicon nitride layer, and the thickness of the dielectric layer is 100 nm-200 nm.
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