CN113113469A - 一种高耐压双栅极横向hemt器件及其制备方法 - Google Patents

一种高耐压双栅极横向hemt器件及其制备方法 Download PDF

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CN113113469A
CN113113469A CN202110259511.5A CN202110259511A CN113113469A CN 113113469 A CN113113469 A CN 113113469A CN 202110259511 A CN202110259511 A CN 202110259511A CN 113113469 A CN113113469 A CN 113113469A
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尹以安
李佳霖
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South China Normal University
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Abstract

本发明涉及一种高耐压双栅极横向HEMT器件，包括位于衬底上的缓冲层以及依次层叠于缓冲层上的GaN沟道层、AlN***层和AlGaN势垒层组成的叠层，还包括p型埋层、位于p型埋层上的栅极和位于势垒层上的源/漏极和Γ型栅；沿厚度方向上，p型埋层自缓冲层靠近沟道层的表面朝向缓冲层中远离沟道层的一侧延伸一定深度；源极和漏极位于势垒层表面；源极和漏极之间设置一栅槽，Γ型栅位于栅槽中并朝向漏极一侧延伸；沿长度方向上，p型埋层自栅极下方延伸至栅槽下方。通过p型埋层的引入、双栅结合AlGaN/AlN/GaN异质结的结构设置，本发明获得了低导通电阻、高饱和电流、高击穿电压和低泄露电流HEMT器件。

Description

一种高耐压双栅极横向HEMT器件及其制备方法
技术领域
本发明涉及HEMT器件技术领域，尤其涉及一种高耐压双栅极横向HEMT器件及其制备方法。
背景技术
AlGaN/GaN HEMT器件，在高功率、高工作温度、强抗辐照能力等性能方面的潜能已然超越了Si基功率器件，其不仅具有GaN材料的优势，而且AlGaN/GaN异质结界面处产生极化电场，能够形成高迁移率和高载流子面密度的二维电子气(2DEG)，在电力电子领域受到了极大的关注。
虽然AlGaN/GaN HEMT器件在理论上具有很高的耐压特性，但实际器件的击穿电压只有几百伏，离GaN材料的理论耐压极限还有很大差距，限制着GaN基HEMT器件的大规模应用。其耐压低的主要原因有：(1)栅极电场的集中效应。当器件处在关断状态下时，电场线集中在栅极边缘，在栅极靠漏一侧出现电场峰值，使器件提前击穿；(2)缓冲层的泄漏电流。在关断状态下，从源极注入的电子经过缓冲层到达漏极形成电流通道，造成器件的提前击穿。因此，提高HEMT器件的耐压能力对改善其性能具有非常重要的意义。
发明内容
本发明的首要目的在于提供一种高耐压双栅极横向HEMT器件及其制备方法，以克服现有技术中的不足，获得低导通电阻、高饱和电流、高击穿电压和低泄漏电流的HEMT器件。
本发明提供的高耐压双栅极横向HEMT器件，既可由P型栅极与MIS槽栅共同控制，同时也可由P型栅极与MIS栅独立控制。通过在部分GaN沟道层中离子注入形成p型埋层，形成了独立的P-GaN栅极结构，参与调控沟道层的二维电子气。其作用机理如下：p型埋层与GaN沟道层构成PN结，形成空间电荷区，消耗一部分2DEG，提高了器件的阈值电压。p型GaN栅极位于AlGaN势垒层、AlN***层和GaN沟道层构成的AlGaN/AlN/GaN异质结叠层一侧，在器件工作状态下，P-GaN栅极接正电压，GaN沟道层的源极接负电压，此时PN结正向导通，空间电荷区减小，降低了源漏的导通电阻，提高了正向输出电流。当器件处于关断状态，P-GaN栅极接负电压，GaN沟道层的漏极接正电压，PN结处于反向偏压，同时与GaN缓冲层也形成PN结反向偏压，不仅减少了栅极泄漏电流，也减少了缓冲层的泄漏电流，大大提高了器件的耐压特性。而MIS槽栅则是通过刻蚀部分AlGaN势垒层形成，降低了栅极下方势垒层的厚度，使阈值电压正移，提高栅控能力。同时，在MIS槽栅朝向漏极一侧引入Γ型栅场板，能够优化栅极电场分布，减低栅极电场集中效应，提高器件的耐压特性。
其次在GaN沟道层和AlGaN势垒层之间***AlN层形成更深而窄的量子阱，提高了沟道电子密度，同时抑制2DEG渗入到AlGaN势垒层中，提高了沟道电子迁移率且抑制了电流崩塌。
另外，本发明的横向HEMT器件的制备方法简单，可行性高，制备的器件稳定性良好。基于上述目的，本发明至少提供如下技术方案：
一种高耐压双栅极横向HEMT器件，包括：衬底、位于衬底上的缓冲层以及依次层叠于缓冲层上的GaN沟道层、AlN***层和AlGaN势垒层组成的叠层，还包括p型埋层、位于p型埋层上的p型栅极和位于势垒层上的源极、漏极和Γ型栅；其中，沿厚度方向上，p型埋层自所述缓冲层靠近沟道层的表面朝向缓冲层中远离所述沟道层的一侧延伸一定深度；源极和漏极位于势垒层表面；源极和漏极之间还设置一栅槽，该栅槽延伸至势垒层中一定深度，一高介电介质层设置于该栅槽内壁，Γ型栅位于该栅槽中并沿栅槽指向漏极的方向延伸；沿长度方向上，p型埋层自栅极下方延伸至栅槽下方。
进一步地，所述p型埋层的掺杂浓度大于等于108cm-3，厚度为70～150nm，长度为3～5μm。
进一步地，AlGaN势垒层、高介电介质层和Γ型栅构成MISΓ型槽栅结构。
进一步地，所述缓冲层优选GaN缓冲层，所述p型埋层选用F+离子源注入缓冲层中形成。
进一步地，所述栅极与所述叠层之间设置有第一钝化层，所述Γ型栅与源极之间以及所述Γ型栅与漏极之间设置有第二钝化层。
进一步地，所述GaN沟道层的厚度为8～15nm；所述势垒层选用Al组分为1％～3％，厚度为15～30nm的AlGaN势垒层；所述AlN***层的厚度为1～2nm。
进一步地，所述高介电介质层选用HfO2、Al2O3或TiO2，其厚度为4～6nm。
进一步地，所述钝化层包括SiNx、SiO2、HfO2或Al2O3。
进一步地，所述栅槽靠近所述源极。
本发明还提供一种高耐压双栅极横向HEMT器件的制备方法，包括以下步骤：
在衬底上外延生长缓冲层；
在所述缓冲层的特定区域离子注入形成p型埋层；
在所述p型埋层以及缓冲层的表面依次外延生长GaN沟道层、AlN***层和AlGaN势垒层形成叠层；
刻蚀该叠层的预定区域暴露部分p型埋层区域；
在p型埋层和AlGaN势垒层表面沉积钝化层；
刻蚀p型埋层表面的钝化层和势垒层表面的钝化层，形成栅极和源/漏极开孔；
沉积金属层形成欧姆接触的源/漏极和栅极；
刻蚀源极和漏极之间的钝化层至势垒层中一定深度形成栅槽；
在栅槽内壁生长一定厚度的高介电介质层；
沉积金属层形成肖特基接触的Γ型栅。
附图说明
图1是本发明实施例高耐压双栅极横向HEMT器件的结构示意图。
图2是本发明实施例高耐压双栅极横向HEMT器件的工作状态示意图。
图3是本发明实施例高耐压双栅极横向HEMT器件的击穿状态的示意图。
图4是本发明实施例高耐压双栅极横向HEMT器件的制备工艺流程图。
图5是本发明实施例高耐压双栅极横向HEMT器件的直流特性图。
图6是本发明实施例高耐压双栅极横向HEMT器件的击穿电压图。
具体实施方式
接下来将结合本发明的附图对本发明实施例中的技术方案进行清楚、完整地描述，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，可以做出结构或逻辑的变化而不脱离本发明的范围。本发明的范围由所附权利要求限定。
本说明书中使用例如“之下”、“下方”、“下”、“之上”、“上方”、“上”等空间相对性术语，以解释一个元件相对于第二元件的定位。除了与图中所示那些不同的取向以外，这些术语意在涵盖器件的不同取向。
另外，使用诸如“第一”、“第二”等术语描述各个元件、区域、区段等，并非意在进行限制。使用“厚度方向上”理解为表示垂直于半导体材料或载体的表面范围延伸的方向或范围。本说明书中“长度方向上”特定理解为源极指向漏极或漏极指向源极的方向。使用的“具有”、“含有”、“包含”、“包括”等是开放式术语，表示存在所陈述的元件或特征，但不排除额外的元件或特征。除非上下文明确做出不同表述。
下面来对本发明做进一步详细的说明。图1示出了根据优选实施例的横向HEMT器件的结构示意图。在该实施例中，横向HEMT包括衬底1和布置于衬底1上的缓冲层3。衬底1可以包括Si、蓝宝或SiC。缓冲层3优选GaN缓冲层，GaN缓冲层的厚度为2～5μm，优选地，GaN缓冲层的厚度为3.5μm。在该优选实施例中，衬底1与缓冲层3之间还包含一AlN成核层2。
在图1所示的实施例中，沟道层5、***层6和势垒层7构成的叠层布置于缓冲层3的部分表面。沟道层5优选GaN沟道层，GaN沟道层的厚度为8～15nm。在优选实施例中，***层6优选AlN***层，其厚度为1～2nm，优选地，AlN***层的厚度为1nm。势垒层7优选AlGaN势垒层，其中Al组分为1％-3％，厚度为15-30nm。该优选实施例中，在GaN沟道层和AlGaN势垒层之间***AlN层，不仅能形成更深而窄的量子阱，提高了沟道电子密度；还能抑制2DEG渗入到AlGaN势垒层中，提高了沟道电子迁移率且抑制了电流崩塌，从而提高了器件的击穿电压。
该横向HEMT还包括源极10、漏极9、p型栅极11和Γ型栅14。p型栅极11即p型GaN栅极，被配置为布置于缓冲层3的表面、叠层的一侧，栅极11通过第二钝化层12与叠层隔离。源极10和漏极9布置在势垒层7上，第一钝化层8布置在源极10和漏极9之间，一栅槽沿第一钝化层8的表面延伸至势垒层7中一定深度，栅槽的内壁上设置有一定厚度的高介电介质层13。Γ型栅14设置于该栅槽中，且自该栅槽延伸至栅槽与漏极9之间的第一钝化层8的表面。该Γ型栅14、高介电介质层13和AlGaN势垒层7构成了MISΓ型栅结构。该MISΓ型栅结构在功能上既能起到MIS槽栅结构的作用，又能够沿漏极一侧起到Γ型栅场板结构的作用。首先槽栅可减薄势垒层，减少二维电子气，使阈值电压正移，提高器件控栅能力。其次，选用高介电常数介质作为栅介质层，可提高器件的频率特性，且介质层材料禁带宽度越大，可形成越高的导带不连续性，即减小了栅漏电，也提高器件的击穿特性。进一步地采用场板结构，缓解了栅极电场集中的现象，使电场分布更加均匀，进一步提高了器件的耐压特性。具体地，栅槽靠近源极10。高介电介质层选用HfO2、Al2O3或TiO2，其厚度为4-6nm。第一钝化层和第二钝化层包括SiNx、SiO2、HfO2或Al2O3。
该横向HEMT还包括p型埋层4。在一优选方案中，p型埋层4优选F+离子源注入部分缓冲层3中进行掺杂形成。埋层4的厚度为70～150nm，长度为3～5μm，其掺杂浓度大于等于108cm-3。优选地，埋层4的载流子浓度为1×1018cm-3，其长度为3μm，厚度为100nm。
p型栅极11布置为与p型埋层4接触形成p型栅极。具体地，沿厚度方向上，p型埋层4布置于自缓冲层3与栅极11接触的表面朝向缓冲层中远离沟道层5的一侧延伸一定深度。沿长度方向上，p型埋层4自栅极11的正下方延伸至栅槽的正下方。该实施例中，引入p型埋层形成p型栅，p型GaN与GaN沟道层形成PN结，利用PN结二极管的特性调节沟道层内的电子气浓度和电场强度，器件关断状态下，可减小2DEG，提高HEMT器件的阈值电压，减小泄漏电流和提高击穿电压，增强器件的可靠性。器件导通时，PN结正向导通，降低导通电阻，提高导通电流。
源极10、漏极9和p型栅极11为欧姆接触。优选地，源极10、漏极9和p型栅极11选用Ti/Al/Ni/Au合金、Ti/Al/Mo/Au合金或Ti/Al/Ti/TiN合金。Γ型栅14为肖特基接触。优选地，Γ型栅选用Ni/Au合金。
图2是优选实施例的横向HEMT器件处于工作状态的示意图。该工作状态中，p型GaN栅极接正电压，源极接负电压，PN结处于正向导通状态，空间电荷区减小，降低了源漏导通电阻，提高了正向输出电流。同时，P-GaN埋层与GaN缓冲层形成的PN结也可以减小部分泄漏电流。参见图5的器件直流特性图，在栅极电压为3V恒定不变的条件下，源漏电压增至10V时，导通电流可高达827mA/mm。
图3为优选实施例的横向HEMT器件处于击穿状态的示意图。P-GaN栅极接负电压，GaN沟道层的漏极接正电压，PN结处于反向截止状态，同时与GaN缓冲层也形成PN结反向偏压，不仅减少了栅极泄漏电流，也减少了缓冲层的泄漏电流，大大提高了器件的耐压特性。如图6所示，该状态下，横向HEMT器件的击穿电压可高达2500V。
功率器件的优值FOM定义为：
Figure BDA0002969211910000071
其中，Bv是器件的击穿电压，RON是器件的特征导通电阻。高的击穿电压，小的特征导通电阻是功率器件所追求的目标。上述优选实施例获得的优值FOM高达15.39GW·cm2。
基于上述横向HEMT器件，参见图4，本发明一优选实施例还提供了该器件的制备方法，该制备方法工艺流程简单，可行性高，制备的器件稳定性良好。该方法包括以下步骤：
在衬底上依次外延生长缓冲层和沟道层。在一优选实施例中，衬底选用蓝宝石衬底，缓冲层和衬底之间还设置一AlN成核层。具体地，首先，清洗蓝宝石衬底1。将衬底依次置于丙酮、乙醇、去离子水中各超声10分钟，取出后用去离子水进行冲洗，最后用N2吹干，去除衬底表面的污染物。然后选用MOCVD技术生长厚度为1nm的AlN成核层和厚度为3.53μm的GaN缓冲层3。
接着，采用离子注入机将F+离子源直接注入GaN缓冲层3的选定表面，注入能量为11keV，注入剂量为2×1018cm-2，注入角度为正8°，在GaN缓冲层的特定区域形成p型GaN埋层4。
之后，继续用MOCVD工艺依次生长厚度为10nm的GaN沟道层5、厚度为1nm的AlN***层6和厚度为30nm的AlGaN势垒层7，形成GaN/AlN/AlGaN异质结。其中，AlGaN势垒层7的Al组分为1％～3％。
接着，采用感应耦合等离子体刻蚀(ICP)工艺对外延片选定区域进行刻蚀至p型GaN埋层4的表面。
之后，选用离子增强型化学气相沉积(PECVD)工艺，在p型GaN埋层4和AlGaN势垒层7表面沉积SiNx钝化层8。
继续刻蚀钝化层，在p型埋层的钝化层中和势垒层的钝化层中形成栅极和源/漏极开孔。优选地，选用反应离子刻蚀(RIE)，在SiNx钝化层8选定区域进行开孔，用于沉积金属电极。
选用电子束蒸发工艺，分别在栅极开孔位置和源/漏极开孔位置沉积Ti/Al/Ni/Au金属电极，之后在880℃的氮气气氛中快速退火40s，形成欧姆接触的源极、漏极和p型GaN栅极。优选地，金属Ti层、Al层、Ni层和Au层的厚度分别为20nm、100nm、40nm和120nm。
接着，采用光刻工艺刻蚀源极和漏极之间的钝化层形成凹槽图形，之后选用ICP干法刻蚀工艺继续刻蚀部分AlGaN势垒层形成栅槽。优选地，势垒层的刻蚀深度为10nm。
接着在栅槽中生长高介电介质层，优选地，选用PEALD工艺在栅槽内壁上生长6nm的HfO2高介电介质层作为栅介质层。
接着淀积栅极金属，采用电子束蒸发工艺在栅槽中沉积Ni/Au金属作为栅电极，并在氮气气氛下，温度为40℃的条件下退火10min，形成MIS槽栅。
继续采用电子束蒸发工艺在上述形成的MIS槽栅旁继续沉积Ni/Au金属，并在氮气气氛下，温度为40℃的条件下退火10min，形成肖特基接触的Γ型栅。
上述实施例为本发明较佳的实施方式，但本发明的实施方式并不受上述实施例的限制，其他的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化，均应为等效的置换方式，都包含在本发明的保护范围之内。

Claims (10)

1.一种高耐压双栅极横向HEMT器件，其特征在于，包括：衬底、位于衬底上的缓冲层以及依次层叠于缓冲层上的GaN沟道层、AlN***层和AlGaN势垒层组成的叠层，还包括p型埋层、位于p型埋层上的p型栅极和位于势垒层上的源极、漏极和Γ型栅；其中，
沿厚度方向上，p型埋层自所述缓冲层靠近沟道层的表面朝向缓冲层中远离所述沟道层的一侧延伸一定深度；
源极和漏极位于势垒层表面；
源极和漏极之间还设置一栅槽，该栅槽延伸至势垒层中一定深度，一高介电介质层设置于该栅槽内壁，Γ型栅位于该栅槽中并沿栅槽指向漏极的方向延伸；
沿长度方向上，p型埋层自栅极下方延伸至栅槽下方。
2.根据权利要求1的所述高耐压双栅极横向HEMT器件，其特征在于，所述p型埋层的掺杂浓度大于等于108cm-3，厚度为70～150nm，长度为3～5μm。
3.根据权利要求1的所述高耐压双栅极横向HEMT器件，其特征在于，AlGaN势垒层、高介电介质层和Γ型栅构成MISΓ型槽栅结构。
4.根据权利要求1至3之一的所述高耐压双栅极横向HEMT器件，其特征在于，所述缓冲层优选GaN缓冲层，所述p型埋层选用F+离子源注入缓冲层中形成。
5.根据权利要求1至3之一的所述高耐压双栅极横向HEMT器件，其特征在于，所述栅极与所述叠层之间设置有第一钝化层，所述Γ型栅与源极之间以及所述Γ型栅与漏极之间设置有第二钝化层。
6.根据权利要求1至3之一的所述高耐压双栅极横向HEMT器件，其特征在于，所述GaN沟道层的厚度为8～15nm；所述势垒层选用Al组分为1％～3％，厚度为15～30nm的AlGaN势垒层；所述AlN***层的厚度为1～2nm。
7.根据权利要求1至3之一的所述高耐压双栅极横向HEMT器件，其特征在于，所述高介电介质层选用HfO2、Al2O3或TiO2，其厚度为4～6nm。
8.根据权利要求1至3之一的所述高耐压双栅极横向HEMT器件，其特征在于，所述钝化层包括SiNx、SiO2、HfO2或Al2O3。
9.根据权利要求1至3之一的所述高耐压双栅极横向HEMT器件，其特征在于，所述栅槽靠近所述源极。
10.一种高耐压双栅极横向HEMT器件的制备方法，其特征在于，包括以下步骤：
在衬底上外延生长缓冲层；
在所述缓冲层的特定区域离子注入形成p型埋层；
在所述p型埋层以及缓冲层的表面依次外延生长GaN沟道层、AlN***层和AlGaN势垒层形成叠层；
刻蚀该叠层的预定区域暴露部分p型埋层区域；
在p型埋层和AlGaN势垒层表面沉积钝化层；
刻蚀p型埋层表面的钝化层和势垒层表面的钝化层，形成栅极和源/漏极开孔；
沉积金属层形成欧姆接触的源/漏极和栅极；
刻蚀源极和漏极之间的钝化层至势垒层中一定深度形成栅槽；
在栅槽内壁生长一定厚度的高介电介质层；
沉积金属层形成肖特基接触的Γ型栅。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113871477A (zh) * 2021-08-30 2021-12-31 瑶芯微电子科技(上海)有限公司 基于栅极场板和源极场板的双异质结hemt器件及其制备方法
CN113964192A (zh) * 2021-09-06 2022-01-21 西安电子科技大学 基于非极性GaN的肖特基二极管及其制备方法
CN114038907A (zh) * 2021-10-21 2022-02-11 华南师范大学 一种双栅控制的高耐压双沟道增强型hemt及其制备方法
CN114284355A (zh) * 2021-12-27 2022-04-05 西交利物浦大学 双栅极mis-hemt器件、双向开关器件及其制备方法
CN115566053A (zh) * 2022-09-30 2023-01-03 苏州汉骅半导体有限公司 半导体器件及其制备方法

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090072272A1 (en) * 2007-09-17 2009-03-19 Transphorm Inc. Enhancement mode gallium nitride power devices
US20100224908A1 (en) * 2009-03-04 2010-09-09 Panasonic Corporation Semiconductor device
US20130221409A1 (en) * 2010-07-28 2013-08-29 The University Of Sheffield Semiconductor devices with 2deg and 2dhg
CN104167445A (zh) * 2014-08-29 2014-11-26 电子科技大学 具有埋栅结构的氮化镓基增强耗尽型异质结场效应晶体管
CN106298911A (zh) * 2016-10-31 2017-01-04 电子科技大学 一种双结型栅氮化镓异质结场效应管
US20170373178A1 (en) * 2016-06-24 2017-12-28 Cree, Inc. Gallium Nitride High-Electron Mobility Transistors with Deep Implanted P-Type Layers in Silicon Carbide Substrates for Power Switching and Radio Frequency Applications and Process for Making the Same
US20170373176A1 (en) * 2016-06-24 2017-12-28 Cree Fayetteville, Inc. Gallium nitride high-electron mobility transistors with p-type layers and process for making the same
CN107658334A (zh) * 2016-07-25 2018-02-02 瑞萨电子株式会社 半导体器件和制造半导体器件的方法
CN109004028A (zh) * 2018-06-22 2018-12-14 杭州电子科技大学 一种具有源极相连P埋层和漏场板的GaN场效应晶体管
CN109037325A (zh) * 2018-06-22 2018-12-18 杭州电子科技大学 一种具有电极相连PIN埋管的GaN场效应晶体管
CN109037326A (zh) * 2018-07-18 2018-12-18 大连理工大学 一种具有p型埋层结构的增强型hemt器件及其制备方法
CN111415986A (zh) * 2019-01-07 2020-07-14 半导体元件工业有限责任公司 电子器件

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090072272A1 (en) * 2007-09-17 2009-03-19 Transphorm Inc. Enhancement mode gallium nitride power devices
US20100224908A1 (en) * 2009-03-04 2010-09-09 Panasonic Corporation Semiconductor device
US20130221409A1 (en) * 2010-07-28 2013-08-29 The University Of Sheffield Semiconductor devices with 2deg and 2dhg
CN104167445A (zh) * 2014-08-29 2014-11-26 电子科技大学 具有埋栅结构的氮化镓基增强耗尽型异质结场效应晶体管
US20170373178A1 (en) * 2016-06-24 2017-12-28 Cree, Inc. Gallium Nitride High-Electron Mobility Transistors with Deep Implanted P-Type Layers in Silicon Carbide Substrates for Power Switching and Radio Frequency Applications and Process for Making the Same
US20170373176A1 (en) * 2016-06-24 2017-12-28 Cree Fayetteville, Inc. Gallium nitride high-electron mobility transistors with p-type layers and process for making the same
CN107658334A (zh) * 2016-07-25 2018-02-02 瑞萨电子株式会社 半导体器件和制造半导体器件的方法
CN106298911A (zh) * 2016-10-31 2017-01-04 电子科技大学 一种双结型栅氮化镓异质结场效应管
CN109004028A (zh) * 2018-06-22 2018-12-14 杭州电子科技大学 一种具有源极相连P埋层和漏场板的GaN场效应晶体管
CN109037325A (zh) * 2018-06-22 2018-12-18 杭州电子科技大学 一种具有电极相连PIN埋管的GaN场效应晶体管
CN109037326A (zh) * 2018-07-18 2018-12-18 大连理工大学 一种具有p型埋层结构的增强型hemt器件及其制备方法
CN111415986A (zh) * 2019-01-07 2020-07-14 半导体元件工业有限责任公司 电子器件

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
尹以安等: ""Mg掺与GaN晶格匹配的InAlN特性研究"", 《电子元件与材料》, vol. 34, no. 8, pages 1 - 4 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113871477A (zh) * 2021-08-30 2021-12-31 瑶芯微电子科技(上海)有限公司 基于栅极场板和源极场板的双异质结hemt器件及其制备方法
CN113964192A (zh) * 2021-09-06 2022-01-21 西安电子科技大学 基于非极性GaN的肖特基二极管及其制备方法
CN114038907A (zh) * 2021-10-21 2022-02-11 华南师范大学 一种双栅控制的高耐压双沟道增强型hemt及其制备方法
CN114284355A (zh) * 2021-12-27 2022-04-05 西交利物浦大学 双栅极mis-hemt器件、双向开关器件及其制备方法
CN115566053A (zh) * 2022-09-30 2023-01-03 苏州汉骅半导体有限公司 半导体器件及其制备方法
CN115566053B (zh) * 2022-09-30 2023-10-20 苏州汉骅半导体有限公司 半导体器件及其制备方法

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