CN1130806A - 制造具有各种金属氧化物半导体场效应晶体管的半导体器件的方法 - Google Patents

制造具有各种金属氧化物半导体场效应晶体管的半导体器件的方法 Download PDF

Info

Publication number
CN1130806A
CN1130806A CN95118439A CN95118439A CN1130806A CN 1130806 A CN1130806 A CN 1130806A CN 95118439 A CN95118439 A CN 95118439A CN 95118439 A CN95118439 A CN 95118439A CN 1130806 A CN1130806 A CN 1130806A
Authority
CN
China
Prior art keywords
logic circuit
circuit component
semiconductor device
volatile memory
source electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN95118439A
Other languages
English (en)
Other versions
CN1052573C (zh
Inventor
工藤隆治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CN1130806A publication Critical patent/CN1130806A/zh
Application granted granted Critical
Publication of CN1052573C publication Critical patent/CN1052573C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

在制造包括分别用于非易失存储器元件、输入保护元件和逻辑电路元件的第一、第二和第三MOSFET的半导体器件的方法中，各栅极结构在P型基片上形成。在该基片中以与第三MOSFET的栅极结构自对准方式注入第一剂量的n型杂质，以形成源极和漏极区域。在该基片中，以与第一和第二MOSFET的栅极结构自对准方式同时注入n型杂质以形成源极和漏极区域。在第三MOSFET的源极和漏极区域的几个部分中注入高于第一剂量的第二剂量的n型杂质。

Description

制造具有各种金属氧化物半导体场 效应晶体管的半导体器件的方法
本发明涉及制造在其中具有非易失存储器的半导体器件的方法，特别是制造由单漏极结构晶体管和诸如轻掺杂漏极(LDD)结构或者过渡连接结构那样的双漏极结构晶体管组成的半导体器件的方法。
通常，在像单片微计算机芯片的半导体器件中，随机存取存储器(RAM)电路和只读存储器电路(ROM)设置在同一芯片上，而逻辑电路则设在此芯片外。在这种情况中，至少ROM的一部分构成像电可编程只读存储器(EPMOM)那样的非易失存储器。在具有片内非易失存储器的半导体器件中，至少需要三种类型的金属氧化物半导体场效应晶体管(以下简称MOSFET)，如逻辑电路的MOSFET，存储元件的MOSFET(包括具有双栅电极结构的MOSFET)和输入保护MOSFET。在这些MOSFET中，逻辑电路MOSFET最好包含有像轻掺杂漏极结构或缓变结结构那样的双漏极结构形成的源极和漏极区域，以便承受热电子，因为MOSFET必须有抵抗热电子的性能。存储器元件MOSFET中有用单漏极结构形成的源极和漏极区域，因为在非易失存储元件中必须对数据写入有效地产生热电子。在输入保护MOSFET中，用具有低电阻率的单漏极结构形成源极和漏极区域，因为这可以防止由于静电荷的输入引发对MOSFET的致热损坏。
下面参照图1A至1E说明上述制造半导体器件的传统方法。
如图1A所示，P型硅基片111设有存储元件形成区域102a、用于输入保护的MOSFET形成区域102b，和在表面区域上用于逻辑电路的MOSFET形成区域102c。在存储器元件形成区域102a中由浮置栅极115a、绝缘膜114和控制栅极115b组成的双栅极结构113a通过栅极绝缘膜112在基片111上形成。在MOSFET形成区域102b和102c中，单栅极结构的栅电极113b和113c通过栅极绝缘膜112在基片111上形成。需要指出的是用于隔离元件的绝缘膜和区域未在图中显示，因为它们已被本领域普通技术人员所知。此后，磷离子以100Kev的加速能量和2～3×1013/cm2注入量以自对准方式对着双栅结构113a及栅电极113b和113c注入基片111，作为其掩膜形成n型低注入量扩散层116。
然后，如图1B所示，光致抗蚀剂层119在基片的整个表面形成，随后从构成用于第一光致抗蚀剂掩膜区域102a的存储元件移走光致抗蚀剂层119。其结果是形成区域102b和102c的MOSFET保持被光致抗蚀剂层119覆盖。接着，砷离子以70Kev加速能量和5.0×1015/cm2注入量以对双栅结构113a自调整方式注入基片111使其作为掩膜。其结果是n型高注入量的扩散层118被形成。n型扩散层118的功能是作为具有单漏极结构的存储器元件MOSFET的源极和漏极区域。
然后，如图1C所示，移走光致抗蚀剂层119并通过低压力CVD方法在整个基片111上附着硅氧化膜。通过各向导性的离子体蚀刻的方法内蚀刻硅氧化膜，以便边壁绝缘膜120a、120b和120c在双栅极结构和栅电极113b、113c的边壁上形成。
然后，如图1D所示，光致抗蚀剂层121在基片111的整个表面形成，随后光致抗蚀剂121从构成用于第二感光致抗蚀剂膜的逻辑电路区域102C和MOSFET移走，以便形成区域102a的存储元件和形成输入保护区域102的MOSFET保留光致抗蚀剂层121的覆盖。接着砷离子以70Kev加速能量和3.0×1015/cm2注入量以对栅电极113C和边壁绝缘膜120C自对准方式注入基片111，使它们作为掩膜。其结果是在保留低浓度n型扩散层122的同时，形成n型高注入量扩散层112。因此，用于逻辑电路的MOSFET形成了具有像过渡连接结构或LDD结构那样的双漏极结构的源极和漏极区域。
最后，如图1E所示，光致抗蚀剂层123在基片111的整个表面形成，随后光致抗蚀剂层从构成输入保护区域102b的MOSFET移走，用于第三光致抗蚀剂掩膜，所以，形成区域102a的存储器元件和形成逻辑电路区域102C的MOSFET保留被光致抗蚀剂层123的覆盖。接着，磷离子以70Kev加速能量和1.0×1015/cm2剂量对栅电极113b和边壁绝缘膜120b以自对准方式注入基片111，使其作为掩膜。因此在保留低渗透浓度n型扩散层116的同时，形成了高剂量的n型扩散层124。在离子注入后进行热处理，此时由于磷离子具有比磷离子高的扩散系数，磷离子从n型高剂量扩散层向边壁绝缘膜120b下面的部分扩散，所以具有单漏极结构的源极和漏极区域被完成。
在如上所述的制造具有非易失存储器的半导体器件的传统方法中，具有用于存储元件和输入保护的单漏极结构的MOSFET和具有用于逻辑电路的双漏极结构的MOSFET是通过这样一种处理过程形成的，即以低剂量将杂质同注入所有的MOSFET和高剂量将质逐一注入每一个MOSFET。因此需要3种掩膜处理和4种离子离子注入处理。因而，要降低半导体器件的生产成本和提高产品的生产效率都是很困难的。
本发明是出于上述观点提出的，其发明目的是提供一种具有简化处理过程的制造半导体器件的方法，该半导体器件具有各种类型的MOSFET。
本发明的另一目的是提供一种制造半导体器件的方法，它能根据漏极结构简化制造方法。
为实现本发明的目的，制造包含在单片芯片上的非易失存储元件，输入保护元件和逻辑电路元件的半导体器件的方法包括以下步骤：
a)在第一导电型基片上形成非易失存储器元件、输入保护元件和逻辑电路元件的栅极结构；
b)在基片中对具有第一剂量的用于逻辑电路元件的栅极结构以自对准方式注入第二导电型杂质以构成逻辑电路元件的源极和漏极区域；
c)在基片中，对非易失存储元件和输入保护元件的栅极结构以自对准方式同步地注入第二导电型杂质，以形成非易失存储器元件和输入保护元件的源极和漏极区域；
d)除了具有比第一注入量高的第二剂量的栅极结构外，在逻辑电路元件的源极和漏极区域的几个部分中注入第二导电型杂质。
非易失存储元件，输入保护元件和逻辑电路元件可以是分别需要有产生热电子性能的第一类型的MOSFET、需要有阻止静电损坏性能的第二类型MOSFET，和需要有阻止热电子的第三类型的MOSFET。
边壁绝缘膜在逻辑电路元件的注入之前优先在非易失存储器元件，输入保护元件和逻辑电路元件的每一个边壁上形成，如果有了边壁绝缘膜，在逻辑电路元件的源极和漏极几个部分中对准边壁绝缘膜和逻辑电路元件的栅极结构注入第二导电型杂质。在这种情况，能够进行注入以形成具有轻掺杂漏极结构的漏极区域或者形成具有缓变结结构的源极和漏极区域。
为了形成非易失存储器元件和输入保护元件的源极和漏极区域，最好用第一剂量以和非易失存储器元件，输入保护元件和逻辑电路元件的栅极结构以自对准方式在基片中同步地注入第二导电型杂质。磷离子的注入在步骤(b)中执行，砷离子的注入在步骤(c)和(d)中执行。在步骤(c)中通过使用作第一掩膜的光致抗蚀剂遮掩要形成的逻辑电路区域；在步骤(d)中通过作为第二掩膜的光致抗蚀剂遮掩要形成的固定存储部件和输入保护部件的区域。
为了完成本发明的另一目的，包含在单片芯片上的需要有能力产生热电子的第一类MOSFET，需要有阻止静电击穿的第二类MOSFET，和需要有阻止热电子的第三类的MOSFET的制造半导体器件的方法包括以下步骤：
(a)在第一导电型基片上形成第一至第三类MOSFET栅极结构；
(b)为遮掩第三类MOSFET，形成使用第一掩膜的第一和第二类MOSFET；知
(c)为遮掩第一和第二类MOSFET，形成使用第二掩膜的第三类MOSFET。
图1A至1E是通过显示制造具有片内非易失存储器的半导体器件的传统方法示意图；
图2A至2D是显示本发明的制造具有片内存储器的半导体器件的方法示意图。
本发明的制造具有片内非易失存储器的半导体器件的方法将参照附图进行详细说明。
首先，参照图2A，P型硅基片11设有形成像EPROM那样的存储元件区域2a的MOSFET，形成输入保护区域2b的MOSFET，和在表面区域上形成逻辑电路区域2c的MOSFET。在形成存储元件区域2a的MOSFET中，由栅电极15a、绝缘膜14和控制栅电极15组成的双栅电极结构13a通过栅极绝缘膜12在基片11上形成。在形成区域2b和2c的MOSFET中，单栅结构的栅电极13b和13c通过栅极绝缘膜12在基片11上形成。需要说明的是隔离元件的膜和区域未在图中显示，因为它们已被本领域的普通技术人员所熟知。接下来磷离子以100Kev加速能量和2至3×1013/cm2剂量与作为掩膜的双栅结构13a和单栅电极13b和13c以自对准注入基片11中，以形成低注入量的n型扩散层116。
然后，如图2B所示，感光性树脂层19在基片11的整个表面形成，随后光致抗蚀剂层19从形成存储器元件，输入保护和用于第一光致抗蚀剂掩膜的区域2a和2b的MOSFET中移走，其结果是形成区域2c的MOSFET保留被光致抗蚀剂层19覆盖。接着，砷离子对双栅极结构13a和单栅极结构13b以自对准方式以70Kev加速能量和5.0×1015/cm2剂量注入基片11中，使它们掩膜，其结果是在层18下面保留低剂量n型扩散层16的同时，形成高剂量的n型扩散层18。n型扩散层18的功能是作为具有单漏极结构的MOSFET的源极和漏极区域。在形成区域2a的MOSFET的源极和漏极区域中，最理想的情形是杂质掺加量要高，因为它可以使热电子有效地产生。在形成区域2b的MOSFET的源极和漏极区域中，最理想的情况是杂质掺加量也要高，因为它可以使静电荷有效的释放。这样就可以从对非易失存储元件的MOSFET所期望的杂质掺加量的区域和对输入保护重叠的MOSFET所期望的杂质掺加量的区域选择有效的杂质掺加量。
然后，如图2C所示，移走层19并通过低压力CVD方法在整个基片111上附着硅氧化膜。通过各向异性的等离子体蚀刻的方法深蚀刻硅氧化膜。所以边壁绝缘膜20a、20b和20c在单栅极结构13a和单栅电极13b、13c的边壁上形成。
然后，如图2D所示，在基片11的整个表面上形成光致抗蚀剂层21，随后，从形成逻辑电路区域2C的MOSFET移走感光性树脂层21以用于第二光致抗蚀剂掩膜，所以，形成区域2a和2b的MOSFET保留光致抗蚀剂层21的覆盖。接着砷离子以70Kev加速能量和3.0～5.0×1015/cm2注入剂量与作为掩膜的栅电极13C和边壁绝缘膜20C以自对准方式注入基片。其结果是在低剂量扩散层16的部分上形成高剂量的n型扩散层22。因此对逻辑电路的MOSFET而言，具有如LDD结构或缓变结结构的双漏极结构的源极和漏极区域可以被完成，因而热电子的产生可以被抑制。
如上所述，本发明的具有单漏极结构和像LDD结构或缓变结结构那样的双漏极结构的三种MOSFET可以通过两种感光性掩膜形成处理和三种离子注入处理构成。因此与制造半导体器件的传统方法相比，本发明可以省去一种光致抗蚀剂掩膜处理和一种离子注入处理。本发明尽管简化了整个处理过程，但在像EPROM那样的存储器元件MOSFET、输入保护MOSFET和逻辑电路MOSFET中仍然能分别确保有效产生热电子、有效地阻止静电击穿以及可靠地抑制热电子的性能。

Claims (11)

1.制造包含非易失存储元件、输入保护元件和逻辑电路元件的半导体器件的方法，包括以下步骤：
(a)在第一导电型基片上形成非易失存储元件，保护元件和逻辑电路元件的栅极结构；
(b)通过用于为遮掩逻辑电路元件的第一掩膜的杂质注入形成非易失存储器元件和输入保护元件；
(c)通过用于为遮掩非易失存储器元件和输入元件的第二掩膜的杂质注入形成逻辑电路元件。
2.根据权利要求1所述的制造半导体器件的方法，其特征在于非易失存储器元件是必须有热电子产生性能的金属氧化物半导体场效应晶体管(简称MOSFET)，输入保护元件是性能能阻止静电击穿的MOSFET，逻辑电路元件必须是能阻止热电子的MOSFET。
3.根据权利要求1或2所述的制造半导体器件的方法，其特征在于所述的步骤(c)包括对非易失存储器元件和输入保护元件以自对准方法在基片中同步地注入第二导电型杂质以形成非易失存储器元件和输入保护元件的源极和漏极区域。
4.根据权利要求1或2所述的制造半导体器件的方法，其特征在于所述的步骤(b)包括以下步骤：
在基片用第一剂量的第二导电型杂质以自对准逻辑电路元件的栅极结构注入以形成逻辑电路元件的源极和漏极区域；
除了具有比第一剂量高的第二剂量的栅极结构外，在逻辑电路的源极和漏极区域的部分中注入第二导电型杂质。
5.根据权利要求1或2所述的制造半导体器件的方法，进一步包括：
(d)在非易失存储器元件、输入保护元件和逻辑电路元件的每一个边壁上形成边壁绝缘膜。
6.根据权利要求5所述的制造半导体器件的方法，其特征在于：步骤(b)包含在逻辑电路元件的源极和漏极区域部分中与边壁绝缘膜和逻辑电路元件的栅极结构对准注入第二导电型杂质。
7.根据权利要求6所述的制造半导体器件的方法，其特征在于所述的步骤(b)包括：在逻辑电路元件的源极和漏极区域几部分中以与边壁绝缘膜和逻辑电路的栅极结构对准的方式注入杂质，以形成具有轻掺杂漏极(LDD)结构的源极和栅极区域。
8.根据权利要求6所述的制造半导体器件的方法：其特征在于所述的步骤(d)包括：在逻辑电路元件的源极和漏极区域几个部分中以与逻辑电路元件的栅极结构和边壁绝缘膜对准的方式注入杂质，以形成具有过渡连接结构的源极和漏极区域。
9.根据权利要求1或2所述的制造半导体器件的方法，进一步包括下述步骤：
(e)在基片中，对非易失存储器元件，输入保护元件和具有第一剂量的逻辑电路元件的栅极结构以自对准方式注入杂质，以形成源极和漏极区域。
10.根据权利要求9所述的制造半导体器件的方法，其特征在于在步骤(e)中注入的杂质是磷，在步骤(b)和(c)中注入的杂质是砷。
11.制造包含非易失存储器元件，输入保护元件和逻辑电路元件的半导体器件的方法，包括以下步骤：
(a)在第一导电型基片上形成非易失存储器元件、输入保护元件和逻辑电路元件的栅极结构；
(b)在基片中对具有第一剂量的和与逻辑电路元件的栅极结构自对准方式注入第二导电型杂质以构成逻辑电路元件的源极和漏极区域；
(c)在基片中，与非易失存储元件和输入保护元件的栅极结构以自对准方式同步地注入第二导电型杂质，以形成非易失存储器元件和输入保护元件的源极和漏极区域；
(d)除了栅极结构外，在逻辑电路元件的源极和漏极区域的几个部分中注入具有比第一剂量高的第二剂量的第二导电型杂质。
CN95118439A 1994-09-14 1995-09-14 制造半导体器件的方法 Expired - Fee Related CN1052573C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP244921/94 1994-09-14
JP6244921A JP2600621B2 (ja) 1994-09-14 1994-09-14 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
CN1130806A true CN1130806A (zh) 1996-09-11
CN1052573C CN1052573C (zh) 2000-05-17

Family

ID=17125961

Family Applications (1)

Application Number Title Priority Date Filing Date
CN95118439A Expired - Fee Related CN1052573C (zh) 1994-09-14 1995-09-14 制造半导体器件的方法

Country Status (4)

Country Link
US (1) US5898006A (zh)
JP (1) JP2600621B2 (zh)
KR (1) KR100194008B1 (zh)
CN (1) CN1052573C (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1096710C (zh) * 1996-12-26 2002-12-18 日本电气株式会社 半导体器件
CN101258587B (zh) * 2005-07-08 2011-08-17 意法半导体股份有限公司 具有多漏结构的半导体功率器件及其相应的制造工艺

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69636738D1 (de) * 1996-12-27 2007-01-11 St Microelectronics Srl Kontaktstruktur für elektronische EPROM oder flash EPROM Halbleiterschaltungen und ihr Herstellungsverfahren
US6258671B1 (en) 1997-05-13 2001-07-10 Micron Technology, Inc. Methods of providing spacers over conductive line sidewalls, methods of forming sidewall spacers over etched line sidewalls, and methods of forming conductive lines
US6180494B1 (en) 1999-03-11 2001-01-30 Micron Technology, Inc. Integrated circuitry, methods of fabricating integrated circuitry, methods of forming local interconnects, and methods of forming conductive lines
KR100307531B1 (ko) 1999-08-09 2001-11-01 김영환 모스페트 소자와 이를 이용한 메모리셀 및 그 제조 방법
US6297102B1 (en) * 1999-10-01 2001-10-02 Taiwan Semiconductor Manufacturing Company Method of forming a surface implant region on a ROM cell using a PLDD implant
KR100344828B1 (ko) * 1999-11-25 2002-07-20 주식회사 하이닉스반도체 반도체 소자의 제조방법
KR100388221B1 (ko) * 2000-10-23 2003-06-19 주식회사 하이닉스반도체 반도체장치의 제조방법
US6773987B1 (en) * 2001-11-17 2004-08-10 Altera Corporation Method and apparatus for reducing charge loss in a nonvolatile memory cell
US7652923B2 (en) * 2007-02-02 2010-01-26 Macronix International Co., Ltd. Semiconductor device and memory and method of operating thereof
JP5276282B2 (ja) * 2007-06-08 2013-08-28 ローム株式会社 半導体装置の製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR930007195B1 (ko) * 1984-05-23 1993-07-31 가부시끼가이샤 히다찌세이사꾸쇼 반도체 장치와 그 제조 방법
JPH0797629B2 (ja) * 1986-01-22 1995-10-18 株式会社日立製作所 半導体集積回路装置
US4745083A (en) * 1986-11-19 1988-05-17 Sprague Electric Company Method of making a fast IGFET
US4775642A (en) * 1987-02-02 1988-10-04 Motorola, Inc. Modified source/drain implants in a double-poly non-volatile memory process
US4851361A (en) * 1988-02-04 1989-07-25 Atmel Corporation Fabrication process for EEPROMS with high voltage transistors
JPH0766946B2 (ja) * 1989-03-31 1995-07-19 株式会社東芝 半導体装置及びその製造方法
US5183773A (en) * 1989-04-13 1993-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device including such input protection transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1096710C (zh) * 1996-12-26 2002-12-18 日本电气株式会社 半导体器件
CN101258587B (zh) * 2005-07-08 2011-08-17 意法半导体股份有限公司 具有多漏结构的半导体功率器件及其相应的制造工艺

Also Published As

Publication number Publication date
CN1052573C (zh) 2000-05-17
KR100194008B1 (ko) 1999-06-15
JPH0888288A (ja) 1996-04-02
KR960012474A (ko) 1996-04-20
US5898006A (en) 1999-04-27
JP2600621B2 (ja) 1997-04-16

Similar Documents

Publication Publication Date Title
US5510279A (en) Method of fabricating an asymmetric lightly doped drain transistor device
US6020244A (en) Channel dopant implantation with automatic compensation for variations in critical dimension
US5804496A (en) Semiconductor device having reduced overlap capacitance and method of manufacture thereof
KR960009994B1 (ko) 반도체 메모리 장치 및 그 제조방법
US20150357465A1 (en) Threshold voltage adjustment of a transistor
US5565369A (en) Method of making retarded DDD (double diffused drain) device structure
US5635749A (en) High performance field effect transistor with lai region
US5780902A (en) Semiconductor device having LDD structure with pocket on drain side
CN1183642A (zh) 制造半导体器件的方法
KR100206649B1 (ko) 반도체장치와 그의 제조방법
US20020003255A1 (en) Semiconductor device and method for fabricating the same
CN1088914C (zh) 制造金属氧化物半导体场效应晶体管的方法
CN1052573C (zh) 制造半导体器件的方法
US5538909A (en) Method of making a shallow trench large-angle-tilt implanted drain device
US20020025641A1 (en) Method for fabricating a MOSFET and a MOSFET
US20030111689A1 (en) Process for the selective formation of salicide on active areas of MOS devices
US6509237B2 (en) Flash memory cell fabrication sequence
KR20000028675A (ko) 반도체 구조 형성 방법
KR940010543B1 (ko) 모스 트랜지스터의 제조방법
CN1122315C (zh) 金属氧化物半导体场效应晶体管制造方法
KR100192169B1 (ko) P+소오드/드레인 접합 형성방법
KR20010061414A (ko) 플래쉬 메모리 소자의 제조방법
KR100259347B1 (ko) 모스트랜지스터의 구조 및 그 제조방법
KR100233400B1 (ko) 소오스/드레인 분배 주입법
JP4228416B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: NEC ELECTRONICS TAIWAN LTD.

Free format text: FORMER OWNER: NIPPON ELECTRIC CO., LTD.

Effective date: 20030404

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20030404

Address after: Kawasaki, Kanagawa, Japan

Patentee after: NEC Corp.

Address before: Tokyo, Japan

Patentee before: NEC Corp.

REG Reference to a national code

Ref country code: HK

Ref legal event code: GR

Ref document number: 1021449

Country of ref document: HK

C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee