CN113078149B - Semiconductor packaging structure, method, device and electronic product - Google Patents

Semiconductor packaging structure, method, device and electronic product Download PDF

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Publication number
CN113078149B
CN113078149B CN202110272185.1A CN202110272185A CN113078149B CN 113078149 B CN113078149 B CN 113078149B CN 202110272185 A CN202110272185 A CN 202110272185A CN 113078149 B CN113078149 B CN 113078149B
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Prior art keywords
packaged
substrate
bonding pads
semiconductor
groove
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CN202110272185.1A
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CN113078149A (en
Inventor
李维平
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Shanghai Yibu Semiconductor Co ltd
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Shanghai Yibu Semiconductor Co ltd
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Priority to CN202110272185.1A priority Critical patent/CN113078149B/en
Publication of CN113078149A publication Critical patent/CN113078149A/en
Priority to TW111105827A priority patent/TWI787085B/en
Priority to KR1020220030531A priority patent/KR102625995B1/en
Priority to US17/693,357 priority patent/US20220293504A1/en
Priority to US17/693,358 priority patent/US20220293547A1/en
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Publication of CN113078149B publication Critical patent/CN113078149B/en
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  • General Physics & Mathematics (AREA)
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  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The application provides a semiconductor packaging structure, a semiconductor packaging method, a semiconductor packaging device and an electronic product. In the semiconductor packaging structure, packaged elements are fixed in grooves on a substrate in a one-to-one correspondence manner; the active surfaces of the packaged elements are opposite to the substrate, the packaged elements are separated from the grooves where the packaged elements are located by insulating materials, each packaged element is provided with a first bonding pad positioned on the active surface of the packaged element, and the surfaces of all the first bonding pads opposite to the substrate are flush; the rewiring layer is positioned on one side of the packaged element, which is opposite to the substrate, a plurality of second bonding pads are formed on a first surface of the rewiring layer, a plurality of third bonding pads are formed on a second surface of the rewiring layer, which is opposite to the first surface, and the second bonding pads are in one-to-one corresponding electric contact with the first bonding pads; the passivation layer is positioned on one side of the rewiring layer, which is away from the substrate; the substrate is formed of a semiconductor material or an insulating material, and has the same or similar coefficient of thermal expansion as the semiconductor material in the packaged element. The packaging structure has the advantages of small warping degree, good heat dissipation performance and high reliability.

Description

Semiconductor packaging structure, method, device and electronic product
Technical Field
The application belongs to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor packaging structure, a semiconductor packaging method, a semiconductor device and an electronic product.
Background
In the conventional semiconductor package manufacturing process, a packaged element (for example, a die, also referred to as die) needs to be packaged, and then a semiconductor device is obtained. The common process is to fix the packaged element on a substrate (submount), a frame (leadframe) or an interposer (interposer), and then use a series of processes such as interconnection and plastic packaging to implement the packaging of the packaged element, so as to obtain the packaged semiconductor device.
Disclosure of Invention
The application aims to provide a semiconductor packaging structure, a method, a device and an electronic product.
In order to solve the technical problems, the application adopts the following technical scheme: a semiconductor package structure, comprising: the packaging structure comprises a substrate, at least one packaged element, a rewiring layer and a passivation layer, wherein at least one groove is formed in the substrate, and the packaged elements are correspondingly fixed in the grooves one by one;
the active surfaces of the packaged elements are opposite to the substrate, the packaged elements are separated from the grooves where the packaged elements are located by insulating materials, each packaged element is provided with a first bonding pad positioned on the active surface of the packaged element, and the surfaces of all the first bonding pads opposite to the substrate are flush;
The rewiring layer is positioned on one side of the packaged element, which is opposite to the substrate, a plurality of second bonding pads are formed on a first surface of the rewiring layer, a plurality of third bonding pads are formed on a second surface of the rewiring layer, which is opposite to the first surface, the second bonding pads are in one-to-one corresponding electrical contact with the first bonding pads, and the rewiring layer is also provided with wires for electrically connecting the second bonding pads and the third bonding pads;
the passivation layer is positioned on one side of the rewiring layer, which is away from the substrate;
wherein the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficient of the substrate is the same as or similar to that of the semiconductor material in the packaged element.
In order to solve the technical problems, the application adopts the following technical scheme: a semiconductor packaging method, comprising:
forming at least one recess in a substrate;
fixing at least one packaged element in the grooves in a one-to-one correspondence manner, wherein the active surfaces of the packaged elements face away from the substrate, the packaged elements are separated from the grooves in which the packaged elements are positioned by insulating materials, each packaged element is provided with a first bonding pad positioned on the active surface of the packaged element, and the surfaces of all the first bonding pads facing away from the substrate are flush;
Forming a planar surface exposing the first bonding pad;
forming a rerouting layer, wherein a plurality of second bonding pads are formed on a first surface of the rerouting layer, a plurality of third bonding pads are formed on a second surface of the rerouting layer opposite to the first surface, the second bonding pads are in one-to-one corresponding electric contact with the first bonding pads, and the rerouting layer is also provided with wires for electrically connecting the second bonding pads and the third bonding pads;
forming a passivation layer;
wherein the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficient of the substrate is the same as or similar to that of the semiconductor material in the packaged element.
In order to solve the technical problems, the application adopts the following technical scheme: a semiconductor package structure, comprising:
the semiconductor packaging structure comprises a substrate, at least one first packaged element, at least one second packaged element, a rewiring layer and a passivation layer, wherein at least one first groove and at least one second groove are formed in the substrate, the first packaged elements are fixed in the first grooves in a one-to-one correspondence manner, the second packaged elements are fixed in the second grooves in a one-to-one correspondence manner, the first packaged elements are in a bare chip state, and the second packaged elements are in a packaging state and have exposed second electrode structures;
The active surfaces of the first packaged elements are opposite to the substrate, the first packaged elements are separated from the first grooves where the first packaged elements are located by insulating materials, the second packaged elements are separated from the second grooves where the second packaged elements are located by insulating materials, each first packaged element is provided with a first bonding pad positioned on the active surface of the first packaged element, and all the first bonding pads are flush with the surface opposite to the substrate and all the second electrode structures are flush with the surface opposite to the substrate;
the rewiring layer is positioned on one side of the packaged element, which is opposite to the substrate, a plurality of second bonding pads are formed on a first surface of the rewiring layer, a plurality of third bonding pads are formed on a second surface of the rewiring layer, which is opposite to the first surface, the first bonding pads are in one-to-one corresponding electric contact with part of the second bonding pads, the second electrode structures are in one-to-one corresponding electric contact with the rest of the second bonding pads, and the rewiring layer is also provided with wires for electrically connecting the second bonding pads with the third bonding pads and wires for electrically connecting the second bonding pads with the second electrode structures;
the passivation layer is positioned on one side of the rewiring layer, which is away from the substrate;
wherein the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficient of the substrate is the same as or similar to that of the semiconductor material in the packaged element.
In order to solve the technical problems, the application adopts the following technical scheme: a semiconductor packaging method, comprising:
forming at least one first groove and at least one second groove on a substrate;
fixing at least one first packaged element in the first groove in a one-to-one correspondence manner, fixing at least one second packaged element in the second groove in a one-to-one correspondence manner, wherein the first packaged element is in a bare chip state, the second packaged element is in a packaged state and is provided with an exposed second electrode structure, the active surface of the first packaged element faces away from the substrate, the first packaged element is separated from the first groove where the first packaged element is located by an insulating material, the second packaged element is separated from the second groove where the second packaged element is located by an insulating material, each first packaged element is provided with a first bonding pad positioned on the active surface of the second packaged element, and the surfaces of all the first bonding pads and all the second electrode structures facing away from the substrate are flush;
forming a flat surface exposing the first bonding pad and the second electrode structure;
forming a rerouting layer, wherein a plurality of second bonding pads are formed on a first surface of the rerouting layer, a plurality of third bonding pads are formed on a second surface of the rerouting layer opposite to the first surface, the first bonding pads are in one-to-one corresponding electric contact with part of the second bonding pads, the second electrode structures are in one-to-one corresponding electric contact with the rest of the second bonding pads, and the rerouting layer is provided with wires electrically connecting the second bonding pads and the third bonding pads and wires electrically connecting the second bonding pads and the second electrode structures;
Forming a passivation layer;
wherein the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficient of the substrate is the same as or similar to that of the semiconductor material in the packaged element.
In order to solve the technical problems, the application adopts the following technical scheme: a semiconductor device, comprising: the semiconductor packaging structure.
In order to solve the technical problems, the application adopts the following technical scheme: an electronic product, comprising: the aforementioned semiconductor device.
Compared with the prior art, the application has the beneficial effects that: since the thermal expansion coefficients of the semiconductor material in the packaged element and the substrate are equal or close (for example, the semiconductor material and the substrate are formed by the same semiconductor material), after packaging is completed, the warping degree of the semiconductor packaging structure generated along with temperature change is relatively smaller, which is beneficial to improving the yield of the semiconductor device and the reliability in electrical and mechanical aspects. Meanwhile, in some embodiments, the semiconductor substrate has better heat dissipation than the molding material of the conventional package form.
Drawings
Fig. 1a and 1b are schematic structural views of two semiconductor package structures according to an embodiment of the present application.
Fig. 2 is a flow chart of a semiconductor packaging method according to an embodiment of the application.
Fig. 3a to 3g are schematic views of the semiconductor package structure shown in fig. 1a in different stages of packaging.
Fig. 4a to 4g are schematic views of the semiconductor package structure shown in fig. 1b in different stages of packaging.
Fig. 5a and 5b are schematic structural views of two semiconductor package structures according to an embodiment of the present application.
Fig. 6 is a flow chart of a semiconductor packaging method according to an embodiment of the present application.
Fig. 7a to 7f are schematic views of the semiconductor package structure shown in fig. 5a in different stages of packaging.
Fig. 8a to 8f are schematic views of the semiconductor package structure shown in fig. 5b in different stages of packaging.
1, a substrate; 10. a groove; 111. 112, an insulating material; 21. 22, encapsulated components; 211. 221, a first bonding pad; 3. a rewiring layer; 31. a second bonding pad; 32. a third bonding pad; 33. routing; 4. a passivation layer; 5. a first electrode structure; 21a, a second encapsulated component; 22a, 23a, a first encapsulated component; 211a, a second electrode structure; 221a, 231a, first pads.
Detailed Description
In the present disclosure, it should be understood that terms such as "comprises" or "comprising," etc., are intended to indicate the presence of the disclosed features, numbers, steps, acts, components, portions, or combinations thereof in this specification, but do not preclude the presence or addition of one or more other features, numbers, steps, acts, components, portions, or combinations thereof.
In addition, it should be noted that, without conflict, the embodiments of the present application and the features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
The application will be further described with reference to examples of embodiments shown in the drawings.
An embodiment of the present application provides a semiconductor package structure including: the packaging structure comprises a substrate, at least one packaged element, a rewiring layer and a passivation layer, wherein the substrate is provided with at least one groove, and the packaged elements are fixed in the grooves in a one-to-one correspondence manner; the active surfaces of the packaged elements are opposite to the substrate, the packaged elements are separated from the grooves where the packaged elements are located by insulating materials, each packaged element is provided with a first bonding pad positioned on the active surface of the packaged element, and the surfaces of all the first bonding pads opposite to the substrate are flush; the rewiring layer is positioned on one side of the packaged element, which is opposite to the substrate, a plurality of second bonding pads are formed on a first surface of the rewiring layer, a plurality of third bonding pads are formed on a second surface of the rewiring layer, which is opposite to the first surface, and the second bonding pads are in one-to-one corresponding electric contact with the first bonding pads; the passivation layer is positioned on one side of the rewiring layer, which is opposite to the substrate, and the rewiring layer is also provided with a wiring for electrically connecting the second bonding pad and the third bonding pad; wherein the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficient of the substrate is the same as or similar to that of the semiconductor material in the packaged element.
Since the thermal expansion coefficients of the semiconductor material in the packaged element and the substrate are equal or close (for example, the semiconductor material and the substrate are formed by the same semiconductor material), after packaging is completed, the warping degree of the semiconductor packaging structure generated along with temperature change is relatively smaller, which is beneficial to improving the yield of the semiconductor device and the reliability in electrical and mechanical aspects. Meanwhile, in some embodiments, the semiconductor substrate has better heat dissipation than the molding material of the conventional package form.
For example, the semiconductor material within the substrate is the same as the semiconductor material within the packaged component.
In these embodiments, the packaged component is placed in a recess formed in the substrate, and the packaged component is covered by the redistribution layer. The base material in the substrate and the packaged component are the same semiconductor material.
The term "same semiconductor material" as used herein refers to materials that are identical in chemical composition, e.g., are all formed of silicon materials, or are all formed of gallium arsenide materials. However, the purity, density, crystalline state, and the like of these semiconductor materials are not limited to be completely uniform.
For another example, the semiconductor material in the packaged element is silicon or gallium arsenide, and the material of the substrate is engineering heat resistant glass. The coefficients of thermal expansion of the two are in the same order of magnitude.
In the application, the thermal expansion coefficients of the two materials are similar, namely the absolute value of the ratio of the difference between the two materials and the smaller absolute value of the two materials is smaller than 9.
In some embodiments, the packaged component is in the form of a die.
In some embodiments, a single semiconductor package includes one packaged component. The effect of the rewiring layer is to simply bring out the first pads on the packaged component.
In some embodiments, a single semiconductor package includes multiple packaged components. At this time, the wiring in the rewiring layer may function as signal interconnection between the first pads of the plurality of packaged elements.
In some embodiments, the number of packaged components is multiple and the thickness is equal, and the depth of each groove is equal.
Referring to fig. 1a and 3a, the thickness of the encapsulated component 21 and the encapsulated component 22 are equal, and the depth of the groove 10 is equal.
Of course, the packaged element 21 and the packaged element 22 may be the same type of packaged element, or may be different types of packaged elements. Since the thickness of the packaged element 21 and the packaged element 22 are equal, each groove 10 may be formed by the same grooving (e.g., etching) process.
If the initial thickness of the packaged components is not uniform, the thickness of the packaged components can be equalized by a thinning process.
Of course, even if the initial thicknesses of these packaged elements 21, 22 are equal, their thicknesses can be reduced and made equal by a thinning process. In this way, the groove depth in which the groove 10 is opened in the substrate 1 can be reduced.
In some embodiments, the number of packaged components is plural, and the thicknesses of at least two packaged components are not equal, wherein the depths of at least two grooves are different so that the upper surfaces of the first pads of the packaged components are flush.
Referring to fig. 1b and 4a, the thickness of the encapsulated component 21 and the encapsulated component 22 are not equal, and the depth of the groove 10 is also not equal. The encapsulated component 21 is thicker and accordingly the depth of the recess 10 in which it is located is deeper.
The grooves 10 of different depths may be formed by controlling a grooving process such as step etching or secondary etching.
In some embodiments, the semiconductor package structure may be used as a stand-alone product after the passivation layer covers the third pad over the redistribution layer.
In some embodiments, referring to fig. 1a and 1b, the semiconductor package structure further includes a first electrode structure 5 located on a side of the passivation layer 4 facing away from the substrate 1, and the passivation layer 4 has vias formed in a region opposite to the third pads 32, where the first electrode structure 5 is in one-to-one correspondence with the third pads 32, and the first electrode structure 5 is electrically connected to the corresponding third pad 32 through the vias.
Specifically, the first electrode structure 5 includes, for example, an Under Bump Metal (UBM) covering the third pad, and a solder ball located above the under bump metal. Of course, the electrode structure may be a Pad (Pad) formed over the third Pad.
In some embodiments, the encapsulated component is separated from the bottom of the recess by an insulating adhesive layer. The encapsulated component is fixed by the insulating adhesive layer, and insulation between the encapsulated component and the bottom of the groove is realized.
In some embodiments, the encapsulated component is separated from the sides of the recess by a cured resin material (e.g., epoxy) or an inorganic insulating material. I.e. the gap between the encapsulated component and the recess is filled with and cured with a resin material or an inorganic insulating material, such as silicon dioxide, is deposited into the gap.
In some embodiments, the conductors in the rewiring layer are separated from one another by a polymer. The polymer in the redistribution layer is, for example, polyimide (PI) or Polymethylene Benzobisoxazole (PBO). Also for example, the conductors in the rewiring layer are separated from one another by a molding compound (molding compound).
The re-wiring layer includes at least one layer of metal trace, and includes vias connecting different layers of metal traces (if there are multiple layers of metal traces), vias connecting the metal trace to the second pad, and vias connecting the metal trace to the third pad. The routing in the rewiring layer can realize interconnection of the second bonding pad and the third bonding pad, interconnection of the second bonding pad and interconnection of the third bonding pad and the third bonding pad.
Referring to fig. 2, an embodiment of the present application also provides a semiconductor packaging method. The packaging method can manufacture the semiconductor packaging structure provided by the embodiment. The manufacturing method comprises the following steps.
Step 1000, forming at least one groove on a substrate;
step 1001, fixing at least one packaged element in a groove in a one-to-one correspondence manner, wherein the active surfaces of the packaged elements face away from the substrate, the packaged elements are separated from the groove where the packaged elements are located by an insulating material, each packaged element is provided with a first bonding pad positioned on the active surface of the packaged element, and the surfaces of all the first bonding pads face away from the substrate are level;
step 1002, forming a flat surface exposing the first bonding pad;
step 1003, forming a rewiring layer, wherein a plurality of second bonding pads are formed on a first surface of the rewiring layer, a plurality of third bonding pads are formed on a second surface of the rewiring layer opposite to the first surface, the second bonding pads are in one-to-one corresponding electric contact with the first bonding pads, and the rewiring layer is also provided with wires for electrically connecting the second bonding pads and the third bonding pads;
step 1004, forming a passivation layer;
wherein the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficient of the substrate is the same as or similar to that of the semiconductor material in the packaged element.
For example, the semiconductor material within the substrate is the same as the semiconductor material within the packaged component.
For another example, the semiconductor material in the packaged element is silicon or gallium arsenide, and the material of the substrate is engineering heat resistant glass.
Because the packaged element and the substrate are made of the same semiconductor material, the thermal expansion coefficients of the packaged element and the substrate are consistent, and after packaging is completed, the warping degree of the semiconductor device along with temperature change is relatively smaller, thereby being beneficial to improving the yield of the semiconductor device and the reliability in electrical and mechanical aspects.
In contrast, the heat conductivity of silicon and engineering heat-resistant glass is larger than that of the traditional plastic packaging material, and the heat dissipation of the semiconductor packaging structure is higher.
In some embodiments, the packaging method further comprises:
step 1005, forming at least one via hole on the passivation layer, wherein the via hole corresponds to the third bonding pad one by one, and the via hole exposes the corresponding third bonding pad;
step 1006, an electrode structure is formed on the third pad in electrical contact therewith.
In some embodiments, the number of the packaged components is a plurality, the depth of the grooves is the same, and the packaging method further comprises: at least part of the encapsulated components are thinned so that the thickness of each encapsulated component is equal.
In some embodiments, the number of packaged components is plural, and the thicknesses of at least two packaged components are not equal, and when grooves are formed on the substrate, the depths of at least two grooves are not equal, so that the upper surfaces of the first bonding pads of the packaged components are flush.
In some embodiments, fixing at least one encapsulated component in the recess in a one-to-one correspondence includes:
an insulating adhesive layer is formed at the bottom of the groove;
adhering the packaged element on the insulating adhesive, wherein a gap is reserved between the packaged element and the side surface of the groove;
and filling insulating materials between the packaged element and the side surface of the corresponding groove.
In some embodiments, filling insulating material between the packaged component and the corresponding recess sides comprises:
and filling and curing the resin material between the encapsulated component and the corresponding groove side surface, or depositing inorganic oxide insulating material into the gap between the encapsulated component and the corresponding groove side surface.
In some embodiments, forming a planar surface exposing the first pad includes: the insulating material and the substrate material above the first pad are removed by a grinding process, followed by a surface treatment.
In some embodiments, the area of the substrate is larger, which may actually form a large number of grooves. The manufacturing further includes: obtaining a plurality of semiconductor packaging structures through a cutting process, wherein each semiconductor packaging structure at least comprises: the semiconductor device comprises a packaged element, a groove in which the packaged element is positioned, a rewiring layer electrically connected with the packaged element, and a passivation layer above the rewiring layer.
In some embodiments, the packaged component is in the form of a die.
In some embodiments, the insulating material in the redistribution layer comprises a polymer or a molding compound.
In some embodiments, referring to fig. 3a to 3g and fig. 1a, a specific implementation procedure of a packaging method of a semiconductor device is as follows.
First, referring to fig. 3a, a plurality of grooves 10 are formed on a substrate 1 using an etching process, and the depths of the plurality of grooves 10 are equal.
In the second step, referring to fig. 3b, an insulating adhesive layer 111 is formed at the bottom of the groove 10.
Third, referring to fig. 3c, the packaged element 21 and the packaged element 22 are respectively placed in one groove 10 and adhered on the insulating adhesive 111, wherein the first bonding pad 211 of the packaged element 21 and the first bonding pad 221 of the packaged element 22 face upwards, and the thicknesses of the packaged element 21 and the packaged element 22 are equal. The encapsulated elements 21 and 22 are both spaced from the side walls of the recess 10.
Fourth, referring to fig. 3d, the groove 10 is filled with and cured with the insulating material 112. For example, liquid epoxy resin is dropped into the gap between the recess 10 and the encapsulated elements 21, 22, and the epoxy resin is cured by heating. Or an inorganic insulating material (for example, silicon dioxide) is deposited to the gap between the recess 10 and the encapsulated components 21, 22.
Fifth, referring to fig. 3e, the insulating material 112 above the first pads 211, 221 and the substrate material above the first pads 211, 221 are ground away, and a surface treatment process such as chemical cleaning, polishing, etc. is performed to obtain a flat surface exposing the first pads 211, 221.
Sixth, referring to fig. 3f, a re-wiring layer 3 is formed on this planar surface, the second pads 31 of the re-wiring layer 3 being in electrical contact with the first pads 211, 221, respectively, and the third pads 32 of the re-wiring layer 3 being interconnected with the second pads 31.
Specifically, for example, a polyimide film is formed, and then a patterning process (e.g., photoresist coating, exposure, development, etching) is performed, so that a via hole exposing the first pads 211, 221 is formed in the polyimide film; then a layer of metal film is deposited, wiring 33 connected to each first bonding pad 211, 221 is formed through a patterning process, and metal materials in the lower layer via holes form a second bonding pad 31; then forming a polyimide film and a wiring 33 again; a polyimide film is then formed, a partial region of the lower trace 33 is then exposed through a patterning process, a metal film is finally deposited, and a third pad 32 connected to the lower trace 33 is formed through a patterning process.
The redistribution layer may include a plurality of traces 33.
Of course, the patterning process may be first used to form the pattern of the second pad 31, then the polyimide film may be formed, then the via hole exposing the second pad 31 may be formed in the polyimide film, and then the pattern of the first layer trace 33 may be formed.
The rerouting layer can be prepared by a person skilled in the art according to the prior art.
Seventh, referring to fig. 3g, a passivation layer 4 is formed on the re-wiring layer 3. The material of the passivation layer 4 may be, for example, silicon nitride or polyimide (polyimide). The passivation layer 4 serves to protect the elements below it.
Eighth, referring to fig. 1a, a via hole is etched on the passivation layer 4, thereby exposing each of the third pads 32, and the first electrode structure 5 is formed on the third pads 32. The first electrode structure 5 includes, for example, an Under Bump Metal (UBM) over the third Pad 32 and a solder ball over the under bump metal, and of course, the first electrode structure 5 may be in the form of a Pad (Pad).
In some embodiments, referring to fig. 4a to 4g and fig. 1b, a specific implementation procedure of the packaging method of the semiconductor device is as follows.
First, referring to fig. 4a, a plurality of grooves 10 are formed on a substrate 1 by controlling a grooving process (e.g., step etching or secondary etching), and the depths of the plurality of grooves 10 are not uniform.
In the second step, referring to fig. 4b, an insulating adhesive layer 111 is formed at the bottom of the groove 10.
Third, referring to fig. 4c, the packaged element 21 and the packaged element 22 are respectively placed in one groove 10 and adhered on the insulating adhesive 111, wherein the first bonding pad 211 of the packaged element 21 and the first bonding pad 221 of the packaged element 22 face upwards and are flush, and the thicknesses of the packaged element 21 and the packaged element 22 are not equal.
Fourth, referring to fig. 4d, the groove 10 is filled with and cured with the insulating material 112. For example, liquid epoxy resin is dropped into the gap between the recess 10 and the encapsulated elements 21, 22, and the epoxy resin is cured by heating.
Fifth, referring to fig. 4e, the insulating material and the substrate material above the first pads 211, 221 are removed by grinding, and a surface treatment process such as chemical cleaning, polishing, etc. is performed to obtain a flat surface exposing the first pads 211, 221.
Sixth, referring to fig. 4f, a re-wiring layer 3 is formed on this planar surface, the second pads 31 of the re-wiring layer 3 being in electrical contact with the first pads 211, 221, respectively, and the third pads 32 of the re-wiring layer 3 being interconnected with the second pads 31.
Specifically, for example, a polyimide film is formed, and then a patterning process (e.g., photoresist coating, exposure, development, etching) is performed, so that a via hole exposing the first pads 211, 221 is formed in the polyimide film; then a layer of metal film is deposited, wiring 33 connected to each first bonding pad 211, 221 is formed through a patterning process, and metal materials in the lower layer via holes form a second bonding pad 31; a polyimide film is then formed, a partial region of the lower trace 33 is then exposed through a patterning process, a metal film is finally deposited, and a third pad 32 connected to the lower trace 33 is formed through a patterning process.
The redistribution layer may include a plurality of traces 33.
Seventh, referring to fig. 4g, a passivation layer 4 is formed on the re-wiring layer 3. The material of the passivation layer 4 may be, for example, silicon nitride or polyimide (polyimide). The passivation layer 4 serves to protect the elements below it.
Eighth, referring to fig. 1b, a via hole is etched on the passivation layer 4, thereby exposing each of the third pads 32, and the first electrode structure 5 is formed on the third pads 32. The first electrode structure 5 may comprise, for example, an Under Bump Metal (UBM) over the third Pad 32 and a solder ball over the under bump metal, and the first electrode structure 5 may also be a Pad (bonding Pad).
An embodiment of the present application provides a semiconductor package structure including: the semiconductor packaging structure comprises a substrate, at least one first packaged element, at least one second packaged element, a rewiring layer and a passivation layer, wherein the substrate is provided with at least one first groove and at least one second groove; the active surfaces of the first packaged elements are opposite to the substrate, the first packaged elements are separated from the first grooves where the first packaged elements are located by insulating materials, the second packaged elements are separated from the second grooves where the second packaged elements are located by insulating materials, each first packaged element is provided with a first bonding pad positioned on the active surface of the first packaged element, and all the first bonding pads are flush with the surface opposite to the substrate and all the second electrode structures are flush with the surface opposite to the substrate; the rewiring layer is positioned on one side of the packaged element, which is opposite to the substrate, a plurality of second bonding pads are formed on a first surface of the rewiring layer, a plurality of third bonding pads are formed on a second surface of the rewiring layer, which is opposite to the first surface, the first bonding pads are in one-to-one corresponding electric contact with part of the second bonding pads, the second electrode structure is in one-to-one corresponding electric contact with the rest of the second bonding pads, and the rewiring layer is also provided with wires for electrically connecting the second bonding pads and the third bonding pads and wires for electrically connecting the second bonding pads and the second electrode structure; the passivation layer is positioned on one side of the rewiring layer, which is away from the substrate; wherein the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficient of the substrate is the same as or similar to that of the semiconductor material in the packaged element.
For example, the semiconductor material within the substrate is the same as the semiconductor material within the packaged component.
For another example, the semiconductor material in the packaged element is silicon or gallium arsenide, and the material of the substrate is engineering heat resistant glass.
In these embodiments, a first packaged component is placed in a first recess formed in a substrate and a second packaged component is placed in a second recess formed in the substrate, the first packaged component and the second packaged component being covered by a rewiring layer. The base material in the substrate and the first encapsulated component are the same semiconductor material.
The first packaged element is in a bare chip state, and the second packaged element is an element which is packaged completely. The semiconductor packaging structure of the application realizes the primary packaging of the first packaged element and the secondary packaging of the second packaged element, and realizes the interconnection between the first packaged element and the second packaged element.
The package form of the second packaged element is, for example, a chip package, a ceramic package, or the like. The second encapsulated component may be, for example, a chip resistor, a chip multilayer ceramic capacitor, or the like, or may be another component already in an encapsulated state.
The shape and the position of each second electrode structure of the same second packaged element are not limited, so long as the second electrode structures have a flush surface, and thus the second electrode structures can be coplanar with the first bonding pad of the first packaged element.
The term "same semiconductor material" as used herein refers to materials that are identical in chemical composition, e.g., are all formed of silicon materials, or are all formed of gallium arsenide materials. However, the purity, density, crystalline state, and the like of these semiconductor materials are not limited to be completely uniform.
Because the thermal expansion coefficients of the first packaged element and the substrate are the same or similar, after packaging is completed, the warping degree of the semiconductor device along with temperature change is relatively smaller, and the yield and the electrical and mechanical reliability of the semiconductor packaging structure are improved. Meanwhile, in some embodiments, the semiconductor substrate has better heat dissipation than the molding material of the conventional package form.
Further, the semiconductor packaging structure realizes secondary packaging of the second packaged element and interconnection between the first packaged element and the second packaged element, so that the semiconductor packaging result has higher integration level.
In some embodiments, the number of the first packaged components is a plurality and the thicknesses are equal, and the depths of the first grooves are equal.
Referring to fig. 5a and 7a, the first encapsulated components 22a and 23a have equal thickness and are located in the first grooves H1 having equal depth.
Of course, the first encapsulated component 22a and the encapsulated component 23a may be the same type of encapsulated component, or may be different types of encapsulated components. Since the thicknesses of the second encapsulated component 21a and the first encapsulated component 22a are equal, each first recess 10 may be formed by the same grooving (e.g., etching) process.
If the initial thickness of the first encapsulated components is not uniform, they can be made equal in thickness by a thinning process.
Of course, even if the initial thicknesses of these first encapsulated elements 22a, 23a are equal, their thicknesses can be reduced and equalized by a thinning process. In this way, the groove depth in which the groove 10 is opened in the substrate 1 can be reduced.
Since the second encapsulated component is in an encapsulated state, its outer dimensions are relatively fixed. The depth of the second recess is relatively fixed and the adjustable margin is relatively small. It is preferable that a relatively thin second encapsulated component is added to the semiconductor package.
Should be ensured
In some embodiments, the number of the first packaged elements is a plurality, and the thicknesses of at least two first packaged elements are not equal, wherein the depths of at least two first grooves are different, so that the upper surfaces of the first bonding pads of the first packaged elements are flush.
Referring to fig. 5b and 8a, the thicknesses of the first encapsulated component 22a and the first encapsulated component 23a are not equal, and the depths of the first grooves H1 where they are located are also not equal. The first encapsulated component 22a is thicker and, correspondingly, the first recess H1 is deeper.
The first grooves H1 and the second grooves H2 of different depths may be formed by controlling a grooving process such as step etching or secondary etching.
In some embodiments, the semiconductor package structure may be used as a stand-alone product after the passivation layer covers the third pad over the redistribution layer.
In some embodiments, referring to fig. 5a and 5b, the semiconductor package structure further includes a first electrode structure 5 located on a side of the passivation layer 4 facing away from the substrate 1, and the passivation layer 4 has vias formed in a region opposite to the third pads 32, where the first electrode structure 5 is in one-to-one correspondence with the third pads 32, and the first electrode structure 5 is electrically connected to the corresponding third pad 32 through the vias.
Specifically, the first electrode structure 5 includes, for example, an Under Bump Metal (UBM) covering the third pad, and a solder ball located above the under bump metal. Of course, the first electrode structure may be a Pad (Pad) formed over the third Pad.
In some embodiments, the first encapsulated component is separated from the bottom of the first groove by an insulating adhesive layer, and the second encapsulated component is separated from the bottom of the second groove by an insulating adhesive layer. Namely, the first encapsulated component and the second encapsulated component are fixed by the insulating adhesive layer, insulation between the first encapsulated component and the bottom of the first groove is realized, and insulation between the second encapsulated component and the bottom of the second groove is realized.
In some embodiments, the first encapsulated component is separated from the side of the first recess by a cured resin material (e.g., epoxy) or an inorganic insulating material; the second encapsulated component is separated from the side of the second recess by a cured resin material (e.g., epoxy) or an inorganic insulating material. I.e. the gap between each encapsulated component and the recess in which it is located is filled with and cured with a resin material or an inorganic insulating material, such as silicon dioxide, is deposited into the gap.
In some embodiments, the conductors in the rewiring layer are separated from one another by a polymer. The polymer in the redistribution layer is, for example, polyimide (PI) or Polymethylene Benzobisoxazole (PBO). For example, the conductors in the redistribution layer are separated from one another by a molding compound (molding compound).
The re-wiring layer includes at least one layer of metal trace, and includes vias connecting different layers of metal traces (if there are multiple layers of metal traces), vias connecting the metal trace to the second pad, and vias connecting the metal trace to the third pad. The routing in the rewiring layer may realize interconnection of the second pad and the third pad, and interconnection of the second pad and the second electrode structure, and of course, interconnection of the second pad and the second pad may also be realized.
Referring to fig. 6, an embodiment of the present application also provides a semiconductor packaging method. The packaging method can manufacture the semiconductor packaging structure provided by the embodiment. The manufacturing method comprises the following steps.
Step 1000, forming at least one first groove and at least one second groove on a substrate;
step 1001, fixing at least one first packaged element in a first groove in a one-to-one correspondence manner, fixing at least one second packaged element in a second groove in a one-to-one correspondence manner, wherein the first packaged element is in a bare chip state, the second packaged element is in a packaged state and is provided with an exposed second electrode structure, the active surface of the first packaged element faces away from the substrate, the first packaged element is separated from the first groove where the first packaged element is located by an insulating material, the second packaged element is separated from the second groove where the second packaged element is located by an insulating material, each first packaged element is provided with a first bonding pad positioned on the active surface of the first packaged element, and the surfaces of all the first bonding pads and all the second electrode structures facing away from the substrate are flush;
Step 1002, forming a flat surface exposing the first bonding pad and the second electrode structure;
step 1003, forming a rewiring layer, wherein a plurality of second bonding pads are formed on a first surface of the rewiring layer, a plurality of third bonding pads are formed on a second surface of the rewiring layer, which is opposite to the first surface, the first bonding pads are in one-to-one corresponding electrical contact with part of the second bonding pads, the second electrode structures are in one-to-one corresponding electrical contact with the rest of the second bonding pads, and the rewiring layer is provided with wires electrically connected with the second bonding pads and the third bonding pads and wires electrically connected with the second bonding pads and the second electrode structures;
step 1004, forming a passivation layer;
wherein the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficient of the substrate is the same as or similar to that of the semiconductor material in the packaged element.
For example, the semiconductor material within the substrate is the same as the semiconductor material within the packaged component.
For another example, the semiconductor material in the packaged element is silicon or gallium arsenide, and the material of the substrate is engineering heat resistant glass.
Because the thermal expansion coefficients of the semiconductor material in the first packaged element and the thermal expansion coefficient of the substrate are the same or similar, after packaging is completed, the warping degree of the semiconductor packaging structure generated along with temperature change is relatively smaller, and the yield and the electrical and mechanical reliability of the semiconductor packaging structure are improved.
In contrast, the heat conductivity of the semiconductor material and the engineering heat-resistant glass is higher than that of the traditional plastic packaging material, and the heat dissipation of the semiconductor packaging structure is better.
In some embodiments, the packaging method further comprises:
step 1005, forming at least one via hole on the passivation layer, wherein the via hole corresponds to the third bonding pad one by one, and the via hole exposes the corresponding third bonding pad;
step 1006, forming a first electrode structure on the third pad in electrical contact therewith.
In some embodiments, the number of the first packaged elements is a plurality, the first grooves are located at the same depth, and the packaging method further includes: at least part of the first encapsulated components are thinned so that the thickness of each first encapsulated component is equal.
In some embodiments, the thicknesses of at least two packaged components of the first packaged component and the second packaged component are unequal, and when the first groove and the second groove are formed on the substrate, the depths of the at least two grooves are unequal, so that the upper surface of the first bonding pad of each first packaged component and the upper surface of each second electrode structure are flush.
In some embodiments, fixing at least one first encapsulated component in the first groove in a one-to-one correspondence includes:
An insulating adhesive layer is formed at the bottom of the first groove;
adhering a first encapsulated element on the insulating adhesive, wherein a gap is reserved between the first encapsulated element and the side surface of the first groove;
and filling insulating materials between the first packaged element and the side surface of the corresponding first groove.
In some embodiments, filling the insulating material between the first encapsulated component and the corresponding first groove side surface comprises:
and filling and curing a resin material between the first encapsulated component and the corresponding first groove side surface, or depositing an inorganic oxide insulating material into a gap between the first encapsulated component and the corresponding first groove side surface.
In some embodiments, fixing at least one second encapsulated component in the second recess in a one-to-one correspondence includes:
an insulating adhesive layer is formed at the bottom of the second groove;
adhering a second encapsulated element on the insulating adhesive, wherein a gap is reserved between the second encapsulated element and the side surface of the second groove;
and filling insulating materials between the second packaged element and the side surface of the corresponding second groove.
In some embodiments, filling the insulating material between the second encapsulated component and the corresponding second groove side surface comprises:
And filling and curing a resin material between the second encapsulated component and the corresponding second groove side surface, or depositing an inorganic oxide insulating material into a gap between the second encapsulated component and the corresponding second groove side surface.
In some embodiments, forming a planar surface exposing the first pad and the second electrode structure includes: the insulating material and the substrate material, which are higher than the first pad and the second electrode structure, are removed by a grinding process, followed by surface treatment.
In some embodiments, the substrate has a larger area, and a plurality of first grooves and second grooves can be formed. The manufacturing further includes: obtaining a plurality of semiconductor packaging structures through a cutting process, wherein at least one semiconductor packaging structure comprises: the semiconductor device comprises at least one first packaged element, at least one second packaged element, a first groove in which the first packaged element is located, a second groove in which the second packaged element is located, a rewiring layer electrically connected with the first packaged element and the second packaged element, and a passivation layer above the rewiring layer.
In some embodiments, the insulating material in the redistribution layer comprises a polymer or a molding compound.
In some embodiments, referring to fig. 7a to 7f and fig. 5a, a specific implementation procedure of the semiconductor packaging method is as follows.
First, referring to fig. 7a, a first groove H1 and a second groove H2 are formed on a substrate 1 by using an etching process, and the depth of the first grooves H1 is equal to that of the second grooves H2.
In the second step, referring to fig. 7b, an insulating adhesive layer 111 is formed at the bottoms of the first and second grooves H1 and H2.
Third, referring to fig. 7b, the first packaged components 22a, 23a are placed in the first grooves H1, the second packaged component 21a is placed in the second grooves H2, and the first packaged components 22a, 23a and the second packaged component 21a are adhered on the insulating adhesive 111, wherein the first bonding pads 221a of the first packaged component 22a and the first bonding pads 231a of the first packaged component 23a face upward, the thicknesses of the first packaged component 22a and the first packaged component 23a are equal, and the upper surfaces of the first bonding pads 221a, 231a and the second electrode structure 211a are flush. The first encapsulated component 22a, 23a and the second encapsulated component 21a are spaced from the side walls of the grooves H1, H2.
Fourth, referring to fig. 7c, the first and second grooves H1 and H2 are filled with and cured with an insulating material 112. For example, the liquid epoxy resin is dropped into the gap between the first groove H1 and the first encapsulated element 22a, 23a, the liquid epoxy resin is dropped into the gap between the second groove H2 and the second encapsulated element 21a, and the epoxy resin is cured by heating. Or an inorganic insulating material (for example, silicon dioxide) is deposited in the gap between the first recess H1 and the first encapsulated component 22a, 23a, and an inorganic insulating material is deposited in the gap between the second recess H2 and the second encapsulated component 21 a.
Fifth, referring to fig. 7d, the insulating material 112 and the substrate material raised above the first pads 221a, 231a and the second electrode structure 211a are ground and removed, and then a surface treatment process such as chemical cleaning, polishing, etc. is performed to obtain a flat surface exposing the first pads 221a, 231a and the second electrode structure 211 a.
Sixth, referring to fig. 7e, a re-wiring layer 3 is formed on this planar surface, the second pads 31 of the re-wiring layer 3 being in electrical contact with the first pads 221a, 231a and the second electrode structure 211a, respectively, and the third pads 32 of the re-wiring layer 3 being interconnected with the second pads 31.
Specifically, for example, a polyimide film is formed, and then a patterning process (e.g., photoresist coating, exposure, development, etching) is performed, so that a via hole exposing the first pads 221a, 231a and the second electrode structure 211a is formed in the polyimide film; then a layer of metal film is deposited, a layer of wiring 33 connected to each first bonding pad 221a and 231a and the second electrode structure 211a is formed through a patterning process, and the metal material in the lower layer of via hole forms a second bonding pad 31; then, a polyimide film is formed again and a via hole exposing the lower line is etched, and then a metal film is deposited, and a third pad 32 connected to the lower line 33 is formed through a patterning process. The rerouting layer may have one or more layers of traces 33 therein.
Of course, the patterning process may be first used to form the pattern of the second pad 31, then the polyimide film may be formed, then the via hole exposing the second pad 31 may be formed in the polyimide film, and then the pattern of the first layer trace 33 may be formed.
The rerouting layer can be prepared by a person skilled in the art according to the prior art.
Seventh, referring to fig. 7f, a passivation layer 4 is formed on the re-wiring layer 3. The material of the passivation layer 4 may be, for example, silicon nitride or polyimide (polyimide). The passivation layer 4 serves to protect the elements below it.
Eighth, referring to fig. 5a, a via hole is etched on the passivation layer 4, thereby exposing each of the third pads 32, and the first electrode structure 5 is formed on the third pads 32. The first electrode structure 5 includes, for example, an Under Bump Metal (UBM) over the third Pad 32 and a solder ball over the under bump metal, and of course, the first electrode structure 5 may be in the form of a Pad (Pad).
In some embodiments, referring to fig. 8a to 8f and 5b, the process of the semiconductor packaging method is as follows.
First, referring to fig. 8a, a plurality of first grooves H1 and second grooves H2 are formed on a substrate 1 by controlling a grooving process (e.g., step etching or multiple etching), and the depths of the grooves are not equal.
In the second step, referring to fig. 8b, an insulating adhesive layer 111 is formed at the bottoms of the first and second grooves H1 and H2.
Third, referring to fig. 8b, the first encapsulated component 22a and the first encapsulated component 23a are respectively placed in a first groove H1, the second encapsulated component 21a is placed in a second groove H2, and the first encapsulated component 22a, the second encapsulated component 23a and the second encapsulated component 21a are all adhered on the insulating adhesive 111, wherein the first bonding pad 221a of the first encapsulated component 22a and the first bonding pad 231a of the first encapsulated component 23a face upwards, the upper surfaces of the first bonding pads 221a, 231a and the second electrode structure 211a are flush, the thicknesses of the first encapsulated component 22a, 23a and the second encapsulated component 21a are not equal, and the depths of the grooves are not equal.
Fourth, referring to fig. 8c, the first and second grooves H1 and H2 are filled with and cured with an insulating material 112. For example, the epoxy resin in a liquid state is dropped into the gap between the first groove H1 and the first encapsulated element 22a, 23a and into the gap between the second groove H2 and the second encapsulated element 21a, and the epoxy resin is cured by heating.
Fifth, referring to fig. 8d, the insulating material and the substrate material raised above the first pads 221a, 231a and the second electrode structure 211a are removed by grinding, and then a surface treatment process such as chemical cleaning, polishing, etc. is performed to obtain a flat surface exposing the first pads 221a, 231a and the second electrode structure 211 a.
Sixth, referring to fig. 8e, a re-wiring layer 3 is formed on this planar surface, the second pads 31 of the re-wiring layer 3 are in electrical contact with the first pads 221a, 231a and the second electrode structure 211a, respectively, and the third pads 32 of the re-wiring layer 3 are interconnected with the second pads 31. The redistribution layer 3 includes at least one layer of trace 33, a via hole connecting the trace 33 and the second pad 31, and a via hole connecting the trace 33 and the third pad 32.
Seventh, referring to fig. 8f, a passivation layer 4 is formed on the re-wiring layer 3. The material of the passivation layer 4 may be, for example, silicon nitride or polyimide (polyimide). The passivation layer 4 serves to protect the elements below it.
Eighth, referring to fig. 5b, a via hole is etched on the passivation layer 4, thereby exposing each of the third pads 32, and the first electrode structure 5 is formed on the third pads 32. The first electrode structure 5 may comprise, for example, an Under Bump Metal (UBM) over the third Pad 32 and a solder ball over the under bump metal, and the first electrode structure 5 may also be a Pad (bonding Pad).
The embodiment of the application also provides a semiconductor device, which comprises the semiconductor packaging structure. The semiconductor package may be further processed, for example, combined with other semiconductor packages to form a module or assembly.
The embodiment of the application also provides an electronic product, which comprises: the aforementioned semiconductor device. The electronic products are various types of electronic products such as mobile phones, computers, servers, smart watches, and the like.
Due to the improvement of the stability of the semiconductor packaging structure, the stability of the semiconductor device and the electronic product is correspondingly improved.
The embodiments of the present application are described in a progressive manner, and the same and similar parts of the embodiments are all referred to each other, and each embodiment is mainly described in the differences from the other embodiments.
The scope of the present application is not limited to the above-described embodiments, and it is apparent that various modifications and variations can be made to the present application by those skilled in the art without departing from the scope and spirit of the application. It is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (48)

1. A semiconductor package structure, comprising: the packaging structure comprises a substrate, at least one packaged element, a rewiring layer and a passivation layer, wherein at least one groove is formed in the substrate, and the packaged elements are correspondingly fixed in the grooves one by one;
The active surfaces of the packaged elements are opposite to the substrate, the packaged elements are separated from the grooves where the packaged elements are located by insulating materials, each packaged element is provided with a first bonding pad positioned on the active surface of the packaged element, and the surfaces of all the first bonding pads opposite to the substrate are flush;
the rewiring layer is positioned on one side of the packaged element, which is opposite to the substrate, a plurality of second bonding pads are formed on a first surface of the rewiring layer, a plurality of third bonding pads are formed on a second surface of the rewiring layer, which is opposite to the first surface, the second bonding pads are in one-to-one corresponding electrical contact with the first bonding pads, and the rewiring layer is also provided with wires for electrically connecting the second bonding pads and the third bonding pads;
the passivation layer is positioned on one side of the rewiring layer, which is away from the substrate;
wherein the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficient of the substrate is the same as or similar to that of the semiconductor material in the packaged element.
2. The semiconductor package according to claim 1, wherein the semiconductor material in the substrate is the same as the semiconductor material in the packaged component.
3. The semiconductor package according to claim 1, wherein the semiconductor material in the packaged element is silicon or gallium arsenide, and the material of the substrate is engineering heat resistant glass.
4. The semiconductor package according to claim 1, wherein the number of the packaged components is plural and the thickness is equal, and the depth of each of the grooves is equal.
5. The semiconductor package according to claim 1, wherein the number of the packaged components is plural, and thicknesses of at least two packaged components are not equal, wherein depths of at least two grooves are different so that upper surfaces of the first pads of the packaged components are flush.
6. The semiconductor package according to claim 1, further comprising an electrode structure located on a side of the passivation layer facing away from the substrate, wherein a via hole is formed in a region of the passivation layer opposite to the third pad, the electrode structure is in one-to-one correspondence with the third pad, and the electrode structure is electrically connected to the corresponding third pad through the via hole.
7. The semiconductor package according to claim 1, wherein the packaged element is in a bare die state.
8. The semiconductor package according to claim 1, wherein the encapsulated component is separated from the bottom of the recess by an insulating adhesive layer.
9. The semiconductor package according to claim 1, wherein the encapsulated component is separated from the side surface of the recess by a cured resin material or an inorganic insulating material.
10. The semiconductor package according to claim 1, wherein the conductors in the redistribution layer are separated from each other by a polymer or a molding compound.
11. A semiconductor packaging method, comprising:
forming at least one recess in a substrate;
fixing at least one packaged element in the grooves in a one-to-one correspondence manner, wherein the active surfaces of the packaged elements face away from the substrate, the packaged elements are separated from the grooves in which the packaged elements are positioned by insulating materials, each packaged element is provided with a first bonding pad positioned on the active surface of the packaged element, and the surfaces of all the first bonding pads facing away from the substrate are flush;
forming a planar surface exposing the first bonding pad;
forming a rerouting layer, wherein a plurality of second bonding pads are formed on a first surface of the rerouting layer, a plurality of third bonding pads are formed on a second surface of the rerouting layer opposite to the first surface, the second bonding pads are in one-to-one corresponding electric contact with the first bonding pads, and the rerouting layer is also provided with wires for electrically connecting the second bonding pads and the third bonding pads;
Forming a passivation layer;
wherein the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficient of the substrate is the same as or similar to that of the semiconductor material in the packaged element.
12. The method of claim 11, wherein the semiconductor material within the substrate is the same as the semiconductor material within the packaged component.
13. The method of claim 11, wherein the semiconductor material within the packaged component is silicon or gallium arsenide and the material of the substrate is engineering heat resistant glass.
14. The method of claim 11, wherein the number of packaged components is a plurality of the same depth of the recess, the method further comprising: at least part of the encapsulated components are thinned so that the thickness of each encapsulated component is equal.
15. The method of claim 11, wherein the number of packaged components is plural and the thickness of at least two packaged components is not equal, and when grooves are formed on the substrate, the depths of at least two grooves are not equal so that the upper surfaces of the first pads of each packaged component are flush.
16. The method of claim 11, wherein securing at least one encapsulated component within the recess in a one-to-one correspondence comprises:
an insulating adhesive layer is formed at the bottom of the groove;
adhering the encapsulated element to the insulating adhesive, wherein a gap is reserved between the encapsulated element and the side surface of the groove;
and filling insulating materials between the packaged element and the side surface of the corresponding groove.
17. The method of claim 16, wherein filling insulating material between the encapsulated component and the corresponding recess sides comprises:
and filling and curing resin materials between the packaged element and the corresponding groove side surfaces, or depositing inorganic oxide insulating materials into gaps between the packaged element and the corresponding groove side surfaces.
18. The method of claim 11, wherein forming a planar surface exposing the first pad comprises:
and removing the insulating material and the substrate material which are higher than the first bonding pad through a grinding process, and then carrying out surface treatment.
19. The method as recited in claim 11, further comprising:
Forming at least one via hole on the passivation layer, wherein the via hole corresponds to the third bonding pad one by one, and the corresponding third bonding pad is exposed by the via hole;
an electrode structure is formed on the third pad in electrical contact therewith.
20. The method according to claim 11 or 19, further comprising:
obtaining a plurality of semiconductor packaging structures through a cutting process, wherein each semiconductor packaging structure at least comprises: the packaged component comprises a packaged component, a groove in which the packaged component is positioned, a rewiring layer electrically connected with the packaged component, and a passivation layer above the rewiring layer.
21. The method of claim 11, wherein the insulating material in the redistribution layer comprises a polymer or a molding compound.
22. The method of claim 11, wherein the packaged component is in a die state.
23. A semiconductor package structure, comprising: the semiconductor packaging structure comprises a substrate, at least one first packaged element, at least one second packaged element, a rewiring layer and a passivation layer, wherein at least one first groove and at least one second groove are formed in the substrate, the first packaged elements are fixed in the first grooves in a one-to-one correspondence manner, the second packaged elements are fixed in the second grooves in a one-to-one correspondence manner, the first packaged elements are in a bare chip state, and the second packaged elements are in a packaging state and have exposed second electrode structures;
The active surfaces of the first packaged elements are opposite to the substrate, the first packaged elements are separated from the first grooves where the first packaged elements are located by insulating materials, the second packaged elements are separated from the second grooves where the second packaged elements are located by insulating materials, each first packaged element is provided with a first bonding pad positioned on the active surface of the first packaged element, and all the first bonding pads are flush with the surface opposite to the substrate and all the second electrode structures are flush with the surface opposite to the substrate;
the rewiring layer is positioned on one side of the packaged element, which is opposite to the substrate, a plurality of second bonding pads are formed on a first surface of the rewiring layer, a plurality of third bonding pads are formed on a second surface of the rewiring layer, which is opposite to the first surface, the first bonding pads are in one-to-one corresponding electric contact with part of the second bonding pads, the second electrode structures are in one-to-one corresponding electric contact with the rest of the second bonding pads, and the rewiring layer is also provided with wires for electrically connecting the second bonding pads with the third bonding pads and wires for electrically connecting the second bonding pads with the second electrode structures;
the passivation layer is positioned on one side of the rewiring layer, which is away from the substrate;
wherein the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficient of the substrate is the same as or similar to that of the semiconductor material in the packaged element.
24. The semiconductor package according to claim 23, wherein the semiconductor material in the substrate is the same as the semiconductor material in the packaged component.
25. The semiconductor package according to claim 23, wherein the semiconductor material in the packaged element is silicon or gallium arsenide, and the material of the substrate is engineering heat resistant glass.
26. The semiconductor package according to claim 23, wherein the number of the first packaged elements is plural and the thickness is equal, and the depth of each of the first grooves is equal.
27. The semiconductor package according to claim 23, wherein the number of the first packaged components is plural, and thicknesses of at least two first packaged components are not equal, wherein depths of at least two first grooves are different so that upper surfaces of first pads of the first packaged components are flush.
28. The semiconductor package according to claim 23, further comprising a first electrode structure on a side of the passivation layer facing away from the substrate, wherein vias are provided in regions of the passivation layer opposite to the third pads, the first electrode structure being in one-to-one correspondence with the third pads, and the first electrode structure being electrically connected to the corresponding third pads through the vias.
29. The semiconductor package according to claim 23, wherein the first encapsulated component is separated from the bottom of the first recess by an insulating adhesive layer, and the second encapsulated component is separated from the bottom of the second recess by an insulating adhesive layer.
30. The semiconductor package according to claim 23, wherein the first encapsulated component is separated from the side surface of the first recess by a cured resin material or an inorganic insulating material, and the second encapsulated component is separated from the side surface of the second recess by a cured resin material or an inorganic insulating material.
31. The semiconductor package according to claim 23, wherein the conductors in the redistribution layer are separated from each other by a polymer or a molding compound.
32. The semiconductor package according to claim 23, wherein the second packaged element is a chip package or a ceramic package.
33. A semiconductor packaging method, comprising:
forming at least one first groove and at least one second groove on a substrate;
fixing at least one first packaged element in the first groove in a one-to-one correspondence manner, fixing at least one second packaged element in the second groove in a one-to-one correspondence manner, wherein the first packaged element is in a bare chip state, the second packaged element is in a packaged state and is provided with an exposed second electrode structure, the active surface of the first packaged element faces away from the substrate, the first packaged element is separated from the first groove where the first packaged element is located by an insulating material, the second packaged element is separated from the second groove where the second packaged element is located by an insulating material, each first packaged element is provided with a first bonding pad positioned on the active surface of the second packaged element, and the surfaces of all the first bonding pads and all the second electrode structures facing away from the substrate are flush;
Forming a flat surface exposing the first bonding pad and the second electrode structure;
forming a rerouting layer, wherein a plurality of second bonding pads are formed on a first surface of the rerouting layer, a plurality of third bonding pads are formed on a second surface of the rerouting layer opposite to the first surface, the first bonding pads are in one-to-one corresponding electric contact with part of the second bonding pads, the second electrode structures are in one-to-one corresponding electric contact with the rest of the second bonding pads, and the rerouting layer is provided with wires electrically connecting the second bonding pads and the third bonding pads and wires electrically connecting the second bonding pads and the second electrode structures;
forming a passivation layer;
wherein the substrate is formed of a semiconductor material or an insulating material, and the thermal expansion coefficient of the substrate is the same as or similar to that of the semiconductor material in the packaged element.
34. The method of claim 33, wherein the semiconductor material within the substrate is the same as the semiconductor material within the packaged component.
35. The method of claim 33, wherein the semiconductor material within the packaged component is silicon or gallium arsenide and the material of the substrate is engineering heat resistant glass.
36. The method of claim 33, wherein the number of first encapsulated components is a plurality of first recesses having the same depth, the method further comprising: at least part of the first encapsulated components are thinned so that the thickness of each first encapsulated component is equal.
37. The method of claim 33, wherein the thicknesses of at least two of the first and second packaged components are unequal, and wherein the depths of at least two of the recesses are unequal when the first and second recesses are formed in the substrate such that the upper surface of the first bonding pad of each of the first packaged components and the upper surface of each of the second electrode structures are flush.
38. The method of claim 33, wherein securing at least one first encapsulated component within the first recess in a one-to-one correspondence comprises:
an insulating adhesive layer is formed at the bottom of the first groove;
adhering the first encapsulated element to the insulating adhesive, wherein a gap is reserved between the first encapsulated element and the side surface of the first groove;
and filling insulating materials between the first encapsulated element and the side surface of the corresponding first groove.
39. The method of claim 38, wherein filling the first encapsulated component with insulating material between the first encapsulated component and the corresponding first recess side surface comprises:
and filling and curing resin materials between the first encapsulated component and the corresponding first groove side surface, or depositing inorganic oxide insulating materials into gaps between the first encapsulated component and the corresponding first groove side surface.
40. The method of claim 33, wherein securing at least one second encapsulated component in the second recess in a one-to-one correspondence comprises:
an insulating adhesive layer is formed at the bottom of the second groove;
adhering the second encapsulated element to the insulating adhesive, wherein a gap is reserved between the second encapsulated element and the side surface of the second groove;
and filling insulating materials between the first encapsulated element and the side surface of the corresponding first groove.
41. The method of claim 40, wherein filling insulating material between the second encapsulated component and the corresponding second recess side comprises:
and filling and curing resin materials between the second encapsulated component and the corresponding second groove side surface, or depositing inorganic oxide insulating materials into gaps between the second encapsulated component and the corresponding second groove side surface.
42. The method of claim 33, wherein forming a planar surface exposing the first pad and the second electrode structure comprises:
and removing the insulating material and the substrate material which are higher than the first bonding pad and the second electrode structure through a grinding process, and then carrying out surface treatment.
43. The method as recited in claim 33, further comprising:
forming a plurality of through holes on the passivation layer, wherein the through holes are in one-to-one correspondence with the third bonding pads, and the corresponding third bonding pads are exposed by the through holes;
and forming a first electrode structure on the third bonding pad, wherein the first electrode structure is electrically contacted with the third bonding pad.
44. The method of claim 33 or 43, further comprising:
obtaining a plurality of semiconductor packaging structures through a cutting process, wherein at least one semiconductor packaging structure comprises: at least one first encapsulated component, at least one second encapsulated component, a first groove in which the first encapsulated component is located, a second groove in which the second encapsulated component is located, a rewiring layer electrically connected to the first encapsulated component and the second encapsulated component, and a passivation layer over the rewiring layer.
45. The method of claim 33, wherein the insulating material in the redistribution layer comprises a polymer or a molding compound.
46. The method of claim 33, wherein the second encapsulated component is a chip-on-package or a ceramic package.
47. A semiconductor device, comprising: the semiconductor package structure according to any one of claims 1 to 10, or comprising: the semiconductor package according to any one of claims 23 to 32.
48. An electronic product, comprising: the semiconductor device of claim 47.
CN202110272185.1A 2021-03-12 2021-03-12 Semiconductor packaging structure, method, device and electronic product Active CN113078149B (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN202110272185.1A CN113078149B (en) 2021-03-12 2021-03-12 Semiconductor packaging structure, method, device and electronic product
TW111105827A TWI787085B (en) 2021-03-12 2022-02-17 Semiconductor packaging structure, semiconductor packaging method, semiconductor packaging device and electronic product
KR1020220030531A KR102625995B1 (en) 2021-03-12 2022-03-11 Semiconductor package structures, methods, devices and electronic products
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