CN113053906A - 存储器元件及其制造方法 - Google Patents

存储器元件及其制造方法 Download PDF

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CN113053906A
CN113053906A CN202010018026.4A CN202010018026A CN113053906A CN 113053906 A CN113053906 A CN 113053906A CN 202010018026 A CN202010018026 A CN 202010018026A CN 113053906 A CN113053906 A CN 113053906A
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钟曜安
裘元杰
廖廷丰
刘光文
陈光钊
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Macronix International Co Ltd
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Abstract

本发明公开了一种存储器元件及其制造方法。存储器元件包括一衬底。第一介电层设置在该衬底上方。多层导电层与多层介电层，交替且水平地设置在该衬底上。通道柱结构设置在该衬底上且在该多层导电层与该多层介电层中。该通道柱结构的侧壁与该多层导电层接触。第二介电层覆盖在该第一介电层上。导电柱结构在该第一与第二介电层中，相邻于该通道柱结构，与该多层导电层的其一接触。该导电柱结构包括一衬绝缘层当作外层。

Description

存储器元件及其制造方法
技术领域
本发明是有关于半导体制造，且特别是关于存储器元件及其制造方法。
背景技术
存储器元件在数字电子装置中是属于必备的部件。当电子装置的处理功能大幅提升的状况下，其存储器元件的存储容量也因应要提升，且同时也要维持缩小存储器元件尺寸的趋势。
因应需求，三维的NAND存储器已有被提出，其是闪存，从二维的NAND存储器改变成三维的架构，其通道层修改为垂直于衬底的垂直通道结构，其是通道柱(channel column)的结构。多层的字线层在垂直于衬底的方向叠置，构成一串晶体管。字线层的末端是以类似楼梯(staircase)状的结构，通过导电柱将字线往上连接到外部的控制电路。如此在三维的架构下，晶体管可以往垂直的方向制造，可以提升存储容量。
然而由于元件面积是有限，因此横向的二维面积还是需要大幅缩减，对于大数量的导电柱结构与通道柱结构是需要高密度配置，而柱之间的距离需要缩小。由于导电柱结构所提供字线层数大幅增加，导电柱结构与通道柱结构的长度也因应增加能连接到上部的控制电路。
在这种需求下，如何必安排导电柱结构与通道柱结构的配置是需要考虑。
发明内容
本发明的存储器元件，在导电柱结构与通道柱结构的制造提出导电柱的结构，在导电柱结构与通道柱结构之间的距离缩小且其长度大幅增加的需求下，可以有效减少导电柱结构与通道柱结构之间的在末端造成漏电或甚至短路的现象。
于一实施例，本发明提供一种存储器元件包括一衬底。第一介电层设置在该衬底上方。多层导电层与多层介电层交替且水平地设置在该衬底上。通道柱结构设置在该衬底上且在该多层导电层与该多层介电层中。该通道柱结构的侧壁与该多层导电层接触。第二介电层覆盖在该第一介电层上。导电柱结构在该第一与第二介电层中，相邻于该通道柱结构，与该多层导电层的其一接触。该导电柱结构包括一衬绝缘层当作外层。
于一实施例，对于所述的存储器元件，该通道柱结构包括垂直于该衬底的硅柱以及电荷存储层。电荷存储层包覆该硅柱。该电荷存储层与该多层导电层接触。该硅柱对应每一层该导电层处提一通道。
于一实施例，对于所述的存储器元件，该电荷存储层是氧化物/氮化物/氧化物的叠层结构。
于一实施例，对于所述的存储器元件，该导电柱结构包括垂直于该衬底的导电中心柱，与该多层导电层中所预定的其一接触。该衬绝缘层包覆该导电中心柱，辅助使该导电中心柱与该通道柱结构隔离。
于一实施例，对于所述的存储器元件，该导电中心柱的材料包括钨、铜、钴、硅、或是多晶硅。
于一实施例，对于所述的存储器元件，该衬绝缘层是氧化硅、高密度电浆(HDP)介电质、四乙氧基硅烷(TEOS)、热氧化物或高介电常数介电质。
于一实施例，对于所述的存储器元件，该衬绝缘层的上端与该导电中心柱接触的面是斜曲面。
于一实施例，对于所述的存储器元件，该导电中心柱的底面包含向侧方向凸出的部分。
于一实施例，对于所述的存储器元件，该导电柱结构高于该通道柱结构。
于一实施例，对于所述的存储器元件，该导电柱结构的长度是3微米或是大于3微米。
于一实施例，本发明提供一种制造存储器元件的方法，包括提供一衬底。形成第一介电层在该衬底上方。形成多层导电层与介电层交替且水平地设置在该衬底上。形成通道柱结构在该衬底上且在该多层导电层与该多层介电层中，其中该通道柱结构的侧壁与该多层导电层接触。形成第二介电层，覆盖在该第一介电层上。形成导电柱结构在该第一与第二介电层中，相邻于该通道柱结构，与该多层导电层的其一接触，其中该导电柱结构包括一衬绝缘层当作外层。
于一实施例，对于所述的制造存储器元件的方法，形成该通道柱结构的步骤包括形成柱状凹陷在该第一介电层中，且穿过该多层导电层。形成电荷存储层在该柱状凹陷的侧壁，其中该电荷存储层与该多层导电层接触。形成硅柱填入该柱状凹陷在该电荷存储层上，其中该硅柱对应每一层该导电层处提供一通道区域。
于一实施例，对于所述的制造存储器元件的方法，该电荷存储层是氧化物/氮化物/氧化物的叠层结构。
于一实施例，对于所述的制造存储器元件的方法，形成该导电柱结构的步骤包括形成柱状凹陷在该第一与第二介电层中，且延伸到该多层导电层中所预定的其一。形成该衬绝缘层在该柱状凹陷的侧壁。将导电材料填满该柱状凹陷形成导电中心柱，与该多导电层中所预定的该其一接触。该衬绝缘层是包覆该导电材料，也提供该导电材料与该通道柱结构的隔离。
于一实施例，对于所述的制造存储器元件的方法，该导电材料包括钨、铜、钴、硅、或是多晶硅。
于一实施例，对于所述的制造存储器元件的方法，该衬绝缘层的材料包括氧化硅、高密度电浆(HDP)介电质、四乙氧基硅烷(TEOS)、热氧化物或高介电常数介电质。
于一实施例，对于所述的制造存储器元件的方法，该衬绝缘层的上端具有回刻蚀该衬绝缘层后所产生的斜曲面结构。
于一实施例，对于所述的制造存储器元件的方法，该导电中心柱的底面包含向侧方向凸出的部分，该部分占据在填入该导电材料前所进行的表面清洁所产生的移除空间。
于一实施例，对于所述的制造存储器元件的方法，该导电柱结构高于该通道柱结构。
于一实施例，对于所述的制造存储器元件的方法，该导电柱结构的长度是3微米或是大于3微米。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1是依据本发明所探究的导电柱结构与通道柱结构之间所存在的缺陷示意图。
图2是依据本发明一实施例，存储器元件的导电柱结构与通道柱结构的剖面结构示意图。
图3A到图3D是依据本发明一实施例，制造存储器元件的导电柱结构与通道柱结构的流程示意图。
图4是依据本发明一实施例，导电柱结构与通道柱结构的剖面结构示意图。
图5是依据本发明一实施例，导电柱结构与通道柱结构的剖面结构示意图。
【符号说明】
100：衬底
102：介电层
104：导电层
106：介电层
108：中心柱
110：硅柱
112：电荷存储层
114：通道柱结构
118：导电柱结构
120：介电层
122：衬绝缘层
130：凹陷
200：导电中心柱
202：衬绝缘层
204：导电柱结构
210：上端部
212：下端部
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。
本发明提出存储器元件，通过导电柱结构与通道柱结构的改变，可以增加导电柱结构与通道柱结构之间的隔离效果。如此，在导电柱结构与通道柱结构之间距离缩小且其长度大幅增加的需求下，可以有效减少导电柱结构与通道柱结构之间的在末端造成漏电或甚至短路的现象。
以下举多个实施例来说明，但是本发明不限于所举的实施例。另外，多个实施例之间也允许有适当的结合。
本发明对三维NAND存储器元件的结构进行探究(looking into)。图1是依据本发明所探究的导电柱结构与通道柱结构之间所存在的缺陷示意图。
参阅图1，对于三维NAND存储器元件，其一串晶体管是沿着垂直于衬底100的通道柱结构114配置。通道柱结构114包含中间的硅柱110以及包覆硅柱110的电荷存储层112。硅柱110例如是中空的多晶硅柱。依照制造方法，中心柱108是后续会填入氧化层所构成。另外一种，也可以是全部填入多晶硅构成实心的硅柱110。本发明不需要限制通道柱结构114的特定结构。硅柱结构110提供晶体管所需要的通道层。电荷存储层112例如是氧化物/氮化物/氧化物(oxide/nitride/oxide,ONO)的结构。多层导电层104，也当作字线控制在通道柱结构114上所对应的晶体管的栅极。依照NAND的一串晶体管的数量会至少设置等数量的导电层104。导电层104之间由介电层102隔离以及支撑。如此，多层介电层102与多层导电层104是交替叠置在衬底100上。于此，导电层104的数量以二层为例，实际上是依照一串晶体管的数量而定，例如32层、64层又或是其它数量。因此，通道柱结构114的长度会很长。
另外导电柱结构118相邻于通道柱结构114也形成在介电106、120中。导电柱结构118会与在这些导电层104中所预定的一层接触，以提供此字线所需要的电压。
本发明观察到当元件密集后，导电柱结构118与通道柱结构114之间的距离会缩小，但是由于导电柱结构118与通道柱结构114的长度因应多层的数量也会很大。因此导致在二者末端出会接近，可造成漏电或是甚至直接接触，造成此存储单元串的失效。
本发明经过对导电柱结构118与通道柱结构114的探究，提出至少可以提升导电柱结构118与通道柱结构114之间的隔离效果。
图2是依据本发明一实施例，存储器元件的导电柱结构与通道柱结构的剖面结构示意图。参阅图2，存储器元件包括一衬底100。第一介电层106设置在衬底100上。多层导电层104与多层介电层102交替且水平地设置在衬底100上。于一实施例，导电层104的材料也可以是钨或是其它的导电体，例如钨、铜、钴、硅、或是多晶硅。
通道柱结构114设置在衬底100上且在多层导电层104与多层介电层102中。通道柱结构114的侧壁与多层导电层104接触。第二介电层120覆盖在第一介电层106上。导电柱结构204在两个介电层106、120中，相邻于通道柱114，与多层导电层104的所预定其一层接触。导电柱结构204的外层包括一衬绝缘层202。导电柱结构204的中心是导电中心柱200。
通道柱结构114的结构例如是图1所描述的结构。于此要注意的是，导电柱结构204包括垂直于衬底100的导电中心柱200，与多层导电层104中所预定的其一层接触。衬绝缘层202包覆导电中心柱200且与介电层106接触，辅助使导电中心柱200与通道柱结构114隔离。导电中心柱200的材料包括钨、铜、钴、硅、或是多晶硅。衬绝缘层202的材料是氧化硅、高密度电浆(HDP)介电质、四乙氧基硅烷(TEOS)、热氧化物或高介电常数介电质。
由于导电柱结构204外表层(shell layer)是衬绝缘层202，其提供进一步的隔离效果，在不实质改变导电柱结构204的密集尺寸下，其可以提升与通道柱结构114的隔离效果。
以下描述制造的流程的多个实施例。图3A到图3D是依据本发明一实施例，制造存储器元件的导电柱结构与通道柱结构的流程示意图。
参阅图3A，先就通道柱结构114的形成，于一实施例，在介电层106先形成柱状的凹陷，其延伸到基底100。于一实施例，通过沉积初始的电荷存储层以及回刻蚀，在柱状的凹陷的侧壁形成电荷存储层112。再通过沉积初始的多晶硅层以及回刻蚀，在电荷存储层112上也形成硅柱110。于一实施例，初始的多晶硅层的厚度较小，不足以全部填满凹陷，因此是中空的硅柱110。于一实施例，中心柱108可以在后续形成介电层120时填入。再一实施例，初始的多晶硅层可以全部填满凹陷，如此通过对多晶硅层研磨而形成实心的硅柱110，其包含多晶硅的中心柱108。本发明不限于形成通道柱结构114的特定方式。
其后，另一层介电层120再形成于介电层106上。介电层120的厚度是根据预计的导电柱结构204的高度而定。通过使用光刻与刻蚀工艺，在两层介电层106、120中形成大深度的凹陷130。此凹陷130的深度会到达对应的一层导电层104，但是不会与其它的导电层104接触。
参阅图3B，初始的衬绝缘层122共形沉积于凹陷130的表面。参阅图3C，通过对衬绝缘层122进行回刻蚀，衬绝缘层122的剩余部分是衬绝缘层202，形成在凹陷130的侧壁。
参阅图3D，导电中心柱200再填入凹陷130后完成导电柱结构204的形成。本发明在维持导电柱结构204的宽幅下，利用再形成的衬绝缘层202可以提升导电中心柱200的隔离。也就是说，虽然有介电层106、120的隔离，本发明再形成衬绝缘层202提升隔离效果。
基于衬绝缘层202的形成，导电中心柱200在上端部210与下端部212会形成因应的结构。
图4是依据本发明一实施例，导电柱结构与通道柱结构的剖面结构示意图。参阅图4，针对导电中心柱200在上端部210，在局部观察下，会往侧方向扩张的结构，其是因为在图3C对衬绝缘层122进行回刻蚀时，回刻蚀造成衬绝缘层202的顶部有斜曲面的结构。当导电中心柱200填入时，其扩张的空间会被导电中心柱200填满。
图5是依据本发明一实施例，导电柱结构与通道柱结构的剖面结构示意图。参阅图5，针对导电中心柱200在下端部212，在局部观察下，其底面包含向侧方向凸出的部分。这是因为在图3C对衬绝缘层122进行回刻蚀后会对导电层104的暴露表面进行清洁，例如是稀释氢氟酸的清洁。此清洁过程会对凹陷130的底部产生微量刻蚀，导致底部面往侧向扩张。扩张的空间在填入导电中心柱200后也会填入此扩张的空间。
本发明的衬绝缘层202的进一步形成，使得导电中心柱200在上端部210与下端部212会观察到对应的结构。本发明的导电柱结构204包含衬绝缘层202，可以增加导电中心柱200隔离效果。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

1.一种存储器元件，包括：
一衬底；
第一介电层在该衬底上方；
多层导电层与多层介电层，交替且水平设置在该衬底上；
通道柱结构，在该衬底上的该多层导电层与该多层介电层中，其中该通道柱结构的侧壁与该多层导电层接触；
第二介电层，覆盖在该第一介电层上；以及
导电柱结构在该第一与第二介电层中，相邻于该通道柱结构，与该多层导电层的其一接触，其中该导电柱结构包括一衬绝缘层当作外层。
2.根据权利要求1所述的存储器元件，其中该通道柱结构包括：
垂直于该衬底的硅柱；以及
电荷存储层，包覆该硅柱，该电荷存储层与该多层导电层接触，
其中该硅柱对应每一层该导电层处提一通道。
3.根据权利要求1所述的存储器元件，其中该电荷存储层是氧化物/氮化物/氧化物的叠层结构。
4.根据权利要求1所述的存储器元件，其中该导电柱结构包括：
垂直于该衬底的导电中心柱，与该多层导电层中所预定的其一接触；以及
该衬绝缘层，包覆该导电中心柱，辅助使该导电中心柱与该通道柱结构隔离。
5.根据权利要求1所述的存储器元件，其中该导电柱结构高于该通道柱结构。
6.一种制造存储器元件的方法，包括：
提供一衬底；
形成第一介电层在该衬底上方；
形成多层导电层与多层介电层，交替且水平地设置在衬底上；
形成通道柱结构在衬底上且在该多层导电层与该多层介电层中，其中该通道柱结构的侧壁与该多层导电层接触；
形成第二介电层，覆盖在该第一介电层上；以及
形成导电柱结构在该第一与第二介电层中，相邻于该通道柱结构，与该多层导电层的其一接触，其中该导电柱结构包括一衬绝缘层当作外层。
7.根据权利要求6所述的制造存储器元件的方法，其中形成该通道柱结构的步骤包括：
形成柱状凹陷在该第一介电层中，且穿过该多层导电层；
形成电荷存储层在该柱状凹陷的侧壁，其中该电荷存储层与该多层导电层接触；以及
形成硅柱填入该柱状凹陷在该电荷存储层上，其中该硅柱对应每一层该导电层处提供一通道区域。
8.根据权利要求6所述的制造存储器元件的方法其中该电荷存储层是氧化物/氮化物/氧化物的叠层结构。
9.根据权利要求6所述的制造存储器元件的方法，其中形成该导电柱结构的步骤包括：
形成柱状凹陷在该第一与第二介电层中，且延伸到该多层导电层中所预定的其一；
形成该衬绝缘层在该柱状凹陷的侧壁；以及
将导电材料填满该柱状凹陷形成导电中心柱，与该多导电层中所预定的该其一接触，
其中该衬绝缘层是包覆该导电材料，也提供该导电材料与该通道柱结构的隔离。
10.根据权利要求6所述的制造存储器元件的方法，其中该导电柱结构高于该通道柱结构。
CN202010018026.4A 2019-12-27 2020-01-08 存储器元件及其制造方法 Pending CN113053906A (zh)

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