CN113009624A - Optical device test structure and manufacturing method thereof - Google Patents
Optical device test structure and manufacturing method thereof Download PDFInfo
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- CN113009624A CN113009624A CN202110189580.3A CN202110189580A CN113009624A CN 113009624 A CN113009624 A CN 113009624A CN 202110189580 A CN202110189580 A CN 202110189580A CN 113009624 A CN113009624 A CN 113009624A
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- 230000003287 optical effect Effects 0.000 title claims abstract description 70
- 238000012360 testing method Methods 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 16
- 238000005253 cladding Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 230000008901 benefit Effects 0.000 abstract description 11
- 238000004806 packaging method and process Methods 0.000 abstract description 10
- 230000008878 coupling Effects 0.000 description 11
- 238000010168 coupling process Methods 0.000 description 11
- 238000005859 coupling reaction Methods 0.000 description 11
- 238000002360 preparation method Methods 0.000 description 5
- 239000013307 optical fiber Substances 0.000 description 4
- 238000012544 monitoring process Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12133—Functions
- G02B2006/12147—Coupler
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12166—Manufacturing methods
- G02B2006/12176—Etching
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Optical Integrated Circuits (AREA)
- Optical Couplings Of Light Guides (AREA)
Abstract
The present disclosure provides an optical device testing structure and a method for manufacturing the same, wherein the structure includes: a substrate; and a device layer formed on the substrate, the device layer comprising an optical device, an end-face coupler, and a grating coupler; wherein the optical device is connected with the end face coupler through an optical waveguide; the end face coupler is coupled with the grating coupler, and the grating coupler is located in a region of the substrate where a scribing deep groove is to be manufactured. The optical device testing structure combines the advantages of the end face coupler and the grating coupler, and can simultaneously solve the problems of wafer level testing and chip packaging of optical chips.
Description
Technical Field
The disclosure relates to the technical field of photonic equipment, in particular to an optical device testing structure and a manufacturing method thereof.
Background
The silicon photonic technology uses silicon as an optical medium, and develops and integrates an optical device by using a Complementary Metal Oxide Semiconductor (CMOS) process, so that the silicon photonic technology is expected to realize low-cost and high-speed optical communication and has wide market application prospects.
One of the key issues inhibiting the widespread use of silicon photonic chips (optical chips for short) is the coupling of optical fibers with optical chips. The problem of coupling to optical fibers is a problem that any optical chip or product must solve. Silicon waveguide couplers mainly include two types, namely, grating couplers and end-face couplers.
The grating coupler has the advantages that the wafer-level optical coupling can be realized, the coupling test can be carried out at any time in the wafer preparation process, and the defects of large loss, small bandwidth and large volume of a packaged chip are overcome; the end face Coupler (Edge Coupler) has the advantages of low loss, large bandwidth and small volume after chip packaging, and has the defects of incapability of wafer-level coupling and coupling test at any time in the process so as to monitor the performance of an optical device at any time.
In the manufacturing process of the optical chip, the grating coupler is required to perform on-line wafer-level testing and wafer-level rapid testing after preparation is completed, but the end-face coupler is required to perform chip packaging coupling finally.
Disclosure of Invention
The present disclosure is directed to an optical device testing structure and a method for fabricating the same, which can simultaneously solve the problems of wafer level testing and chip packaging of optical chips.
An embodiment of a first aspect of the present disclosure provides an optical device testing structure, including:
a substrate; and
a device layer formed on the substrate, the device layer including an optical device, an end-face coupler, and a grating coupler;
wherein the optical device is connected with the end face coupler through an optical waveguide; the end face coupler is coupled with the grating coupler, and the grating coupler is located in a region of the substrate where a scribing deep groove is to be manufactured.
In some embodiments according to the present disclosure, the end-face coupler is an inverted cone end-face coupler or a cantilever beam end-face coupler.
According to some embodiments of the present disclosure, the substrate comprises: the device comprises a silicon substrate and a buried oxide layer formed on the silicon substrate, wherein the device layer is formed on the buried oxide layer.
According to some embodiments of the present disclosure, the buried oxide layer is made of silicon oxide.
Some embodiments according to the present disclosure further comprise: an upper cladding layer formed on the device layer.
According to some embodiments of the present disclosure, the upper cladding layer is made of silicon oxide.
An embodiment of a second aspect of the present disclosure provides a method for manufacturing an optical device test structure, including:
providing a substrate comprising: the buried oxide layer is formed on the silicon substrate;
forming a device layer on the buried oxide layer, wherein the device layer comprises an optical device, an end face coupler and a grating coupler; wherein the optical device is connected with the end face coupler through an optical waveguide; the end face coupler is coupled with the grating coupler, and the grating coupler is positioned in a region on the substrate where a scribing deep groove is to be manufactured;
forming an upper cladding layer on the device layer;
and etching the scribing deep groove in the region to be manufactured with the scribing deep groove on the substrate, sequentially etching the upper cladding, the grating coupler and the oxygen burying layer in the region, and etching the silicon substrate with the preset depth.
In some embodiments according to the present disclosure, the end-face coupler is an inverted cone end-face coupler or a cantilever beam end-face coupler.
This disclosure compares advantage with prior art and lies in:
the optical device testing structure provided by the disclosure combines the advantages of the end face coupler and the grating coupler, can be used for coupling testing at any time in the wafer preparation process through the grating coupler, and is convenient for monitoring the performance of an optical device at any time; because the grating coupler is positioned in the area of the scribing deep groove to be manufactured, when the wafer is prepared and scribed into a chip, the grating coupler is removed incidentally, and the chip is packaged through the end face coupler, so that the volume after packaging is small. Therefore, the optical device testing structure provided by the disclosure can simultaneously solve the wafer level testing and chip packaging problems of the optical chip.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the disclosure. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 illustrates a side view of an optical device testing structure provided by the present disclosure;
FIG. 2 illustrates a top view of an optical device testing structure provided by the present disclosure;
FIG. 3 illustrates a side view of another optical device testing structure provided by the present disclosure;
fig. 4 shows a side view of a scribe deep trench provided by the present disclosure;
FIG. 5 illustrates a front view of a cantilever release window provided by the present disclosure along line ab;
FIG. 6 illustrates a front view of a cantilevered silicon substrate provided by the present disclosure etched along line ab;
figure 7 illustrates a front view of a cantilevered silicon substrate provided by the present disclosure after further etching along line ab.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
In order to solve the problems in the prior art, embodiments of the present disclosure provide an optical device testing structure and a method for manufacturing the same, which are described below with reference to the accompanying drawings.
FIG. 1 illustrates a side view of an optical device testing structure provided by the present disclosure; FIG. 2 illustrates a top view of an optical device testing structure provided by the present disclosure; as shown in fig. 1 and 2, the present disclosure provides the above optical device testing structure, including:
a substrate 100; and
device layers formed on the substrate 100, the device layers including an optical device 210, an end-face coupler 220, and a grating coupler 230;
wherein the optical device 210 and the end-face coupler 220 are connected by an optical waveguide; the end-face coupler 220 is coupled to the grating coupler 230, and the grating coupler 230 is located in a region a of the substrate 100 where a deep groove to be scribed is to be formed.
Specifically, as shown in fig. 1, the substrate 100 includes: a silicon substrate 110, and a buried oxide layer 120 formed on the silicon substrate 110, the device layer being formed on the buried oxide layer 120.
Specifically, the buried oxide layer 120 may be made of silicon oxide.
In some embodiments of the present disclosure, the end-face coupler 220 may be an inverted cone end-face coupler or a cantilever beam type end-face coupler. When 220 is a cantilever-type end-face coupler, there will be a cantilever window as shown in FIG. 2 for etching the substrate.
In some embodiments of the present disclosure, the above optical device testing structure may further include: an upper cladding layer 300 formed on the device layer, as shown in FIG. 3. FIG. 3 illustrates a side view of another optical device testing structure provided by the present disclosure.
Specifically, the upper cladding layer 300 may be made of silicon oxide, which is the same as the material used for the buried oxide layer 120.
On the basis of the structure shown in fig. 3, after a wafer test, deep groove etching and scribing are performed from the area a, the grating coupler is removed by the way, and an etched end face of the end face coupler is formed, wherein the width of the scribing deep groove is 100-200 um, and the depth is about 100um, as shown in fig. 4. The remaining end-couplers may be used for chip-package coupling.
This disclosure compares advantage with prior art and lies in:
the optical device testing structure provided by the disclosure combines the advantages of the end face coupler and the grating coupler, can be used for coupling testing at any time in the wafer preparation process through the grating coupler, and is convenient for monitoring the performance of an optical device at any time; because the grating coupler is positioned in the area of the scribing deep groove to be manufactured, when the wafer is prepared and scribed into a chip, the grating coupler is removed incidentally, and the chip is packaged through the end face coupler, so that the volume after packaging is small. Therefore, the optical device testing structure provided by the disclosure can simultaneously solve the wafer level testing and chip packaging problems of the optical chip.
The present disclosure also provides a method for manufacturing an optical device test structure, the method is used for manufacturing the optical device test structure, and includes the following steps:
providing a substrate comprising: the buried oxide layer is formed on the silicon substrate;
forming a device layer on the buried oxide layer, wherein the device layer comprises an optical device, an end face coupler and a grating coupler, as shown in FIG. 1; in particular, the device layer can be fabricated by using a related photolithography process.
Wherein the optical device is connected with the end face coupler through an optical waveguide; the end face coupler is coupled with the grating coupler, and the grating coupler is positioned in a region on the substrate where a scribing deep groove is to be manufactured;
forming an upper cladding layer on the device layer, as shown in FIG. 3; in particular, the upper cladding layer may be formed by depositing silicon oxide on the device layer in association with a deposition process.
And etching the scribing deep groove in the region to be manufactured with the scribing deep groove on the substrate, sequentially etching the upper cladding layer, the grating coupler and the oxygen burying layer in the region, and etching the silicon substrate with a preset depth to form the structure shown in fig. 4.
Specifically, the deep trench etching is to form a smooth sidewall of the end-face coupler, and a certain depth is required to be greater than the radius of the optical fiber, so that the optical fiber can be coupled to the smooth sidewall of the end-face coupler. Therefore, the silicon substrate also needs to be etched away to a certain depth (the predetermined depth mentioned above), which is usually 100um-150 um.
In some embodiments of the present disclosure, the endface coupler is an inverted tapered endface coupler or a cantilevered beam endface coupler.
When the end-face coupler is a cantilever-type end-face coupler, a cantilever release window as shown in fig. 2 is fabricated for etching the substrate when the cantilever-type end-face coupler is fabricated.
FIG. 5 is a front view of the cantilever release window along line ab; as shown in fig. 6, which is a front view along line ab after the cantilever silicon substrate is etched, the present disclosure does not limit the shape of the trench at the bottom of the cantilever, including but not limited to a typical trench with a bottom in a sphere-like shape; figure 7 is a front view of the cantilevered silicon substrate after further etching along line ab. The etching can be performed by a relevant method, and the method is not limited by the disclosure.
This disclosure compares advantage with prior art and lies in:
the optical device testing structure provided by the disclosure combines the advantages of the end face coupler and the grating coupler, can be used for coupling testing at any time in the wafer preparation process through the grating coupler, and is convenient for monitoring the performance of an optical device at any time; because the grating coupler is positioned in the area of the scribing deep groove to be manufactured, when the wafer is prepared and scribed into a chip, the grating coupler is removed incidentally, and the chip is packaged through the end face coupler, so that the volume after packaging is small. Therefore, the optical device testing structure provided by the disclosure can simultaneously solve the wafer level testing and chip packaging problems of the optical chip.
One skilled in the art can also devise methods that are not exactly the same as those described above in order to form the same structure. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (8)
1. An optical device testing structure, comprising:
a substrate; and
a device layer formed on the substrate, the device layer including an optical device, an end-face coupler, and a grating coupler;
wherein the optical device is connected with the end face coupler through an optical waveguide; the end face coupler is coupled with the grating coupler, and the grating coupler is located in a region of the substrate where a scribing deep groove is to be manufactured.
2. The optical device test structure of claim 1, wherein the endface coupler is an inverted tapered endface coupler or a cantilevered endface coupler.
3. The optical device test structure of claim 1, wherein the substrate comprises: the device comprises a silicon substrate and a buried oxide layer formed on the silicon substrate, wherein the device layer is formed on the buried oxide layer.
4. The optical device test structure of claim 3, wherein the buried oxide layer is made of silicon oxide.
5. The optical device test structure of claim 1, further comprising: an upper cladding layer formed on the device layer.
6. The optical device test structure of claim 5, wherein the upper cladding layer is made of silicon oxide.
7. A method of fabricating an optical device test structure, comprising:
providing a substrate comprising: the buried oxide layer is formed on the silicon substrate;
forming a device layer on the buried oxide layer, wherein the device layer comprises an optical device, an end face coupler and a grating coupler; wherein the optical device is connected with the end face coupler through an optical waveguide; the end face coupler is coupled with the grating coupler, and the grating coupler is positioned in a region on the substrate where a scribing deep groove is to be manufactured;
forming an upper cladding layer on the device layer;
and etching the scribing deep groove in the region to be manufactured with the scribing deep groove on the substrate, sequentially etching the upper cladding, the grating coupler and the oxygen burying layer in the region, and etching the silicon substrate with the preset depth.
8. The method of claim 7, wherein the endface coupler is an inverted tapered endface coupler or a cantilevered endface coupler.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110189580.3A CN113009624A (en) | 2021-02-19 | 2021-02-19 | Optical device test structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110189580.3A CN113009624A (en) | 2021-02-19 | 2021-02-19 | Optical device test structure and manufacturing method thereof |
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| CN113009624A true CN113009624A (en) | 2021-06-22 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115842241A (en) * | 2022-12-23 | 2023-03-24 | 上海铭锟半导体有限公司 | Waveguide grating antenna based on evanescent wave regulation and control and manufacturing method |
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| US20180313718A1 (en) * | 2017-04-28 | 2018-11-01 | Cisco Technology, Inc. | Wafer level optical probing structures for silicon photonics |
| US20200033533A1 (en) * | 2018-07-24 | 2020-01-30 | Elenion Technologies, Llc | On-wafer testing of photonic chips |
| CN110941045A (en) * | 2018-05-18 | 2020-03-31 | 博创科技股份有限公司 | Optical wafer and chip with reflector function for wafer level test |
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2021
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|---|---|---|---|---|
| US9459177B1 (en) * | 2015-05-15 | 2016-10-04 | Alcatel Lucent | Wafer-level testing of optical circuit devices |
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| US20180313718A1 (en) * | 2017-04-28 | 2018-11-01 | Cisco Technology, Inc. | Wafer level optical probing structures for silicon photonics |
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| CN115842241A (en) * | 2022-12-23 | 2023-03-24 | 上海铭锟半导体有限公司 | Waveguide grating antenna based on evanescent wave regulation and control and manufacturing method |
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Application publication date: 20210622 |