CN112992254B - 刷新测试电路及方法 - Google Patents
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Abstract
本发明提供一种刷新测试电路及方法。刷新测试电路包括内部时钟产生器、计数器以及地址检测电路。内部时钟产生器传送控制时钟信号至刷新控制器,以产生用于刷新动作的存储库选择信号以及行地址信号。计数器对存储库选择信号的变动进行计数,以产生计数值。地址检测电路检测在刷新动作中行地址信号的值是否依序增加,以产生检测信号。
Description
技术领域
本发明涉及一种内存测试装置,尤其涉及一种刷新测试电路及方法。
背景技术
在动态随机存取内存(Dynamic Random Access Memory,DRAM)中,由于会有电荷损失(charge loss),需要定期对存储存储库进行刷新动作以补充新的电荷。动态随机存取内存例如可通过刷新控制器来逐次提供所有要进行刷新的行地址。因此,在内存的生产流程中必须要测试刷新控制器是否正常运行,以确保每个生产出来的内存都可正常执行刷新功能。
在现有技术中,当要测试刷新功能时,可从外部写入新的数据来进行刷新,以检测刷新后的数据是否正确。然而,在进行上述测试时,通常会禁止由内部触发预充电动作,以得到足够的时间进行写入操作。因此,需要由一些其他控制电路来触发预充电动作。与正常的刷新动作相比,控制时序会改变,耗费的时间也较长。
发明内容
本发明提供一种刷新测试电路及方法,可由额外设置的电路来对刷新控制器所提供的刷新用信号进行检测,以在不改变原本控制时序的情况下,进行刷新功能的测试。
本发明的刷新测试电路包括内部时钟产生器、计数器以及地址检测电路。内部时钟产生器传送控制时钟信号至刷新控制器,以产生用于刷新动作的存储库选择信号以及行地址信号。计数器耦接刷新控制器。计数器对存储库选择信号的变动进行计数,以产生计数值。地址检测电路耦接刷新控制器以及计数器。地址检测电路检测在刷新动作中行地址信号的值是否依序增加,以产生检测信号。
在本发明的一实施例中,上述的地址检测电路包括比较器、与门以及正反器。比较器的第一输入端接收计数值,第二输入端耦接行地址信号,并且对计数值及行地址信号的值进行比较,以在其输出端输出比较信号。与门的第一输入端耦接比较信号。正反器的输入端耦接与门的输出端,控制端耦接存储库选择信号,输出端耦接与门的第二输入端,并且输出检测信号。
本发明的刷新测试方法包括:传送控制时钟信号至刷新控制器,以产生用于刷新动作的存储库选择信号以及行地址信号;对存储库选择信号的变动进行计数,以产生计数值;以及,检测在刷新动作中行地址信号的值是否依序增加,以产生检测信号。
基于上述,本发明的刷新测试电路可由计数器以及地址检测电路来对存储库的刷新动作次数以及进行刷新动作的地址进行检测。由此,可在不改变原本控制时序的情况下,以较短的时间完成刷新功能的测试。
附图说明
图1是依照本发明一实施例的一种刷新测试电路的电路示意图;
图2是依照本发明一实施例的一种地址检测电路的电路示意图;
图3A及图3B是依照本发明一实施例的一种刷新测试的波形示意图;
图4是依照本发明另一实施例的一种地址检测电路的电路示意图;
图5是依照本发明一实施例说明一种刷新测试方法的流程图。
具体实施方式
现将详细地参考本发明的示范性实施例,示范性实施例的实例说明于附图中。只要有可能,相同组件符号在附图和描述中用来表示相同或相似部分。
以下请参照图1,图1是依照本发明一实施例的一种刷新测试电路的电路示意图。刷新测试电路100例如内建在动态随机存取内存(Dynamic Random Access Memory,DRAM)中,以对其刷新功能进行测试。如图1所示,刷新测试电路100包括计数器120、地址检测电路130以及内部时钟产生器140。在本实施例中,刷新测试电路100用以对刷新控制器110所产生的信号进行测试。
举例来说,当内建有刷新测试电路100的动态随机存取内存要进行刷新动作时,刷新控制器110可接收到刷新请求信号RQ,并且依据刷新请求信号RQ产生用于刷新动作的存储库选择信号BNKSEL以及行地址信号RADD。当特定的存储库被选取执行刷新时,刷新控制器110可致能对应的存储库选择信号BNKSEL(例如上升至高逻辑电平),并且输出行地址信号RADD以指定所要刷新的地址。在本实施例中,刷新控制器110例如是利用多个逻辑闸所组成的逻辑电路,但本发明并不以此为限。
内部时钟产生器140耦接刷新控制器110。内部时钟产生器140可传送控制时钟信号ICLK至刷新控制器110,以产生用于刷新动作的存储库选择信号BNKSEL以及行地址信号RADD。由此,刷新控制器110可接收控制时钟信号ICLK,并且反应于控制时钟信号ICLK来产生每个存储库选择信号BNKSEL以及行地址信号RADD。
计数器120耦接刷新控制器110。计数器120可对存储库选择信号BNKSEL的变动进行计数,以产生计数值COUNT。举例来说,当存储库选择信号BNKSEL从低逻辑电平上升至高逻辑电平时,计数器120就会将计数值COUNT进行累加。
地址检测电路130耦接刷新控制器110以及计数器120。地址检测电路130可检测在刷新动作中行地址信号RADD的值是否依序增加,以产生检测信号TEST。具体来说,由于动态随机存取内存需要依序对每个地址进行刷新,刷新控制器110可对应地依序增加行地址信号RADD的值。地址检测电路130则可以检测刷新控制器110是否有输出正确的行地址信号RADD,并且输出对应的检测信号TEST。
举例来说,图2是依照本发明一实施例的一种地址检测电路的电路示意图。在本实施例中,地址检测电路130包括比较器210、与门220以及正反器230。比较器210的第一输入端接收计数值COUNT,比较器210的第二输入端耦接行地址信号RADD。比较器210可对计数值COUNT及行地址信号RADD的值进行比较,以在其输出端输出比较信号CMP1。在本实施例中,当计数值COUNT等于行地址信号RADD的值时,比较器210输出逻辑1(高逻辑电平)的比较信号CMP1。当计数值COUNT不等于行地址信号RADD的值时,比较器210输出逻辑0(低逻辑电平)的比较信号CMP1。
与门220的第一输入端耦接比较信号CMP1。正反器230的输入端耦接与门220的输出端。正反器230的控制端耦接存储库选择信号BNKSEL。由此,正反器230可依据存储库选择信号BNKSEL而对与门220的输出值进行储存,并且作为检测信号TEST进行输出。
此外,正反器230的输出端耦接与门220的第二输入端。所输出的检测信号TEST初始值为逻辑1(高逻辑电平)。基于上述结构,一旦比较器210所输出的比较信号CMP1变为逻辑0(低逻辑电平)时,正反器230所输出的检测信号TEST就会变为逻辑0(低逻辑电平)。并且,由于检测信号TEST会回授到与门220的关系,逻辑0(低逻辑电平)的检测信号TEST会持续到测试结束,以通知使用者发生测试错误。
由此,使用者可依据计数值COUNT来判断对存储库的刷新动作次数是否正确,并且依据检测信号TEST来判断每次进行刷新动作的地址是否正确,以进行刷新功能的测试。
由于在本实施例中不需要进行额外的写入动作或读出动作,且可正常地由内部触发预充电动作,在进行刷新测试时并不需要改变原来正常刷新动作的控制时序。此外,由于测试中不涉及内存阵列,测试时控制时钟信号ICLK可以比一般的刷新动作运行地更快。举例来说,内部时钟产生器140可以是双频(dual-frequency)的并且可以产生双频时钟(dual-frequency clock)。因此,当内部时钟产生器140输出更快的时钟时,刷新控制器110能够以更快的时钟频率运行,就可以在短时间内完成刷新测试。
图3A及图3B是依照本发明一实施例的一种刷新测试的波形示意图。以下对本案适用于动态随机存取内存的刷新测试方法进行说明,请同时参照图1、图2、图3A及图3B。
图3A所示的波形例如是刷新功能正常运作时的波形。在图3A中,当刷新控制器110接收到用以请求进行刷新动作的刷新请求信号RQ时(即时间点TA1),刷新控制器110会产生存储库选择信号BNKSEL以及行地址信号RADD。具体来说,在时间点TA1时,刷新控制器110会开始选择要进行刷新的存储库并且切换存储库选择信号BNKSEL的逻辑电平。此外,在存储库选择信号BNKSEL的两个上升缘(rising edge)之间(例如时间点TA1与TA2之间),刷新控制器110会对行地址信号RADD的值进行累加,以对下一个地址进行刷新。
另一方面,每当存储库选择信号BNKSEL上升至高逻辑电平(例如时间点TA1)之后,计数器120就会对计数值COUNT进行累加,以计数进行刷新动作的次数。在本实施例中,为了方便说明,将行地址信号RADD以及计数值COUNT初始值皆设为0,但本发明并不以此为限。
本案的地址检测电路130可被存储库选择信号BNKSEL的上升缘所触发而开始进行检测。如图3A所示,在时间点TA1时,由于计数值COUNT以及行地址信号RADD的值皆为0,图2中的比较器210会输出逻辑1(高逻辑电平)的比较信号CMP1。此时,由于检测信号TEST的初始值为逻辑1,与门220的输出值能会保持为逻辑1。因此,在时间点TA1时,对与门220的输出值进行储存的正反器230会输出逻辑1(高逻辑电平)的检测信号TEST。以此类推,在图3A的时间点TA2、TA3、TA4及TA5时,计数值COUNT皆等于行地址信号RADD的值,因此检测信号TEST皆保持在逻辑1(高逻辑电平),以表示刷新功能通过测试。
图3B所示的波形例如是刷新控制器110输出错误的行地址信号RADD而导致刷新功能不正常时的波形。在图3B中,当刷新控制器110接收到用以请求进行刷新动作的刷新请求信号RQ时(即时间点TB1),刷新控制器110会产生存储库选择信号BNKSEL以及行地址信号RADD。具体来说,在时间点TB1时,刷新控制器110会开始选择要进行刷新的存储库并且切换存储库选择信号BNKSEL的逻辑电平。此外,在存储库选择信号BNKSEL的两个上升缘之间(例如时间点TB1与TB2之间),刷新控制器110会对行地址信号RADD的值进行累加,以对下一个地址进行刷新。
与图3A的波形不同的是,在时间点TB2与TB3之间,刷新控制器110将行地址信号RADD的值累加至异常值X1,而不是2。因此,在被时间点TB3时的存储库选择信号BNKSEL的上升缘所触发而开始进行检测的址检测电路130中,由于计数值COUNT不等于行地址信号RADD的值,比较器210所输出的比较信号CMP1为逻辑0(低逻辑电平)。图2中的比较器210会输出逻辑0(低逻辑电平)的比较信号CMP1,导致与门220的输出值变为逻辑0,正反器230所输出的检测信号TEST也就随之变为逻辑0(低逻辑电平),并且持续到测试结束,以通知使用者发生测试错误。
在图3B中,异常值X1~X4仅表示不与对应的计数值COUNT相等的行地址信号RADD的值,异常值Y1~Y4仅表示不与对应的行地址信号RADD的值相等的计数值COUNT,本发明并未对各异常值进行限定。
图4是依照本发明另一实施例的一种地址检测电路的电路示意图。在本实施例中,地址检测电路130A包括正反器410、比较器420、与门430以及正反器440。正反器410的输入端耦接当下行地址信号RADD_N,正反器410的控制端耦接存储库选择信号BNKSEL。
比较器420的第一输入端耦接当下行地址信号RADD_N,比较器420的第二输入端耦接正反器410的输出端。比较器420可对当下行地址信号RADD_N的值及正反器410所储存的先前(前一个)行地址信号RADD_N-1的值进行比较,以在其输出端输出比较信号CMP2。在本实施例中,在当下行地址信号RADD_N的值减去先前行地址信号RADD_N-1的值等于1时,比较器420输出逻辑1(高逻辑电平)的比较信号CMP2。在当下行地址信号RADD_N的值减去先前行地址信号RADD_N-1的值不等于1时,比较器420输出逻辑0(低逻辑电平)的比较信号CMP2。
与门430的第一输入端耦接比较信号CMP2。正反器440的输入端耦接与门430的输出端。正反器440的控制端耦接存储库选择信号BNKSEL。由此,正反器440可依据存储库选择信号BNKSEL而对与门430的输出值进行储存,并且作为检测信号TEST进行输出。
此外,正反器440的输出端耦接与门430的第二输入端,并且所输出的检测信号TEST初始值为逻辑1(高逻辑电平)。基于上述结构,一旦比较器420所输出的比较信号CMP2变为逻辑0(低逻辑电平)时,正反器440所输出的检测信号TEST就会变为逻辑0(低逻辑电平)。并且,由于检测信号TEST会回授到与门430的关系,逻辑0(低逻辑电平)的检测信号TEST会持续到测试结束,以通知使用者发生测试错误。
图5是依照本发明一实施例说明一种刷新测试方法的流程图。请参照图5,在本实施例中动态随机存取内存的刷新测试方法包括下列步骤。传送控制时钟信号至刷新控制器,以产生用于刷新动作的存储库选择信号以及行地址信号(步骤S510)。接着,对存储库选择信号的变动进行计数,以产生计数值(步骤S520)。最后,检测在刷新动作中行地址信号的值是否依序增加,以产生检测信号(步骤S530)。关于,上述步骤S510、S520及S530的实施细节在前述的实施例及实施方式都有详尽的说明,在此则不再赘述。
综上所述,本发明的刷新测试电路可由计数器以及地址检测电路来对存储库的刷新动作次数以及进行刷新动作的地址进行检测。据此,由于并未针对刷新测试进行额外的写入动作或读出动作,在进行刷新测试时并不需要改变原来正常刷新动作的控制时序,并且控制时钟信号可以比一般的刷新动作运行地更快,也能以较短的时间完成刷新测试。
最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。
Claims (5)
1.一种刷新测试电路,其特征在于,包括:
内部时钟产生器,传送控制时钟信号至刷新控制器,以产生用于刷新动作的存储库选择信号以及行地址信号;
计数器,耦接所述刷新控制器,对所述存储库选择信号的变动进行计数,以产生计数值;以及
地址检测电路,耦接所述刷新控制器以及所述计数器,检测在所述刷新动作中所述行地址信号的值是否依序增加,以产生检测信号,
其中,所述地址检测电路包括:
比较器,其第一输入端接收所述计数值,其第二输入端耦接所述行地址信号,对所述计数值及所述行地址信号的值进行比较,以在其输出端输出比较信号,其中所述地址检测电路依据所述比较信号产生所述检测信号。
2.根据权利要求1所述的刷新测试电路,其中所述内部时钟产生器是双频的。
3.根据权利要求1所述的刷新测试电路,其中所述地址检测电路还包括:
与门,其第一输入端耦接所述比较信号;以及
正反器,其输入端耦接所述与门的输出端,其控制端耦接所述存储库选择信号,其输出端耦接所述与门的第二输入端,并且输出所述检测信号。
4.一种刷新测试电路,其特征在于,包括:
内部时钟产生器,传送控制时钟信号至刷新控制器,以产生用于刷新动作的存储库选择信号以及行地址信号;
计数器,耦接所述刷新控制器,对所述存储库选择信号的变动进行计数,以产生计数值;以及
地址检测电路,耦接所述刷新控制器以及所述计数器,检测在所述刷新动作中所述行地址信号的值是否依序增加,以产生检测信号,
其中,所述地址检测电路包括:
第一正反器,其输入端耦接所述行地址信号,其控制端耦接所述存储库选择信号;
比较器,其第一输入端耦接所述行地址信号,其第二输入端耦接所述第一正反器的输出端,对当下所述行地址信号的值及所述第一正反器所储存的先前所述行地址信号的值进行比较,以在其输出端输出比较信号;
与门,其第一输入端耦接所述比较信号;以及
第二正反器,其输入端耦接所述与门的输出端,其控制端耦接所述存储库选择信号,其输出端耦接所述与门的第二输入端,并且输出所述检测信号。
5.一种刷新测试方法,其特征在于,包括:
传送控制时钟信号至刷新控制器,以产生用于刷新动作的存储库选择信号以及行地址信号;
对所述存储库选择信号的变动进行计数,以产生计数值;以及
检测在所述刷新动作中所述行地址信号的值是否依序增加,以产生检测信号,
其中,检测在所述刷新动作中所述行地址信号的值是否依序增加,以产生所述检测信号的步骤包括:
对所述计数值及所述行地址信号的值进行比较,以输出比较信号;
依据所述比较信号判断所述行地址信号的值是否依序增加,以产生所述检测信号;
对当下所述行地址信号的值及通过正反器所储存的先前所述行地址信号的值进行比较,以输出比较信号;以及
依据所述比较信号判断所述行地址信号的值是否依序增加,以产生所述检测信号。
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