CN112968691A - Pulse time delay precision self-adaptive synchronization method - Google Patents
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Abstract
The invention provides a pulse delay precision self-adaptive synchronization method, and aims to provide a self-adaptive synchronization delay method with high synchronization precision, good reliability and low error rate. The invention is realized by the following scheme: the method comprises the steps that external periodic input pulses P0 of a digital circuit system pass through an FPGA built-in adjustable delayer to obtain clock CLK sampling signals P1, and sampling signals P1 pass through a register to obtain pulse signals P2; and simultaneously, a clock CLK of an external digital circuit system is used for driving a timing pulse generator to generate a pulse signal P3 which is generated by local counting and has the same frequency with the external periodic pulse signal, a time delay comparator is used for calculating the time delay difference N of the rising edges of the pulse signal P2 and the pulse signal P3, a time delay judgment strategy model is used for carrying out combined calculation according to a plurality of search periods to obtain a time delay control quantity N0 of the digital difference N, so that a time delay correction quantity M is obtained, and an internal pulse signal which is stably synchronous with the external pulse signal is obtained.
Description
Technical Field
The invention relates to a synchronous FPGA pulse time delay method in the technical field of array digital signal processing.
Background
Array signal processing is an important branch in the field of signal processing, and along with the development of technology, the array signal processing develops towards full digitalization, and an advanced Digital Beam Forming (DBF) technology is adopted to realize the shaping of a transmitting beam so as to reduce the probability of interception of the transmitting signal. And digital sampling is directly adopted in the channel array elements or digital sampling is carried out after analog synthesis among local array elements, next step of synthesis processing is carried out, and the diversity of array application functions can be realized by utilizing the stability and flexibility of a digital system. In large-scale array signal processing, digital processing circuits are distributed in various modules at different positions, synchronous sampling is required among the modules, namely the digital processing circuits are distributed in different modules and are processed by using the same time reference. In a digital system, a mode of distributing periodic synchronous pulses to each digital processing module is generally adopted, so that synchronous processing among the modules needs to accurately identify a processing clock period corresponding to the synchronous pulses according to a processing clock, but due to engineering reasons, time delay of pulse signals distributed to each digital processing module is slightly different, and when the processing clock of the digital module is higher, a pulse signal rising edge is close to a digital clock edge at a high rate, so that a metastable state is caused. The meta-stability may cause inconsistency in the identification of the rising edge of the pulse signal among the digital blocks, thereby causing synchronization failure among the blocks, that is, different digital blocks sample the transition of the pulse signal at different rising edges of CLK.
In a distributed digital synchronous processing system, the delay performance of synchronous pulse transmission for synchronization among digital circuits is an important index in the system, and the performance of the system is directly influenced by the performance of delay difference, delay jitter and the like. The phased array system requires phase coherent to be realized in each array element, thereby effectively forming the antenna directivity. Modern array processing signal bandwidth is wider and wider, clocks of digital processing circuits are higher and higher, and requirements on synchronous distribution precision of synchronous pulse signals are higher and higher.
Synchronization of all modules of each subarray of the distributed phased array is achieved through a common clock signal. For the distributed phased array, it is very complicated to implement signal coherent and synchronization between the receiving and transmitting units at far distance, which requires a high-precision synchronous clock source. The distributed control system clock is realized by using counters, and whether 2 standards exist in synchronization of the 2 clocks is judged, wherein the standards include whether the numerical values of the counters are equal, and whether the increasing speeds of the numerical values of the counters are equal. According to IEEE1588, to synchronize the slave clock to the master clock, the offset between the slave clock and the master clock is first determined, this offset is calculated from the offset between the transmission timestamp and the reception timestamp of the packet, and its accuracy is affected by 2 factors, namely the uncertainty of the delay time of the data transmission and the accuracy of the timestamp itself. Because the clock delay has only two choices, the precise matching of the phase can not be realized, and the requirement of some ultra-high speed circuits is difficult to adapt. The self-adaptive synchronizer can predict the phase relation between the sampling clock and the input data, self-adaptively select the steady-state sampling result and reduce the probability of the metastable state. Although the data delay synchronizer can realize accurate delay of data, the latch of ultra-high speed data or DDR data is realized. However, due to the use of a large number of delay units, the complexity of FPGA design is increased, and implementation is difficult. The FPGA can acquire data such as frequency, duty ratio, amplitude, rise time and the like of a pulse signal at a high speed, and a D trigger is generally adopted in the FPGA to realize sampling of input data. In order to avoid a metastable state, the D flip-flop requires that input data meet certain setup and hold times relative to a clock edge, that is, the input data and an internal clock of the FPGA meet a certain phase relationship. The rising edge of a pulse signal can be resolved only by taking the clock CLK period as stepping, so that the resolution of the clock CLK decimal cycle time delay is realized. Due to uncertainty of relative phases of input data and a sampling clock, the establishing and holding time of a D trigger in the FPGA can not be met, and a metastable state occurs. However, in the high-speed data acquisition system based on the FPGA in which the internal clock and the external clock adopt the same clock source, the relative phase relationship between the input data of the FPGA and the internal clock of the FPGA is uncertain due to the routing delay, the device delay, and the input pin delay of the FPGA, which results in the significant increase of the influence of the precision of the timestamp on the synchronization precision.
Disclosure of Invention
The invention aims to provide a high-precision pulse delay precision self-adaptive synchronization method with high synchronization precision, good reliability, low error rate and high precision aiming at the synchronization requirement of a distributed digital module of the existing large conformal phased array system, so as to solve the problems of long delay and poor data consistency of the existing synchronization method and effectively improve the stability of the distributed system.
The above object of the present invention can be achieved by the following means. A pulse time delay precision self-adaptive synchronization method has the following technical characteristics: the method comprises the steps that external periodic input pulses P0 of a digital circuit system pass through an FPGA built-in adjustable delayer to obtain clock CLK sampling signals P1, and sampling signals P1 pass through a register to obtain pulse signals P2; meanwhile, the FPGA drives a timing pulse generator by using an external digital circuit system clock CLK, generates a pulse signal P3 which is generated by local counting and has the same frequency with an external periodic pulse signal, sends the pulse signal P3 to a time comparator for comparison, calculates the time delay difference N of the rising edges of the pulse signal P2 and the pulse signal P3, sends the obtained digital clock difference N to a time delay judgment strategy module for time delay correction, sets a time delay value DT by the time delay judgment strategy module, and feeds the set time delay value DT back to the adjustable delayer to obtain a corresponding digital difference value N; the delay judgment strategy module controls a delay value DT to adjust the delay amount of the adjustable delayer, an adjusting delay unit is smaller than the CLK clock period and is divided into two paths, one path passes through a pulse delay adjustment module, the other path is sent into a time comparator, time delay difference values N of P2 and P3 are compared and output to a delay judgment strategy module to perform time-sharing strategy delay judgment, fine delay difference between a sampling signal P1 and a pulse signal P3 is calculated, delay control quantity N0 of a digital difference value N is obtained according to searching of a plurality of search periods and is subjected to combined calculation to obtain a delay correction quantity M, interval searching and delay screening judgment are completed, a pulse delay adjustment circuit is controlled to adjust a pulse signal P3, and an internal pulse signal which is stably synchronous with an external pulse signal is obtained in a self-adaptive mode.
Compared with the prior art, the invention has the beneficial effects that:
the synchronization precision is high. The invention aims at the problem of metastable state sampling which can occur when an external periodic pulse signal is directly sampled by an external input clock CLK. An external periodic pulse signal P0 is input into an FPGA through a field programmable gate array FPGA pin, a sampling signal P1 is output through an adjustable time delay device and is sent into a register, an internal pulse signal P2 is obtained according to an external input clock CLK of a digital circuit system and is sent into a time comparator, a timing pulse generator is driven by the external CLK of the digital circuit system inside the FPGA to generate a pulse signal P3 with the same frequency as the external periodic pulse signal and is divided into two paths, stable and reliable synchronization is achieved by using a periodic pulse reference signal, the resolution of decimal period time delay of the clock CLK is achieved, the resolution precision of the FPGA circuit to the rising edge of the pulse signal is remarkably improved, and the defect that the rising edge of the pulse signal can be resolved only by taking the clock CLK period as stepping is overcome.
The reliability is good. The method comprises the steps of sending a time comparator to compare and output N digital difference values N to a time delay judgment strategy module for time delay judgment, calculating the digital difference value N of the rising edge of a pulse signal P2 and a pulse signal P3, feeding back the obtained time delay value DT to an adjustable time delay unit, sequentially changing the time delay value DT to obtain a corresponding digital difference value N, comparing the interval of the numerical value change of the digital difference value N by the time comparator to obtain the time delay control range of the external periodic pulse signal stably sampled by a clock CLK and the numerical value N0 of the digital difference value N corresponding to the range, and remarkably improving the phenomenon of digital module asynchronization caused by the metastable state which possibly occurs when the rising edge of the external periodic pulse signal is close to the rising edge of the clock CLK. The problem of providing stable pulse output when carrying out rising edge continuous search to external pulse is effectively solved. In the process of obtaining N0 through the interval analysis of the numerical change and stability of the N value, multiple detection combined judgment is adopted, the continuous detection of the external periodic pulse signal can be realized under the condition of not influencing the continuous generation of the internal pulse signal P4, and when the state change of the external periodic pulse signal is detected, the state of the internal pulse signal P4 can be adjusted in time. When the external periodic pulse signal disappears, the internal pulse signal P4 can be continuously generated in each digital module, so that the synchronization state among the digital modules is maintained. To resolve the possibility of false pulse acquisition due to glitches.
The error rate is low. The time delay judgment strategy module of the invention corrects according to the N0 value of the digital difference value N to obtain a time delay correction quantity M, and the pulse signal P3 is adjusted by the pulse time delay adjustment module to obtain an internal pulse signal which is stably synchronous with an external pulse signal, so that the error rate is low, the fault tolerance of the distributed digital system to the pulse signal can be obviously improved, and the normal synchronization between the digital modules can still be normally maintained when the pulse signal is burred or the pulse signal fails (effective first and then fails). The metastable state sampling problem which can occur when the external periodic pulse signal is directly sampled by the external input clock CLK is effectively solved.
The invention is suitable for the synchronization among the distributed digital circuit modules of the large-scale digital phased array system, and is also suitable for the field of other digital signal processing.
Drawings
FIG. 1 is a circuit schematic processing flow diagram of the adaptive synchronous FPGA pulse delay of the present invention.
Fig. 2 is a schematic diagram of the phase relationship of the input pulses P0 and CLK with respect to delay count and fine delay adjustment.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the present invention will be further described with reference to the accompanying drawings and embodiments. The technical scheme in the embodiment of the invention is clearly and completely described.
Detailed Description
See fig. 1. According to the invention, firstly, a clock CLK sampling signal P1 is obtained by an external periodic input pulse P0 of a digital circuit system through an FPGA built-in adjustable delayer, and a pulse signal P2 is obtained by sampling a sampling signal P1 through a register; meanwhile, the FPGA drives a timing pulse generator by using an external digital circuit system clock CLK, generates a pulse signal P3 which is generated by local counting and has the same frequency with an external periodic pulse signal, sends the pulse signal P3 to a time comparator for comparison, calculates the time delay difference N of the rising edges of the pulse signal P2 and the pulse signal P3, sends the obtained digital clock difference N to a time delay judgment strategy module for time delay correction, sets a time delay value DT by the time delay judgment strategy module, and feeds the set time delay value DT back to the adjustable delayer to obtain a corresponding digital difference value N; the delay judgment strategy module controls a delay value DT to adjust the delay amount of the adjustable delayer, an adjusting delay unit is smaller than the CLK clock period and is divided into two paths, one path passes through a pulse delay adjustment module, the other path is sent into a time comparator, time delay difference values N of P2 and P3 are compared and output to a delay judgment strategy module to perform time-sharing strategy delay judgment, fine delay difference between a sampling signal P1 and a pulse signal P3 is calculated, delay control quantity N0 of a digital difference value N is obtained according to searching of a plurality of search periods and is subjected to combined calculation to obtain a delay correction quantity M, interval searching and delay screening judgment are completed, a pulse delay adjustment circuit is controlled to adjust a pulse signal P3, and an internal pulse signal which is stably synchronous with an external pulse signal is obtained.
Inputting an external periodic input pulse P0 of a digital circuit system into an FPGA through a field programmable gate array FPGA pin, outputting a sampling signal P1 by a P0 through an adjustable time delayer, sending the signal into a register for sampling, obtaining an internal pulse signal P2 according to an external input clock CLK of the digital circuit system, sending the internal pulse signal into a time comparator, driving a timing pulse generator by the internal CLK of the FPGA through the external CLK of the digital circuit system to generate a pulse signal P3 with the same frequency as the external periodic pulse signal, carrying out combined calculation by a time delay judgment strategy module according to N0 values searched in a plurality of search periods to obtain a time delay correction quantity M, comparing an N0 value with N0 values searched for a plurality of times at each time by the combined calculation process, considering that the N0 value is valid at the time, adding or subtracting a constant according to the N0 to obtain an M value, and considering that the N0 may be error data if the N0 value is different, no M value calculation is performed.
In an optional embodiment, the adaptive synchronous FPGA pulse delay may be divided into three parts, a first part processes an input, the adaptive synchronous FPGA pulse delay is divided into three parts, the first part processes the input, a second part generates a pulse P3 by locally counting a digital circuit system clock CLK, and a third part completes an interval search and delay screening judgment function according to a delay judgment strategy.
In the first part for processing input, a digital circuit system external input pulse P0 obtains a sampling signal P1 through an adjustable delayer, and the sampling signal P1 obtains a pulse signal P2 after being sampled by a digital circuit system clock CLK;
in the second part, the digital circuit system sends a clock CLK local counting generation pulse P3 to a time delay comparator, calculates the CLK clock number of a pulse signal P2 and a pulse signal P3, and obtains the time delay difference n of the rising edge of the CLK clock;
in the third part, a time delay judgment strategy module time delay comparator block records a digital difference value N of a time delay difference N, controls a time delay value DT to adjust the delay amount of the adjustable delayer, searches for a range larger than 1 CLK period, adjusts a time delay unit to be smaller than a CLK clock period, completes interval search and time delay screening judgment by using a time delay judgment strategy, calculates a fine time delay difference between a sampling signal P1 and a pulse signal P3, and controls a pulse time delay adjustment circuit to adjust the pulse signal P3 to obtain an output pulse signal P4 signal of self-adaptive synchronous FPGA pulse time delay.
And the time delay judgment strategy module sets the time delay control quantity DT to the adjustable time delayer, and obtains a corresponding digital difference value N when the time delay value DT is set once.
And the time delay judgment strategy module controls the time delay control quantity DT to search within a certain range by stepping a period which is not more than the CLK, and the search period is more than the period of the CLK according to the capacity of the adjustable delayer. After a search period, a delay control range within which the external periodic pulse signal of the digital circuit system is stably sampled by the clock CLK and a digital difference value N0 corresponding to the delay control range are obtained.
The delay judgment strategy module takes less than 1/5 CLK periods to more than 1 CLK period as a beneficial search range, controls the delay value DT to adjust the delay amount of the adjustable delayer, records the value N every time adjustment is carried out for 1 time, adjusts the delay unit to be less than the CLK clock period, accumulates the delay value DT for the unit of the adjustable delay unit one by one, and obtains the digital difference value N of the delay count of the delay value DT and fine delay adjustment data shown in figure 2 after the search range is carried out for one time.
The delay judgment strategy module can search limited round numbers or continuous search as required, after the search range of the delay judgment strategy module is completed, the interval of numerical value change and stability of the N value is analyzed, the stable N value is selected to determine a delay correction quantity M, the delay value DT is controlled again to perform a round of new search, the delay correction quantity M is determined jointly according to the digital difference value N of multiple rounds of search, an external periodic pulse signal of the delay control range which can be stably sampled by a clock CLK and an N value N0 corresponding to the range are obtained, and the pulse signal P3 is corrected by using the N0 value to obtain an internal pulse signal which is stably synchronous with the external pulse signal.
As shown in fig. 2, the delay judgment policy module calculates a digital difference N between rising edges of the pulse signal P2 and the pulse signal P3 every time the delay value DT of the controllable delay circuit is changed, sequentially changes DT to obtain a corresponding N, calculates a digital difference N between rising edges of the pulse signal P2 and the pulse signal P3 every time the delay value DT of the controllable delay circuit is changed, obtains a digital clock difference N between the pulses P2 and P3 by sequentially changing the delay value DT, and records a delay value DT corresponding to a time when the N jumps from the digital difference N to N +1 as a metastable state delay value DT 0. When the adjustable delayer is set to be the initial delay value DT0, and the register sampling signal P1 has a metastable state with sampling uncertainty, the phase relationship between the input pulse P0 and the CLK is different, and the initial delay value DT0 is different.
The abnormal digital difference value N caused by the reasons of the burrs of the input clock signal and the like is removed, so that the influence of accidental burrs is avoided. When the external input pulse signal of the digital circuit system disappears, the external input pulse-free signal can be determined according to the jump characteristic that the digital difference value N cannot be searched to N + 1; when the external pulse signal disappears, the delay correction amount M can be maintained so that the pulse signal P4 has a continuous output and is synchronized with the pulse before the external pulse signal disappears.
The embodiments described above are some, but not all embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
Claims (10)
1. A pulse time delay precision self-adaptive synchronization method has the following technical characteristics: the method comprises the steps that external periodic input pulses P0 of a digital circuit system pass through an FPGA built-in adjustable delayer to obtain clock CLK sampling signals P1, and sampling signals P1 pass through a register to obtain pulse signals P2; meanwhile, the FPGA drives a timing pulse generator by using an external digital circuit system clock CLK, generates a pulse signal P3 which is generated by local counting and has the same frequency with an external periodic pulse signal, sends the pulse signal P3 to a time comparator for comparison, calculates the time delay difference N of the rising edges of the pulse signal P2 and the pulse signal P3, sends the obtained digital clock difference N to a time delay judgment strategy module for time delay correction, sets a time delay value DT by the time delay judgment strategy module, and feeds the set time delay value DT back to the adjustable delayer to obtain a corresponding digital difference value N; the delay judgment strategy module controls a delay value DT to adjust the delay amount of the adjustable delayer, an adjusting delay unit is smaller than the CLK clock period and is divided into two paths, one path passes through a pulse delay adjustment module, the other path is sent into a time comparator, time delay difference values N of P2 and P3 are compared and output to a delay judgment strategy module to perform time-sharing strategy delay judgment, fine delay difference between a sampling signal P1 and a pulse signal P3 is calculated, delay control quantity N0 of a digital difference value N is obtained according to searching of a plurality of search periods and is subjected to combined calculation to obtain a delay correction quantity M, interval searching and delay screening judgment are completed, a pulse delay adjustment circuit is controlled to adjust a pulse signal P3, and an internal pulse signal which is stably synchronous with an external pulse signal is obtained in a self-adaptive mode.
2. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: the self-adaptive synchronous FPGA pulse time delay is divided into three parts, wherein the first part processes input, the second part generates a pulse P3 by locally counting a digital circuit system clock CLK, and the third part completes the functions of interval search and time delay screening judgment according to a time delay judgment strategy; in the first part for processing input, a digital circuit system external input pulse P0 obtains a sampling signal P1 through an adjustable delayer, and the sampling signal P1 obtains a pulse signal P2 after being sampled by a digital circuit system clock CLK; in the second part, the digital circuit system sends a clock CLK local counting generation pulse P3 to a time delay comparator, calculates the CLK clock number of a pulse signal P2 and a pulse signal P3, and obtains the time delay difference n of the rising edge of the CLK clock; in the third part, a time delay judgment strategy module time delay comparator block records a digital difference value N of a time delay difference N, controls a time delay value DT to adjust the delay amount of the adjustable delayer, searches for a period range larger than 1 CLK, adjusts a time delay unit to be smaller than a CLK clock period, and completes the functions of interval searching and time delay screening judgment by using a time delay judgment strategy.
3. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: the time delay judgment strategy module performs combined calculation to obtain a time delay correction quantity M according to N0 values searched in a plurality of search periods, wherein the process of the combined calculation is that every time a new N0 value is obtained, the N0 value of this time is compared with the N0 values searched for a plurality of times, if the N0 value is the same, the N0 value of this time is considered to be effective, a constant is added or subtracted according to N0 to obtain the M value, if the N0 is different, the N0 is possibly error data, and M value calculation is not performed.
4. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: the time delay judgment strategy module sets a time delay control quantity DT to the adjustable delayer, a corresponding digital difference value N is obtained by setting a time delay value DT once, searching is carried out within a certain range by stepping a period which is not more than CLK through controlling the time delay control quantity DT, the searching period is more than one period of CLK according to the capacity of the adjustable delayer, and a time delay control range of external periodic pulse signals of the digital circuit system which are stably sampled by the clock CLK and a numerical value N0 of the digital difference value N corresponding to the range are obtained through searching of one searching period.
5. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: and the time delay judgment strategy module takes 1/5 CLK periods to more than 1 CLK period as a beneficial search range, controls the time delay value DT to adjust the delay amount of the adjustable delayer, records the value N every time adjustment is carried out for 1 time, adjusts the time delay unit to be less than the CLK clock period, accumulates the time delay value DT on the time delay unit units one by one, and obtains the digital difference value N of the time delay count of the time delay value DT and fine time delay adjustment data after the search range is carried out for one time.
6. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: the delay judgment strategy module can search limited round numbers or continuous search as required, after the search range of the delay judgment strategy module is completed, the interval of numerical value change and stability of the N value is analyzed, the stable N value is selected to determine a delay correction quantity M, the delay value DT is controlled again to perform a round of new search, the delay correction quantity M is determined jointly according to the digital difference value N of multiple rounds of search, an external periodic pulse signal of the delay control range which can be stably sampled by a clock CLK and an N value N0 corresponding to the range are obtained, and the pulse signal P3 is corrected by using the N0 value to obtain an internal pulse signal which is stably synchronous with the external pulse signal.
7. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: the time delay judgment strategy module calculates the digital difference value N of the rising edges of the pulse signal P2 and the pulse signal P3 after changing the time delay value DT once, obtains the corresponding N, calculates the digital difference value N of the rising edges of the pulse signal P2 and the pulse signal P3 after changing the time delay value DT once, obtains the digital clock difference value N between the P2 and the P3 pulse by changing the time delay value DT value in sequence, and records the time delay value DT corresponding to the moment when the N value jumps from the digital difference value N to N +1 as the metastable state time delay value DT 0.
8. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: when the adjustable delayer is set to be the initial delay value DT0, and the register sampling signal P1 has a metastable state with sampling uncertainty, the phase relationship between the input pulse P0 and the CLK is different, and the initial delay value DT0 is different.
9. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: when the external input pulse signal of the digital circuit system disappears and the jump characteristic of the digital difference value N to N +1 cannot be searched, determining that the external input pulse-free signal exists, and keeping the time delay correction quantity M, so that the pulse signal P4 has continuous output and is synchronous with the pulse before the external pulse signal disappears.
10. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: when the external input pulse signal of the digital circuit system disappears, determining the external input pulse-free signal according to the jump characteristic that the digital difference value N cannot be searched to N + 1; when the external pulse signal disappears, the delay correction amount M is maintained so that the pulse signal P4 has a continuous output and is synchronized with the pulse before the external pulse signal disappears.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115243357A (en) * | 2022-07-15 | 2022-10-25 | 中国人民解放军国防科技大学 | RF-PWM signal delay error correction method and system |
| CN117155530A (en) * | 2023-09-19 | 2023-12-01 | 成都立思方信息技术有限公司 | Trigger synchronization precision improving method of cascade trigger system |
| CN117353463A (en) * | 2023-12-04 | 2024-01-05 | 广东电网有限责任公司中山供电局 | Synchronous sampling method and related device for multipath alternating current electric quantity |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL8502859A (en) * | 1985-10-21 | 1987-05-18 | Philips Nv | CIRCUIT SYSTEM WITH DATA RE-SYNCHRONIZATION. |
| GB2200774A (en) * | 1987-02-09 | 1988-08-10 | Teradyne Inc | Timing generators |
| US5828250A (en) * | 1994-09-06 | 1998-10-27 | Intel Corporation | Differential delay line clock generator with feedback phase control |
| US20060291537A1 (en) * | 1999-06-14 | 2006-12-28 | Time Domain Corporation | Time transfer utilizing ultra wideband signals |
| CN104411012A (en) * | 2014-12-05 | 2015-03-11 | 武汉虹信通信技术有限责任公司 | Method and system for measuring timing deviation between small cell and macro cell of LTE (long term evolution) system |
| CN106291619A (en) * | 2016-07-29 | 2017-01-04 | 中国人民解放军国防科学技术大学 | A kind of aeronautical satellite inter-satellite link wireless long-period spread spectrum code signal high-performance catching method |
| CN107733421A (en) * | 2016-11-18 | 2018-02-23 | 上海兆芯集成电路有限公司 | For the data synchronizing unit for being latched the asynchronous data signal relevant with clock signal |
| CN109886413A (en) * | 2019-01-21 | 2019-06-14 | 中国科学技术大学 | A kind of adaptive metastable FPGA array synchronous trigger method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101729063B (en) * | 2008-10-16 | 2012-05-30 | 北京兆易创新科技有限公司 | Delay phase locked loop circuit and method for adjusting output clock signal phase |
| CN109901119B (en) * | 2019-01-31 | 2023-06-02 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Radar pulse signal sampling jitter real-time elimination processing method |
-
2021
- 2021-02-10 CN CN202110183712.1A patent/CN112968691B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL8502859A (en) * | 1985-10-21 | 1987-05-18 | Philips Nv | CIRCUIT SYSTEM WITH DATA RE-SYNCHRONIZATION. |
| GB2200774A (en) * | 1987-02-09 | 1988-08-10 | Teradyne Inc | Timing generators |
| US5828250A (en) * | 1994-09-06 | 1998-10-27 | Intel Corporation | Differential delay line clock generator with feedback phase control |
| US20060291537A1 (en) * | 1999-06-14 | 2006-12-28 | Time Domain Corporation | Time transfer utilizing ultra wideband signals |
| CN104411012A (en) * | 2014-12-05 | 2015-03-11 | 武汉虹信通信技术有限责任公司 | Method and system for measuring timing deviation between small cell and macro cell of LTE (long term evolution) system |
| CN106291619A (en) * | 2016-07-29 | 2017-01-04 | 中国人民解放军国防科学技术大学 | A kind of aeronautical satellite inter-satellite link wireless long-period spread spectrum code signal high-performance catching method |
| CN107733421A (en) * | 2016-11-18 | 2018-02-23 | 上海兆芯集成电路有限公司 | For the data synchronizing unit for being latched the asynchronous data signal relevant with clock signal |
| CN109886413A (en) * | 2019-01-21 | 2019-06-14 | 中国科学技术大学 | A kind of adaptive metastable FPGA array synchronous trigger method |
Non-Patent Citations (2)
| Title |
|---|
| 杨寿佳等: "一种自适应高精度脉冲激光同步时域控制技术的研究", 《光学与光电技术》 * |
| 郑恒秋等: "卫星双向话音通道高精度时间同步***", 《时间频率学报》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115243357A (en) * | 2022-07-15 | 2022-10-25 | 中国人民解放军国防科技大学 | RF-PWM signal delay error correction method and system |
| CN115243357B (en) * | 2022-07-15 | 2023-08-18 | 中国人民解放军国防科技大学 | RF-PWM signal delay error correction method and system |
| CN117155530A (en) * | 2023-09-19 | 2023-12-01 | 成都立思方信息技术有限公司 | Trigger synchronization precision improving method of cascade trigger system |
| CN117353463A (en) * | 2023-12-04 | 2024-01-05 | 广东电网有限责任公司中山供电局 | Synchronous sampling method and related device for multipath alternating current electric quantity |
| CN117353463B (en) * | 2023-12-04 | 2024-03-19 | 广东电网有限责任公司中山供电局 | Synchronous sampling method and related device for multipath alternating current electric quantity |
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