CN105846939B - A kind of accurate System and method for for keeping multimode synchronous - Google Patents

A kind of accurate System and method for for keeping multimode synchronous Download PDF

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CN105846939B
CN105846939B CN201610173738.7A CN201610173738A CN105846939B CN 105846939 B CN105846939 B CN 105846939B CN 201610173738 A CN201610173738 A CN 201610173738A CN 105846939 B CN105846939 B CN 105846939B
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delay
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time
synchronous
clock
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CN105846939A (en
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马骁
王军
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Chengdu Bosiwei Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The invention discloses a kind of accurate System and method for for keeping multimode synchronous, its system includes sampling time delay device, synchronous frequency divider, chronometer time measuring unit and state control machine；Sampling time delay device is used to receive synchronized sampling clock and carries out delay process to synchronized sampling clock；Synchronous frequency divider is used to generate synchronization frequency division signal and synchronous triggering signal；Chronometer time measuring unit is used to generate Time delay measurement signal；State control machine is used for the transmission break-make for controlling synchronous frequency divider and time-base signal, and gives sampling time delay device according to Time delay measurement signal generation delay configuration signal output.It is precise and stable the invention provides a kind of accurate System and method for for keeping multimode synchronous, and synchronize and system worked well is not influenceed during adjustment, it is applied widely.

Description

A kind of accurate System and method for for keeping multimode synchronous
Technical field
The present invention relates to a kind of accurate System and method for for keeping multimode synchronous.
Background technology
Phased array is with mimo system, largely using medium-high frequency synchronization submodule block system, such as analog-digital converter（ADC）, number Weighted-voltage D/A converter（DAC）, programmable logic array（FPGA）Deng；General this kind of submodule is required for the time reference with systematic unity Signal possesses the phase relation of determination so that system can reconstruct receiving and transmitting signal.
As shown in figure 1, traditional technical scheme by sampled signal Fs and time-base signal Fb distinguish input sample delayer with When base delayer after, input synchronized sampler synchronizing processing, output determines the Fb_sync signals of phase relation with Fs； So as to which system time reference is converted into submodule internal synchronization benchmark to allow each scaling down processing in submodule inside can ensure that Without synchronous reset in the case of metastable state；Typically also auxiliary has foundation to keep detector to this kind of method simultaneously, is prolonged by adjusting two What slow device ensured time reference signal and synchronous sampling signal establishes the retention time in prescribed limit.
This kind of scheme has more defect such as：First, conventional method assume that system time reference signal is adopted with medium-high frequency Sample signal is homologous generation, and the delay of time-base signal and synchronous sampling signal is not in deviation in a big way；Conventional method pair Do not acted in synchronization system of the deviation in a synchronized sampling more than the cycle, and it is large-scale in（Such as tens to up to ten thousand Submodule）In synchronization system, larger delay distortion can not often avoid；
Second, conventional method needs to interrupt normal work when synchronizing adjustment, and this is in many continuous working systems In be unacceptable；System can only often reduce synchronous sampling signal frequency to adapt to conventional synchronization scheme, but pay Cost is reduction of the process bandwidth of system, adds the demand of radio frequency frequency conversion and filtering, systematic entirety is received restriction.
The content of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide it is a kind of it is accurate keep the synchronous system of multimode with Method, it is precise and stable, and synchronize adjustment during system worked well is not influenceed, it is applied widely.
The purpose of the present invention is achieved through the following technical solutions：A kind of accurate system for keeping multimode synchronous, Including sampling time delay device, synchronous frequency divider, chronometer time measuring unit and state control machine；
Described sampling time delay device is used to receive synchronized sampling clock Fs；Delay process life is carried out to synchronized sampling clock Fs Into the first delay clock Fs1；And enter line delay under the delay configuration signal delay_adjust of state control machine control and adjust It is whole, delay process is carried out to synchronized sampling clock Fs after delay adjustment, generates the second delay clock Fs2；
Described synchronous frequency divider is used for the delay clock of signal first for receiving time-base signal Fb and the generation of sampling time delay device Fs1, and according to signal generation the synchronization frequency division signal div_clk and synchronous triggering signal Fb_sync received；
Described chronometer time measuring unit is used to receive time-base signal Fb and synchronization frequency division signal div_clk, and generates Time delay measurement signal delay_value；
Described state control machine is used for the transmission break-make for controlling synchronous frequency divider and time-base signal, and according to Time delay measurement Signal delay_value generation delay configurations signal delay_adjust, which is exported, gives sampling time delay device；
Further, state control machine can generate enable signal Fb_int_en control synchronous frequency divider with when base believe Number transmission break-make.
Described state control machine can also carry out pre-configured to the system cycle of synchronous frequency divider.
A kind of accurate method for keeping multimode synchronous, including rough grade synchronizing step S1 and tracking adjustment step S2；
Described rough grade synchronizing step S1 includes following sub-step：
S11. by synchronized sampling clock Fs input sample delayers, the first delay clock Fs1 is generated；
S12. state control machine controls time-base signal Fb to be connected to the transmission channel of synchronous frequency divider；
S13. by time-base signal Fb and the first delay clock Fs1 input synchronous frequency dividers, synchronization frequency division signal is generated Div_clk and synchronous triggering signal Fb_sync；
S14. state control machine controls time-base signal Fb to be disconnected to the transmission channel of synchronous frequency divider, and time-base signal Fb is no longer Synchronous frequency divider is triggered to change；
Further, state control machine is connected Fb signals into synchronous frequency divider, shape by enabled Fb_int_en signals After state machine enables more than more than the 1 time-base signal Fb cycle of Fb_int_en signal times, Fb_int_en signals are closed, believe Fb Disconnection number is connected with synchronous frequency divider, time-base signal Fb no longer triggers synchronous frequency divider change, completes thick synchronous.
Described tracking adjustment step S2 includes following sub-step：
S21. by synchronization frequency division signal div_clk and time-base signal Fb input chronometer time measuring units, generation is delayed Measurement signal delay_value；
S22. by Time delay measurement signal delay_value input state control machines, state control machine is according to Time delay measurement Signal delay_value generation delay configuration signals delay_adjust；
S23. delay is configured into signal delay_adjust input sample delayers, according to delay configuration signal delay_ Adjust is adjusted to sampling time delay device, and synchronized sampling clock is entered at line delay using the sampling time delay device after adjustment Reason, obtains the second delay clock Fs2.
Before synchronization frequency division signal is generated, in addition to a synchronous frequency divider configuration step：State control machine is to synchronization The system cycle of frequency divider is configured, and it is maintained unified signal frequency with time-base signal Fb.
Further, before step S1, in addition to a basic data generation step：Outside global system generation is same Sampling clock Fs and time-base signal Fb is walked, and the synchronized sampling clock Fs of generation and time-base signal Fb are input to described one kind It is accurate to keep in the synchronous system of multimode.
Further, described chronometer time measuring unit（Also it is TDC）, can be used such as delay chain, oscillator counter Realized etc. technical scheme, the delay inside chronometer time measuring unit TDC test constantlies between div_clk and external timing Fb Value, obtains Time delay measurement signal delay_value, and state control machine generates corresponding according to Time delay measurement signal delay_value Delay configuration signal delay_adjust sampling time delay device is adjusted, with the sampling time delay device after adjustment to synchronously adopting Sample clock FS carries out delay process, obtains the second delay clock Fs2；Kept so as to allow between internal div_clk and outside Fb signals Determine phase relation.
Further, described a kind of accurate system for keeping multimode synchronous, can be operated in single, multiple and week Phase property time-base signal triggers pattern, it is multiple with frequency periodicity time-base signal pattern, chronometer time measuring unit TDC can be with Carry out multiple averaging and obtain higher synchronization accuracy.
The beneficial effects of the invention are as follows：（1）Synchronous method is divided into rough grade synchronously with two big steps of tracking adjustment, led to It is poor using the real time of the thick synchronous synchronization frequency division signal of chronometer time measuring unit TDC measurements and synchronous time-base signal to cross, Postpone finally by sample delay adjustment sampling clock to reach the effect of precise synchronization.
（2）Normal work need not be interrupted when synchronizing adjustment, it is not required that synchronous sampling signal frequency is reduced, It is precise and stable, it is applied widely.
Brief description of the drawings
Fig. 1 is traditional synchronous system architecture schematic diagram；
Fig. 2 is the system structure diagram of the present invention；
Fig. 3 is flow chart of the method for the present invention.
The input graph of a relation of synchronized sampling clock Fs and time-base signal Fb and submodule outside Fig. 4.
Fig. 5 is the internal structure schematic diagram of submodule.
Fig. 6 is the time diagram of embodiment one.
Embodiment
Technical scheme is described in further detail below in conjunction with the accompanying drawings, but protection scope of the present invention is not limited to It is as described below.
As shown in Fig. 2 a kind of accurate system for keeping multimode synchronous, including sampling time delay device, synchronous frequency divider, precision Time measuring unit and state control machine；
Described sampling time delay device is used to receive synchronized sampling clock Fs；Delay process life is carried out to synchronized sampling clock Fs Into the first delay clock Fs1；And enter line delay under the delay configuration signal delay_adjust of state control machine control and adjust It is whole, delay process is carried out to synchronized sampling clock Fs after delay adjustment, generates the second delay clock Fs2；
Described synchronous frequency divider is used for the delay clock of signal first for receiving time-base signal Fb and the generation of sampling time delay device Fs1, and according to signal generation the synchronization frequency division signal div_clk and synchronous triggering signal Fb_sync received；
Described chronometer time measuring unit is used to receive time-base signal Fb and synchronization frequency division signal div_clk, and generates Time delay measurement signal delay_value；
Described state control machine is used for the transmission break-make for controlling synchronous frequency divider and time-base signal, and according to Time delay measurement Signal delay_value generation delay configurations signal delay_adjust, which is exported, gives sampling time delay device；
Further, state control machine can generate control enable signal Fb_int_en come control synchronous frequency divider and when The transmission break-make of base signal.
Described state control machine can also carry out pre-configured to the system cycle of synchronous frequency divider.
As shown in figure 3, a kind of accurate method for keeping multimode synchronous, including rough grade synchronizing step S1 and tracking adjustment Step S2；
Described rough grade synchronizing step S1 includes following sub-step：
S11. by synchronized sampling clock Fs input sample delayers, the first delay clock Fs1 is generated；
S12. state control machine controls time-base signal Fb to be connected to the transmission channel of synchronous frequency divider；
S13. by time-base signal Fb and the first delay clock Fs1 input synchronous frequency dividers, synchronization frequency division signal is generated Div_clk and synchronous triggering signal Fb_sync；
S14. state control machine controls time-base signal Fb to be disconnected to the transmission channel of synchronous frequency divider, and time-base signal Fb is no longer Synchronous frequency divider is triggered to change；
Further, state control machine is connected Fb signals into synchronous frequency divider, shape by enabled Fb_int_en signals After state machine enables more than more than the 1 time-base signal Fb cycle of Fb_int_en signal times, Fb_int_en signals are closed, believe Fb Disconnection number is connected with synchronous frequency divider, time-base signal Fb no longer triggers synchronous frequency divider change, completes thick synchronous.
Described tracking adjustment step S2 includes following sub-step：
S21. by synchronization frequency division signal div_clk and time-base signal Fb input chronometer time measuring units, generation is delayed Measurement signal delay_value；
S22. by Time delay measurement signal delay_value input state control machines, state control machine is according to Time delay measurement Signal delay_value generation delay configuration signals delay_adjust；
First, sets target length of delay Ttarget, according to Time delay measurement signal delay_value and target delay value Difference between Ttarget judges whether to need the length of delay for adjusting sample delay, if Time delay measurement signal delay_ Value is less than target delay value Ttarget, and delay configuration signal delay_value numerical value is in sampling time delay device length of delay On the basis of increase, if Time delay measurement signal delay_value is more than target delay value Ttarget,（Value added or reduced value It is generally equal to difference）Delay configuration signal delay_value numerical value reduces on the basis of sampling time delay device length of delay.
S23. delay is configured into signal delay_adjust input sample delayers, according to delay configuration signal delay_ Adjust is adjusted to sampling time delay device, and synchronized sampling clock is entered at line delay using the sampling time delay device after adjustment Reason, obtains the second delay clock Fs2.
Before synchronization frequency division signal is generated, in addition to a synchronous frequency divider configuration step：State control machine is to synchronization The system cycle of frequency divider is configured, and it is maintained unified signal frequency with time-base signal Fb, so as to make its output Div_clk and time-base signal Fb can keep frequency it is unified.
Further, before step S1, in addition to a basic data generation step：Outside global system generation is same Sampling clock Fs and time-base signal Fb is walked, and the synchronized sampling clock Fs of generation and time-base signal Fb are input to described one kind It is accurate to keep in the synchronous system of multimode.
Further, described chronometer time measuring unit（Also it is TDC）, can be used such as delay chain, oscillator counter Realized etc. technical scheme, the delay inside chronometer time measuring unit TDC test constantlies between div_clk and external timing Fb Value, obtains Time delay measurement signal delay_value, and state control machine generates corresponding according to Time delay measurement signal delay_value Delay configuration signal delay_adjust sampling time delay device is adjusted, with the sampling time delay device after adjustment to synchronously adopting Sample clock FS carries out delay process, obtains the second delay clock Fs2；Kept so as to allow between internal div_clk and outside Fb signals Determine phase relation.
Further, described a kind of accurate system for keeping multimode synchronous, can be operated in single, multiple and week Phase property time-base signal triggers pattern, it is multiple with frequency periodicity time-base signal pattern, chronometer time measuring unit TDC can be with Carry out multiple averaging and obtain higher synchronization accuracy.
In a particular application, a kind of described accurate system for keeping multimode synchronous applies in multiple submodule, with Keep the synchronization between multiple submodule；As shown in figure 4, outside the generation synchronized sampling clock Fs and time-base signal of submodule Fb, and synchronized sampling clock Fs and time-base signal Fb are separately input in each submodule.
As shown in figure 5, include a kind of described accurate system and son for keeping multimode synchronization inside each submodule Module clock domain, the second delay clock Fs2 and synchronization as caused by a kind of synchronous system of described accurate holding multimode Trigger signal Fb_sync is transferred to the clock zone of submodule.The clock zone of submodule refers to being used as synchronised clock using Fs2 Synchronous circuit region, all trigger signals in the region are Fb_sync, have the synchronized relation determined with Fs2, general Submodule clock zone includes the electricity that digital analog converter, analog-digital converter and FPGA etc. have the requirement of intermodule deterministic delays Road.
Embodiment one, as shown in Figure 6, it is assumed that have two submodules, respectively module 1 and module 2, module in practical application 1 postpones with sampling clock of the module 2 with Tmis；Respective synchronous frequency divider has Tckq1 and the respective clocks of Tckq2 to data Delay（Tckq1 and Tckq2 is in several ps units between several ns units）；When time-base signal Fb rising edges reach, module 1 Correct sampling, module 2 undergo metastable state sampling and used, and its internal div_clk is just exported after Tmis+N*fs_cycle；Wherein, its Middle Tmis is in several ps units between several ns units, and for N between 1 ~ 2, fs_cycle is the sample clock frequency cycle；Touch After sending out synchronous frequency divider reset, rough grade synchronizing step terminates.
From fig. 6 it can be seen that after rough grade synchronizing step terminates, the inside frequency-dividing clock div_ of two submodules Clk does not align；But a TDC measurable ranges section has been unified to, now, tracking adjustment step starts, TDC Trigger using time-base signal Fb rising edges along as opening flag, triggered using internal div_clk signals as end mark, by respectively Respective delay numerical value delay_value is exported, as shown in Figure 6：
The delay_value of module 1 is now equal to Tsetup+Tckq1；Tsetup is relative with the sampling clock of module 1 Fb settling times, in several ps units between several ns units；
The delay_vlaue of module 2 is now equal to Tsetup+Tmis+Tckq2+N*fs_cycle；
The delay_value input state control machines that each submodule is calculated；
For two submodule unified definitions, one standard delay amount Ttarget, the state control machine in each submodule thinks When measuring length of delay in each submodule TDC and being equal to Ttarget, or during positioned at some tolerable scope, each submodule reaches same Step requires；
State control machine in module 1, which is calculated to Ttarget-Tsetup-Tckq1, obtains retardation（That is delay_ adjust）, and the delay sampler in input module 1, it is adjusted；
State control machine in module 2, which calculates, arrives Ttarget-Tsetup-Tmis-Tckq2-N*fs_cycle Obtain retardation（That is delay_adjust）, and the delay sampler being input in module 2, it is adjusted；So as to obtain Precise synchronization sampled signal and internal div_clk fractional frequency signals.
System can be operated in single, multiple and periodicity time-base signal triggering pattern, in multiple and same frequency periodicity Under time-base signal pattern, TDC measurements can carry out multiple averaging and obtain higher synchronization accuracy.
Because system use may span across the TDC of period measurement, sampling clock delayer can offset sampling clock integer simultaneously Circular error and Tmis sampling clock distribution errors；Anti- burr further can be used（Deglitch）Sample delay obtains dynamic Continuously adjustable ability.
Because each submodule uses the Ttarget of systemic presupposition, it is adjusted with reference to TDC current measurement values, Shi Jixin Number overall drift the relative synchronization relation each submodule of the system is not influenceed, be applicable to time-base signal Fb itself System of the delay with larger drift；Only needs are reserved sufficiently large in setting Ttarget values divider ratios corresponding with div_clk Redundant space with include metastable state may caused by delay skew with the issuable maximum drifts of time-base signal Fb itself i.e. Can.

Claims (4)

  1. A kind of 1. accurate system for keeping multimode synchronous, it is characterised in that：Including sampling time delay device, synchronous frequency divider, precision Time measuring unit and state control machine；
    Described sampling time delay device is used to receive synchronized sampling clock Fs；Delay process generation the is carried out to synchronized sampling clock Fs One delay clock Fs1；And enter line delay adjustment under the delay configuration signal delay_adjust of state control machine control, prolong When adjustment after to synchronized sampling clock Fs carry out delay process, generate the second delay clock Fs2；
    Described synchronous frequency divider is used for signal the first delay clock Fs1 for receiving time-base signal Fb and the generation of sampling time delay device, And according to signal generation the synchronization frequency division signal div_clk and synchronous triggering signal Fb_sync received；
    Described chronometer time measuring unit is used to receive time-base signal Fb and synchronization frequency division signal div_clk, and generates delay Measurement signal delay_value；
    Described state control machine is used to controlling the transmission break-make of synchronous frequency divider and time-base signal, and by Time delay measurement signal Delay_value input state control machines, according to Time delay measurement signal delay_value and standard delay amount Ttarget, calculate Generation delay configuration signal delay_adjust, which is exported, gives sampling time delay device.
  2. A kind of 2. accurate system for keeping multimode synchronous according to claim 1, it is characterised in that：Described state control Machine processed can also carry out pre-configured to the system cycle of synchronous frequency divider.
  3. A kind of 3. accurate method for keeping multimode synchronous, it is characterised in that：Including rough grade synchronizing step S1 and tracking adjustment Step S2；
    Described rough grade synchronizing step S1 includes following sub-step：
    S11. by synchronized sampling clock Fs input sample delayers, the first delay clock Fs1 is generated；
    S12. state control machine controls time-base signal Fb to be connected to the transmission channel of synchronous frequency divider；
    S13. by time-base signal Fb and the first delay clock Fs1 input synchronous frequency dividers, synchronization frequency division signal div_clk is generated With synchronous triggering signal Fb_sync；
    S14. state control machine controls time-base signal Fb to be disconnected to the transmission channel of synchronous frequency divider, and time-base signal Fb is no longer triggered Synchronous frequency divider changes；
    Described tracking adjustment step S2 includes following sub-step：
    S21. by synchronization frequency division signal div_clk and time-base signal Fb input chronometer time measuring units, Time delay measurement is generated Signal delay_value；
    S22. by Time delay measurement signal delay_value input state control machines, according to Time delay measurement signal delay_value With standard delay amount Ttarget, generation delay configuration signal delay_adjust is calculated；
    S23. delay is configured into signal delay_adjust input sample delayers, according to delay configuration signal delay_adjust Sampling time delay device is adjusted, and delay process is carried out to synchronized sampling clock using the sampling time delay device after adjustment, is obtained Second delay clock Fs2.
  4. A kind of 4. accurate method for keeping multimode synchronous according to claim 3, it is characterised in that：In synchronous point of generation Before frequency signal, in addition to a synchronous frequency divider configuration step：State control machine is carried out to the system cycle of synchronous frequency divider Configuration, it is set to maintain unified signal frequency with time-base signal Fb.
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CN109884893B (en) * 2019-02-28 2021-09-10 西安理工大学 Multi-process variable dynamic time lag estimation method
CN114220255B (en) * 2021-12-29 2024-05-10 宜昌测试技术研究所 Distributed acoustic equipment synchronous control system and method
CN116054827A (en) * 2023-01-10 2023-05-02 中国兵器装备集团自动化研究所有限公司 Broadband digital array system synchronization method and device

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