CN112927643A - Gate drive circuit, drive method of gate drive circuit and display panel - Google Patents
Gate drive circuit, drive method of gate drive circuit and display panel Download PDFInfo
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- CN112927643A CN112927643A CN202110127450.7A CN202110127450A CN112927643A CN 112927643 A CN112927643 A CN 112927643A CN 202110127450 A CN202110127450 A CN 202110127450A CN 112927643 A CN112927643 A CN 112927643A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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Abstract
The invention discloses a gate driving circuit, a driving method of the gate driving circuit and a display panel. The grid driving circuit comprises an input module, a node control module, an output module, a switching tube and a leakage current suppression module; the input module is used for providing input signals for the node control module and the leakage current suppression module; the node control module is used for providing node control signals for the output module and the leakage current suppression module; the grid electrode of the switch tube is connected with the second power signal input end, the first pole of the switch tube is connected with the leakage current suppression module, and the second pole of the switch tube is connected with the output module; the leakage current suppression module is used for suppressing a second pole potential of the switch tube when the switch tube leaks; the output module is used for outputting a grid driving signal according to the node control signal and the input signal. The leakage current of the switching tube can be inhibited by arranging the leakage current inhibiting module in the grid driving circuit, so that the grid driving circuit can be ensured to output low-level signals in full range, and the stability of the grid driving circuit is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a gate driving circuit, a driving method of the gate driving circuit and a display panel.
Background
The display panel is provided with a gate driving circuit for providing driving signals for the pixel circuits in the display panel. The gate driving circuit has leakage current, so that the gate driving signal output by the gate driving circuit is abnormal, thereby reducing the stability of the gate driving circuit.
Disclosure of Invention
The invention provides a gate driving circuit, a driving method of the gate driving circuit and a display panel, and aims to improve the stability of the gate driving circuit.
In a first aspect, an embodiment of the present invention provides a gate driving circuit, including an input module, a node control module, an output module, a switching tube, and a leakage current suppression module;
the input module is connected with an input signal end, a clock signal input end, a node control module and a leakage current suppression module and is used for providing input signals for the node control module and the leakage current suppression module;
the node control module is connected with the input signal end, the clock signal input end, the first power signal input end, the output module and the leakage current suppression module and is used for providing node control signals for the output module and the leakage current suppression module;
the grid electrode of the switch tube is connected with a second power signal input end, the first pole of the switch tube is connected with the leakage current suppression module, and the second pole of the switch tube is connected with the output module;
the leakage current suppression module is connected with the second power signal input end and a second pole of the switch tube and used for suppressing the potential of the second pole of the switch tube when the switch tube leaks current;
the output module is connected with the first power signal input end and the second power signal input end and used for outputting a grid driving signal according to the node control signal and the input signal.
Optionally, the drain current suppressing module comprises a first transistor, a second transistor and a third transistor;
a gate of the first transistor is connected to an output terminal of the node control module, a first pole of the first transistor is connected to the second power signal input terminal, a second pole of the first transistor is connected to a second pole of the second transistor and a gate of the third transistor, a first pole of the second transistor and a first pole of the third transistor are connected to an output terminal of the input module, a gate of the second transistor is connected to a second pole of the switch, and a second pole of the third transistor is connected to a first pole of the switch.
Optionally, the output module includes a fourth transistor, a fifth transistor, a first capacitor, and a second capacitor;
the gate of the fourth transistor and the first pole of the first capacitor are connected to the output terminal of the node control module, the first pole of the fourth transistor and the second pole of the first capacitor are connected to the first power signal input terminal, the second pole of the fourth transistor and the second pole of the fifth transistor are connected to the second pole of the fifth transistor, the gate of the fifth transistor and the first pole of the second capacitor are connected to the second pole of the switching tube, the first pole of the fifth transistor and the second power signal input terminal are connected, and the second pole of the fifth transistor and the second pole of the second capacitor are connected to serve as the output terminal of the output module.
Optionally, the output module further comprises a sixth transistor and a seventh transistor;
the gate of the sixth transistor is connected to the gate of the fourth transistor, the first pole of the fourth transistor is connected to the first power signal input terminal through the sixth transistor, the gate of the seventh transistor is connected to the output terminal of the output module, the first pole of the seventh transistor is connected to the second power signal input terminal, and the second pole of the seventh transistor is connected to the first pole of the fourth transistor.
Optionally, the node control module comprises an eighth transistor, a ninth transistor, a tenth transistor and a third capacitor;
the gate of the eighth transistor is connected to the input signal terminal, the first pole of the eighth transistor and the first pole of the tenth transistor are connected to the first power signal input terminal, the second pole of the eighth transistor is connected to the gate of the ninth transistor and the first pole of the third capacitor, the first pole of the ninth transistor and the second pole of the third capacitor are connected to the clock signal input terminal, the second pole of the ninth transistor is connected to the second pole of the tenth transistor and serves as the output terminal of the node control module, and the gate of the tenth transistor is connected to the output terminal of the input module.
Optionally, the input module comprises an eleventh transistor;
the gate of the eleventh transistor is connected to the clock signal input terminal, the first pole of the eleventh transistor is connected to the input signal terminal, and the second pole of the eleventh transistor serves as the output terminal of the input module.
Optionally, the first to eleventh transistors are P-type transistors; the first power signal provided by the first power signal input terminal is at a high level, and the second power signal provided by the second power signal input terminal is at a low level.
In a second aspect, an embodiment of the present invention further provides a driving method of a gate driving circuit, configured to drive any gate driving circuit provided in the first aspect; the method comprises the following steps:
in the first stage, the node control signal output by the node control module controls the gate driving signal output by the output module to be at a low level, and simultaneously controls the leakage current suppression module to output the input signal provided by the input module to the output module;
in the second stage, the leakage current suppression module transmits the input signal provided by the input module and controls the gate drive signal output by the output module to be at a low level;
in a third phase, the leakage current suppression module suppresses leakage current between the input module and the switch tube.
Optionally, the drain current suppressing module comprises a first transistor, a second transistor and a third transistor;
a gate of the first transistor is connected to an output terminal of the node control module, a first pole of the first transistor is connected to the second power signal input terminal, a second pole of the first transistor is connected to a second pole of the second transistor and a gate of the third transistor, a first pole of the second transistor and a first pole of the third transistor are connected to an output terminal of the input module, a gate of the second transistor is connected to a second pole of the switch, and a second pole of the third transistor is connected to a first pole of the switch;
the driving method of the grid driving circuit comprises the following steps;
in the third stage, the second transistor is turned on, so that the potentials of the grid electrode, the source electrode and the drain electrode of the third transistor are controlled to be equal, and the third transistor is turned off.
In a third aspect, an embodiment of the present invention further provides a display panel, including any of the gate driving circuits provided in the first aspect.
According to the invention, the leakage current suppression module is arranged in the grid driving circuit, when the output module outputs a low level signal, the input signal and the node control signal control the leakage current suppression module to be cut off, so that the input signal provided by the input module cannot be transmitted to the first pole of the switch tube through the leakage current suppression module, the leakage current phenomenon of the switch tube can be improved, the second pole potential of the switch tube is prevented from being raised when the switch tube leaks, the pull-down action of the output module is prevented from being influenced by the second pole potential of the switch tube, the grid driving circuit is ensured to output the low level signal in a full range, and the stability of the grid driving circuit is improved.
Drawings
Fig. 1 is a schematic structural diagram of a partial gate driving circuit provided in the prior art;
fig. 2 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another gate driving circuit according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of another gate driving circuit according to an embodiment of the invention;
fig. 5 is a schematic structural diagram of another gate driving circuit according to an embodiment of the invention;
fig. 6 is a schematic structural diagram of another gate driving circuit according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another gate driving circuit according to an embodiment of the invention;
FIG. 8 is a timing diagram of the gate driving circuit shown in FIG. 7;
fig. 9 is a flowchart illustrating a driving method of a gate driving circuit according to an embodiment of the invention;
fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of a partial gate driving circuit provided in the prior art. As shown in fig. 1, the gate driving circuit includes a first P-type transistor M1, a second P-type transistor M2, a third P-type transistor M3, and a coupling capacitor Cs. The gate of the first P-type transistor M1 is connected to the clock signal line ECK, the first pole of the first P-type transistor M1 serves as an enable terminal EIN of the gate driving circuit, the second pole of the first P-type transistor M1 is connected to the first pole of the second P-type transistor M2, the gate of the second P-type transistor M2 is connected to the low-level power signal line VGL, the second pole of the second P-type transistor M2 is connected to the gate of the third P-type transistor M3 and the first pole of the coupling capacitor Cs, the first pole of the third P-type transistor M3 is connected to the low-level power signal line VGL, and the second pole of the third P-type transistor M3 is connected to the second pole of the coupling capacitor Cs and serves as an output terminal VOUT of the gate driving circuit. The second P-type transistor M2 is continuously turned on. When the clock signal provided by the clock signal line ECK is at a low level and the enable signal provided by the enable terminal EIN of the gate driving circuit is at a low level, the first P-type transistor M1 is turned on, the enable signal is transmitted to the gate of the third P-type transistor M3 through the first P-type transistor M1 and the second P-type transistor M2, the third P-type transistor M3 is controlled to be turned on, the low-level signal provided by the low-level power signal line VGL is output through the third P-type transistor M3, and the potential of the output gate driving signal is the difference between the low-level potential and the threshold of the third P-type transistor M3. At this time, the coupling effect of the coupling capacitor Cs makes the gate potential of the third P-type transistor M3 smaller than the low level signal, and the gate driving circuit can fully output the low level signal. When the gate potential of the third P-type transistor M3 is lower than the low level signal, the first pole potential of the second P-type transistor M2 is maintained at the low level potential, the second pole potential of the second P-type transistor M2 is lower than the low level potential, and the second P-type transistor M2 is turned off. In the subsequent stage, the first P-type transistor M1 is turned on or off intermittently, and a leakage current exists in the second P-type transistor M2, so that the gate potential of the third P-type transistor M3 gradually rises due to the leakage current. When the gate potential of the third P-type transistor M3 rises to the low level potential, the potential of the gate driving signal output by the third P-type transistor M3 is the difference between the low level potential and the threshold of the third P-type transistor M3, and therefore the low level signal cannot be output at full amplitude, which reduces the stability of the gate driving circuit. When the gate driving circuit is in a low-frequency operating state, the gate driving circuit outputs a low-level signal for a long time, and the third P-type transistor M3 is under negative stress for a long time, so that the threshold voltage of the third P-type transistor M3 is negatively biased, which further causes the level of the gate driving signal output by the third P-type transistor M3 to increase, and further reduces the stability of the gate driving circuit.
In view of the above technical problems, an embodiment of the present invention provides a gate driving circuit. Fig. 2 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention. As shown in fig. 2, the gate driving circuit includes an input module 110, a node control module 120, an output module 130, a switch tube 140, and a leakage current suppressing module 150; the input module 110 is connected to the input signal terminal STV, the clock signal input terminal CK, the node control module 120, and the leakage suppression module 150, and configured to provide an input signal for the node control module 120 and the leakage suppression module 150; the node control module 120 is connected to the input signal terminal STV, the clock signal input terminal CK, the first power signal input terminal V1, the output module 130, and the leakage suppression module 150, and is configured to provide a node control signal for the output module 130 and the leakage suppression module 150; the gate of the switch tube 140 is connected to the second power signal input terminal V2, the first pole of the switch tube 140 is connected to the leakage current suppressing module 150, and the second pole of the switch tube 140 is connected to the output module 130; the leakage current suppressing module 150 is connected to the second power signal input terminal V2 and the second pole of the switch tube 140, and is configured to suppress a second pole potential of the switch tube 140 when the switch tube 140 leaks current; the output module 130 is connected to the first power signal input terminal V1 and the second power signal input terminal V2, and is configured to output a gate driving signal according to a node control signal and an input signal.
Specifically, the switch tube 140 is always turned on under the control of the second power signal provided by the second power signal input terminal V2. As shown in fig. 2, the switching tube 140 may be a P-type transistor. The first power signal provided at the first power signal input terminal V1 may be high and the second power signal provided at the second power signal input terminal V2 may be low. The clock signal input CK may provide a clock signal. In the operation process of the gate driving circuit, the clock signal provided by the clock signal input terminal CK can control the input signal provided by the input signal terminal STV to be output to the node control module 120 and the leakage current suppressing module 150 through the input module 110, and the leakage current suppressing module 150 transmits the input signal to the output module 130 through the switch tube 140 under the action of the node control signal. Meanwhile, the node control module 130 may output a node control signal having a level opposite to that of the input signal to the output module 130 according to the input signal. The output module 130 outputs a gate driving signal according to the input signal and the node control signal. When the input signal is at a low level, the output module 130 may output the gate driving signal at the low level, and at this time, the pull-down action of the output module 130 makes the second pole potential of the switch tube 140 smaller than the potential of the low level signal, and the output module 130 may output the low level signal at full amplitude, and the switch tube 140 is turned off. And the input signal and the node control signal control the leakage current suppressing module 150 to be cut off, so that the input signal provided by the input module 110 cannot be transmitted to the first pole of the switch tube 140 through the leakage current suppressing module 150, thereby improving the leakage current phenomenon of the switch tube 140, and avoiding the second pole potential of the switch tube 140 being raised when the switch tube 140 leaks, so that the pull-down effect of the output module 130 is prevented from being influenced by the second pole potential of the switch tube 140, ensuring that the gate driving circuit can output a low level signal in full range, and improving the stability of the gate driving circuit.
Fig. 3 is a schematic structural diagram of another gate driving circuit according to an embodiment of the invention. As shown in fig. 3, the drain current suppressing module 150 includes a first transistor T1, a second transistor T2, and a third transistor T3; a gate of the first transistor T1 is connected to the output terminal OUT1 of the node control module 120, a first pole of the first transistor T1 is connected to the second power signal input terminal V2, a second pole of the first transistor T1 is connected to the second pole of the second transistor T2 and a gate of the third transistor T3, a first pole of the second transistor T2 and a first pole of the third transistor T3 are connected to the output terminal OUT2 of the input module 110, a gate of the second transistor T2 is connected to the second pole of the switch 140, and a second pole of the third transistor T3 is connected to the first pole of the switch 140.
Specifically, it is exemplarily shown in fig. 3 that the first transistor T1, the second transistor T2, and the third transistor T3 are P-type transistors. The first power signal provided by the first power signal input terminal V1 may be set to a high level and the second power signal provided by the second power signal input terminal V2 may be set to a low level. When the clock signal provided by the clock signal input terminal CK is at a low level and the input signal provided by the input signal terminal STV is at a low level, the input module 110 transmits the input signal provided by the input signal terminal STV to the node control module 120, controls the node control signal output by the node control module 120 to be a high level signal, controls the first transistor T1 to be turned off, maintains the gate potential of the third transistor T3 at a low level in the previous stage, turns on the third transistor T3, transmits the input signal to the switching tube 140 through the third transistor T3, and transmits the input signal to the output module 130 through the switching tube 140, and the output module 130 outputs a gate driving signal at a low level according to the input signal and controls the second transistor T2 to be turned on. The pull-down of the output module 130 makes the second pole potential of the switch tube 140 smaller than the potential of the low level signal, and the output module 130 can output the low level signal at full amplitude, while the switch tube 140 is turned off. When the gate driving circuit continues to output the low-level gate driving signal and the second transistor T2 continues to be turned on, the third transistor T3 is diode-connected, that is, the gate and the first pole of the third transistor T3 have the same potential, so that a signal with a certain voltage drop is generated after the input signal passes through the input module 110. Meanwhile, the second pole potential of the third transistor T3 keeps the input signal output by the input module 110 in the previous stage, and the potential of the input signal is equal to the potentials of the gate and the first pole of the third transistor T3, that is, the potentials of the gate, the first pole and the second pole of the third transistor T3 are equal, so that the leakage current is reduced when the third transistor T3 is turned off, further the leakage current phenomenon of the switch tube 140 is improved, the second pole potential of the switch tube 140 is prevented from being raised when the switch tube 140 leaks, further the pull-down action of the output module 130 is prevented from being affected by the second pole potential of the switch tube 140, the gate driving circuit is ensured to output a low level signal in full amplitude, and the stability of the gate driving circuit is improved.
Fig. 4 is a schematic structural diagram of another gate driving circuit according to an embodiment of the invention. As shown in fig. 4, the output module 130 includes a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2; a gate of the fourth transistor T4 and a first pole of the first capacitor C1 are connected to the output terminal OUT1 of the node control block 120, a first pole of the fourth transistor T4 and a second pole of the first capacitor C1 are connected to the first power signal input terminal V1, a second pole of the fourth transistor T4 is connected to a second pole of the fifth transistor T5, a gate of the fifth transistor T5 and a first pole of the second capacitor C2 are connected to the second pole of the switch tube 140, a first pole of the fifth transistor T5 is connected to the second power signal input terminal V2, and a second pole of the fifth transistor T5 and a second pole of the second capacitor C2 are connected to the output terminal OUT of the output block 130.
Specifically, it is exemplarily shown in fig. 4 that the fourth transistor T4 and the fifth transistor T5 are P-type transistors, the first power signal provided from the first power signal input terminal V1 is at a high level, and the second power signal provided from the second power signal input terminal V2 is at a low level. When the clock signal provided by the clock signal input terminal CK is at a low level and the input signal provided by the input signal terminal STV is at a low level, the input module 110 transmits the input signal provided by the input signal terminal STV to the node control module 120, so as to control the node control signal output by the node control module 120 to be a high level signal, the node control signal controls the first transistor T1 and the fourth transistor T4 to be turned off, and the first power signal provided by the first power signal input terminal V1 cannot be output through the fourth transistor T4. Meanwhile, the gate voltage of the third transistor T3 maintains the low level of the previous stage, the third transistor T3 is turned on, the input signal is transmitted to the switch tube 140 through the third transistor T3 and is transmitted to the fifth transistor T5 through the switch tube 140, the fifth transistor T5 is controlled to be turned on, the second power signal provided by the second power signal input terminal V2 is output through the fifth transistor T5, that is, the gate driving signal output by the output terminal OUT of the output module 130 is the difference between the low level and the threshold voltage of the fifth transistor T5. When the gate driving signal changes to low level, the coupling effect of the second capacitor C2 makes the gate potential of the fifth transistor T5 less than the potential of the low level signal, i.e. the second pole potential of the switch tube 140 is less than the potential of the low level signal, and the fifth transistor T5 can output the low level signal at full amplitude, while the switch tube 140 is turned off. At this time, the second transistor T2 is turned on under the control of the low level. When the gate driving circuit continuously outputs the gate driving signal with the low level, and the second transistor T2 is continuously turned on, so that the third transistor T3 is in a diode connection manner, that is, the gate and the first pole of the third transistor T3 have the same potential, and a signal with a certain voltage drop is generated after the input signal passes through the input module 110. Meanwhile, the second pole potential of the third transistor T3 keeps the input signal output by the input module 110 in the previous stage, and the potential of the input signal is equal to the gate and first pole potentials of the third transistor T3, so that the third transistor T3 is turned off, and the leakage current of the third transistor T3 is reduced, thereby improving the leakage current phenomenon of the switch tube 140, avoiding the second pole potential of the switch tube 140 being raised when the switch tube 140 leaks, avoiding the rise of the gate potential of the fifth transistor T5, ensuring that the fifth transistor T5 can output a low-level signal in full amplitude, and improving the stability of the gate driving circuit.
Fig. 5 is a schematic structural diagram of another gate driving circuit according to an embodiment of the invention. As shown in fig. 5, the output module 130 further includes a sixth transistor T6 and a seventh transistor T7; a gate of the sixth transistor T6 is connected to a gate of the fourth transistor T4, a first pole of the fourth transistor T4 is connected to the first power signal input terminal V1 through the sixth transistor T6, a gate of the seventh transistor T7 is connected to the output terminal OUT of the output block 130, a first pole of the seventh transistor T7 is connected to the second power signal input terminal V2, and a second pole of the seventh transistor T7 is connected to a first pole of the fourth transistor T4.
Specifically, fig. 5 exemplarily shows that the sixth transistor T6 and the seventh transistor T7 are P-type transistors, the first power signal provided from the first power signal input terminal V1 is at a high level, and the second power signal provided from the second power signal input terminal V2 is at a low level. When the clock signal provided by the clock signal input terminal CK is at a low level and the input signal provided by the input signal terminal STV is at a low level, the input module 110 transmits the input signal provided by the input signal terminal STV to the node control module 120, controls the node control signal output by the node control module 120 to be a high level signal, controls the first transistor T1, the fourth transistor T4 and the sixth transistor T6 to be turned off by the node control signal, and the first power signal provided by the first power signal input terminal V1 cannot be output through the fourth transistor T4 and the sixth transistor T6. Meanwhile, the gate potential of the third transistor T3 maintains the low level of the previous stage, the third transistor T3 is turned on, the input signal is transmitted to the switch tube 140 through the third transistor T3 and is transmitted to the fifth transistor T5 through the switch tube 140, the fifth transistor T5 is controlled to be turned on, the second power signal provided by the second power signal input terminal V2 is output through the fifth transistor T5, that is, the output terminal OUT of the output module 130 outputs a low level signal. At this time, the seventh transistor T7 is turned on, and the second power signal provided by the second power signal input terminal V2 is transmitted to the first electrode of the fourth transistor T4 through the seventh transistor T7, so that a phenomenon of leakage current of the fourth transistor T4 due to a large potential difference between the first electrode potential and the second electrode potential of the fourth transistor T4 when the first electrode potential of the fourth transistor T4 is the first power signal can be avoided, and the stability of the gate driving circuit outputting the gate driving signal is further improved.
Fig. 6 is a schematic structural diagram of another gate driving circuit according to an embodiment of the present invention. As shown in fig. 6, the node control module 120 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a third capacitor C3; a gate of the eighth transistor T8 is connected to the input signal terminal STV, a first pole of the eighth transistor T8 and a first pole of the tenth transistor T10 are connected to the first power signal input terminal V1, a second pole of the eighth transistor T8 is connected to a gate of the ninth transistor T9 and a first pole of the third capacitor C3, a first pole of the ninth transistor T9 and a second pole of the third capacitor C3 are connected to the clock signal input terminal CK, a second pole of the ninth transistor T9 is connected to a second pole of the tenth transistor T19 and serves as an output terminal OUT1 of the node control block 120, and a gate of the tenth transistor T10 is connected to an output terminal OUT2 of the input block 110.
Specifically, it is exemplarily shown in fig. 6 that the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are P-type transistors. The first power signal provided at the first power signal input terminal V1 is at a high level and the second power signal provided at the second power signal input terminal V2 is at a low level. When the clock signal provided by the clock signal input terminal CK is at a low level and the input signal provided by the input signal terminal STV is at a low level, the input module 110 transmits the input signal provided by the input signal terminal STV to the gate of the tenth transistor T10 to control the tenth transistor T10 to be turned on, and the first power signal provided by the first power signal input terminal V1 is output through the tenth transistor T10, i.e., the output terminal OUT1 of the node control module 120 outputs a high-level signal. Meanwhile, the clock signal controls the eighth transistor T8 to be turned on, and the first power signal provided by the first power signal input terminal V1 is transmitted to the gate of the ninth transistor T9 through the eighth transistor T8, so that the gate potential of the ninth transistor T9 is prevented from being lowered due to the coupling effect of the third capacitor C3, and the ninth transistor T9 can be controlled to be turned off. When the clock signal provided by the clock signal input terminal CK is at a low level and the input signal provided by the input signal terminal STV is at a high level, the input signal controls the eighth transistor T8 to be turned off, and the input module 110 transmits the input signal provided by the input signal terminal STV to the gate of the tenth transistor T10 to control the tenth transistor T10 to be turned off. The clock signal provided by the clock signal input terminal CK is coupled to the gate of the ninth transistor T9 through the third capacitor C3, so that the ninth transistor T9 is controlled to be turned on, the clock signal provided by the clock signal input terminal CK is output through the ninth transistor T9, that is, the output terminal OUT1 of the node control module 120 outputs a low-level signal, the first transistor T1, the fourth transistor T4 and the sixth transistor T6 are controlled to be turned on, the first power signal provided by the first power signal input terminal V1 is output through the fourth transistor T4 and the sixth transistor T6, and the output terminal OUT of the output module 130 outputs a high-level signal. Meanwhile, the first power signal provided by the first power signal input terminal V1 is output to the gate of the third transistor T3 through the first transistor T1, which controls the third transistor T3 to be turned on, and the input signal output by the input module 110 is transmitted to the gate of the fifth transistor T5 through the third transistor T3 and the switch 140, which controls the fifth transistor T5 to be turned off.
Fig. 7 is a schematic structural diagram of another gate driving circuit according to an embodiment of the invention. As shown in fig. 7, the input block 110 includes an eleventh transistor T11; a gate of the eleventh transistor T11 is connected to the clock signal input terminal CK, a first pole of the eleventh transistor T11 is connected to the input signal terminal STV, and a second pole of the eleventh transistor T11 serves as the output terminal OUT2 of the input block 110.
In particular, fig. 7 exemplarily shows that the eleventh transistor T11 is a P-type transistor. The first power signal provided at the first power signal input terminal V1 is at a high level and the second power signal provided at the second power signal input terminal V2 is at a low level. When the clock signal provided by the clock signal input terminal CK is at a low level, the input signal provided by the input signal terminal STV is output through the eleventh transistor T11, i.e., the output terminal OUT2 of the input block 110 outputs the difference between the input signal and the threshold voltage of the eleventh transistor T11.
The first power signal provided at the first power signal input terminal V1 may be set to a high level and the second power signal provided at the second power signal input terminal V2 may be set to a low level. Fig. 8 is a timing diagram corresponding to the gate driving circuit provided in fig. 7. Wherein, STV is a time sequence of an input signal provided by the input signal terminal STV, CK is a time sequence of a clock signal provided by the clock signal input terminal CK, and OUT is a time sequence of a gate driving signal provided by the output terminal OUT of the output module. The operation of the gate driving circuit is described below with reference to fig. 7 and 8.
In the first period T11, stv is high, CK is high, the eighth transistor T8 and the eleventh transistor T11 are turned off, and the clock signal provided by the clock signal input terminal CK is transmitted to the gate of the ninth transistor T9 through the coupling effect of the third capacitor C3, so as to control the ninth transistor T9 to be turned off. The eleventh transistor T11 is turned off, the first electrode of the third transistor T3 is in a floating state, the low level signal of the previous stage is maintained, the tenth transistor T10 is controlled to be turned on, the node control module 120 outputs a high level signal, and the fourth transistor T4 and the sixth transistor T6 are controlled to be turned off. Meanwhile, the gate of the fifth transistor T5 is maintained at a low level, which controls the fifth transistor T5 to be turned on, and the gate driving signal output by the gate driving circuit is maintained at a low level. The gate driving signal controls the seventh transistor T7 to be turned on, and the second power signal provided by the second power signal input terminal V2 is transmitted to the first electrode of the fourth transistor T4 through the seventh transistor T7, so that the phenomenon of leakage current of the fourth transistor T4 due to a large potential difference between the first electrode potential and the second electrode potential of the fourth transistor T4 when the first electrode potential of the fourth transistor T4 is the first power signal can be avoided, and the stability of the gate driving circuit outputting the gate driving signal is further improved.
In the second stage T12, stv is high, ck is low, the eighth transistor T8 is turned off, and the eleventh transistor T11 is turned on. The input signal is output through the eleventh transistor T11, controlling the tenth transistor T10 to be turned off. The clock signal provided by the clock signal input terminal CK is coupled to the gate of the ninth transistor T9 through the third capacitor C3, so that the ninth transistor T9 is controlled to be turned on, the clock signal provided by the clock signal input terminal CK is output through the ninth transistor T9, that is, the output terminal OUT1 of the node control module 120 outputs a low-level signal, the first transistor T1, the fourth transistor T4 and the sixth transistor T6 are controlled to be turned on, the first power signal provided by the first power signal input terminal V1 is output through the fourth transistor T4 and the sixth transistor T6, the output terminal OUT of the output module 130 outputs a high-level signal, and the output high-level signal controls the seventh transistor T7 to be turned off. Meanwhile, the first power signal provided by the first power signal input terminal V1 is output to the gate of the third transistor T3 through the first transistor T1, which controls the third transistor T3 to be turned on, and the input signal is transmitted to the gate of the fifth transistor T5 through the eleventh transistor T11, the third transistor T3 and the switch tube 140, which controls the fifth transistor T5 to be turned off. At this time, the second pole potential of the switch tube 140 is at a high level, and the second transistor T2 is controlled to be turned off.
In the third stage T13, stv is low, ck is high, the eighth transistor T8 is turned on, and the eleventh transistor T11 is turned off. The first power signal provided from the first power signal input terminal V1 is transmitted to the gate of the ninth transistor T9 through the eighth transistor T8, and controls the ninth transistor T9 to be turned off. The eleventh transistor T11 has a floating second pole to maintain the high level voltage of the previous stage, the tenth transistor T10 remains off, the output terminal OUT1 of the node control block 120 is floating to maintain the low level voltage of the previous stage, and the output terminal OUT of the output block 130 outputs a high level signal. Meanwhile, the third transistor T3 is turned on, and the input signal is transmitted to the gate of the fifth transistor T5 through the eleventh transistor T11, the third transistor T3 and the switch 140, thereby controlling the fifth transistor T5 to be turned off.
In a fourth stage T14, stv is low, ck is low, the eighth transistor T8 and the eleventh transistor T11 are turned on, the input signal is output through the eleventh transistor T11, when the potential output by the eleventh transistor T11 is the difference between the low level and the threshold voltage of the eleventh transistor T11, the low level output by the eleventh transistor T11 controls the tenth transistor T10 to be turned on, the node control module 120 outputs a high level signal, controls the first transistor T1, the fourth transistor T4 and the sixth transistor T6 to be turned off, the gate of the third transistor T3 maintains the low level potential of the previous stage, the third transistor T3 is turned on, the level output by the eleventh transistor T11 is output to the gate of the fifth transistor T5 through the third transistor T3 and the switching transistor 140, controls the fifth transistor T5 to be turned on, the second power supply signal provided by the second power supply signal input terminal V2 is output through the fifth transistor T5, at this time, the gate driving signal outputted from the gate driving circuit is a difference between the low level potential and the threshold voltage of the fifth transistor T5. Then, the coupling of the second capacitor C2 makes the gate potential of the fifth transistor T5 lower than the potential of the low-level signal, so that the fifth transistor T5 can output the low-level signal at full amplitude.
In the above process, the potentials of the first pole and the second pole of the third transistor are equal, and both are the difference between the low level and the threshold voltage of the eleventh transistor T11. The gate driving signal controls the seventh transistor T7 to be turned on, and the second power signal provided by the second power signal input terminal V2 is transmitted to the first electrode of the fourth transistor T4 through the seventh transistor T7, so that the phenomenon of leakage current of the fourth transistor T4 due to a large potential difference between the first electrode potential and the second electrode potential of the fourth transistor T4 when the first electrode potential of the fourth transistor T4 is the first power signal can be avoided, and the stability of the gate driving circuit outputting the gate driving signal is further improved.
In the fifth period T15, stv is low, ck is high, the eighth transistor T8 is turned on, and the eleventh transistor T11 is turned off. The first power signal provided from the first power signal input terminal V1 is transmitted to the gate of the ninth transistor T9 through the eighth transistor T8, and controls the ninth transistor T9 to be turned off. The output terminal OUT1 of the node control module 120 is in a floating state, and maintains the high level potential of the previous stage, and the first transistor T1, the fourth transistor T4 and the sixth transistor T6 are turned off. The second pole of the eleventh transistor T11 is in a floating state, and maintains the low level potential of the previous stage. After the previous stage, the second pole potential of the switch tube 140 is less than the potential of the low level signal, so that the switch tube 140 is turned off, the second transistor T2 is turned on, and the third transistor T3 realizes a diode connection mode. At this time, the gate, the first pole and the second pole of the third transistor T3 are equal to each other, and are the difference between the low level potential and the threshold voltage of the transistor, thereby showing that the third transistor T3 is turned off, and the leakage current of the third transistor T3 is obviously reduced, thereby improving the leakage current phenomenon of the switch tube 140, and avoiding the second pole potential of the switch tube 140 being raised when the switch tube 140 leaks, so that the pull-down action of the output module 130 is prevented from being influenced by the second pole potential of the switch tube 140, ensuring that the gate driving circuit can output the low level signal in full amplitude, and improving the stability of the gate driving circuit.
On the basis of the above technical solutions, the first transistor T1 to the eleventh transistor T11 are P-type transistors; the first power signal provided at the first power signal input terminal V1 is at a high level and the second power signal provided at the second power signal input terminal V2 is at a low level.
Specifically, after the first power signal provided by the first power signal input terminal V1 is maintained at a high level and the second power signal provided by the second power signal input terminal V2 is maintained at a low level, the states of the transistors can be controlled according to the input signal and the clock signal, so that the gate driving circuit can normally output the gate driving signal.
In other embodiments, the first to eleventh transistors T1 to T11 may also be N-type transistors, and the high and low levels of the first power signal provided by the first power signal input terminal V1 and the second power signal provided by the second power signal input terminal V2 are adaptively changed.
The embodiment of the invention also provides a driving method of the gate driving circuit, which is used for driving the gate driving circuit provided by any embodiment of the invention. Fig. 9 is a flowchart illustrating a driving method of a gate driving circuit according to an embodiment of the invention. As shown in fig. 9, the driving method of the gate driving circuit includes:
s910, in the first stage, the node control signal output by the node control module controls the gate driving signal output by the output module to be at a low level, and simultaneously controls the leakage current suppression module to output the input signal provided by the input module to the output module;
in the first stage, the input signal provided by the input signal terminal is at a high level, the clock signal provided by the clock signal input terminal is at a low level, the node control signal output by the node control module is at a low level, the output module is controlled to output a high level signal, and the leakage current suppression module is controlled to output the input signal provided by the input module to the output module. In the subsequent process, when the input signal provided by the input signal terminal is at a low level and the clock signal provided by the clock signal input terminal is at a high level, the gate driving circuit keeps outputting a high-level signal.
S920, in the second stage, the leakage current suppression module transmits the input signal provided by the input module and controls the gate driving signal output by the output module to be at a low level;
in the second stage, the input signal provided by the input signal terminal is at a low level, the clock signal provided by the clock signal input terminal is at a low level, and the node control signal output by the node control module is at a high level. The input signal output by the leakage current suppression module controls the output module to output a low level signal, the pull-down action of the output module controls the output module to output the low level signal in a full range, and the switching tube is cut off at the moment.
And S930, in the third stage, the leakage current suppression module suppresses leakage current between the input module and the switch tube.
In the third stage, the input signal provided by the input signal end is at a low level, the clock signal provided by the clock signal input end is at a high level, the switching tube is continuously cut off, the leakage current suppression module is cut off, and the leakage current is reduced. The input signal provided by the input module can not be transmitted to the first pole of the switch tube through the leakage current suppression module, so that the leakage current phenomenon of the switch tube can be improved, the second pole potential of the switch tube is lifted when the leakage current of the switch tube is avoided, the influence of the second pole potential of the switch tube on the pull-down action of the output module can be avoided, the fact that the grid drive circuit can output low-level signals in a full range is guaranteed, and the stability of the grid drive circuit is improved.
According to the technical scheme of the embodiment of the invention, after the grid driving signal output by the grid driving circuit is at a low level, the pull-down action of the output module enables the second pole potential of the switch tube to be smaller than the potential of the low level signal, the output module can output the low level signal in a full range, and meanwhile, the switch tube is cut off. And input signal and node control signal control leakage current restrain module are cut off for the input signal that input module provided can't transmit to the first pole of switch tube through leakage current restrain module, thereby can improve the leakage current phenomenon of switch tube, has avoided the second pole electric potential of switch tube to have lifted when the switch tube leaks, thereby can avoid the pull-down effect of output module to receive the influence of the second pole electric potential of switch tube, has guaranteed that grid drive circuit can full output low level signal, has improved grid drive circuit's stability.
On the basis of the technical scheme, the leakage current suppression module comprises a first transistor, a second transistor and a third transistor; when the grid electrode of the first transistor is connected with the output end of the node control module, the first pole of the first transistor is connected with the second power supply signal input end, the second pole of the first transistor is connected with the second pole of the second transistor and the grid electrode of the third transistor, the first pole of the second transistor and the first pole of the third transistor are connected with the output end of the input module, the grid electrode of the second transistor is connected with the second pole of the switch tube, and the second pole of the third transistor is connected with the first pole of the switch tube, the driving method of the grid driving circuit comprises the following steps:
in the third stage, the second transistor is turned on, the potentials of the grid electrode, the source electrode and the drain electrode of the third transistor are controlled to be equal, and the third transistor is turned off.
Specifically, in the third stage, the second transistor is turned on, and the third transistor may be controlled to be in a diode connection mode, that is, the gate and the first pole of the third transistor have the same potential, so that a signal with a certain voltage drop is generated after the input signal passes through the input module. Meanwhile, the second pole potential of the third transistor keeps the input signal output by the input module at the previous stage, and the potential of the second pole potential is equal to the potential of the grid electrode and the first pole potential of the third transistor, namely the potential of the grid electrode, the first pole potential and the second pole potential of the third transistor are equal, so that the leakage current is reduced when the third transistor is cut off, the leakage current phenomenon of the switch tube is further improved, the second pole potential of the switch tube is prevented from being raised when the switch tube leaks, the pull-down action of the output module is prevented from being influenced by the second pole potential of the switch tube, the fact that the grid drive circuit can output low-level signals in a full range is ensured, and the stability of the grid drive circuit is improved.
The embodiment of the invention also provides a display panel. Fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 10, the display panel includes a gate driving circuit 211 provided in any embodiment of the present invention.
Specifically, as shown in fig. 10, the display panel includes a display area AA and a non-display area NAA, the display area AA is provided with the pixel unit 200, the non-display area NAA is provided with a gate driver 210, and the gate driver 210 includes a plurality of stages of gate driving circuits 211 connected in cascade. Each stage of the gate driving circuit 211 may provide a gate driving signal to the pixel unit 200 of the corresponding row. The stability of the gate driving circuit is improved, and the display stability of the display panel is further improved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A grid driving circuit is characterized by comprising an input module, a node control module, an output module, a switch tube and a leakage current suppression module;
the input module is connected with an input signal end, a clock signal input end, a node control module and a leakage current suppression module and is used for providing input signals for the node control module and the leakage current suppression module;
the node control module is connected with the input signal end, the clock signal input end, the first power signal input end, the output module and the leakage current suppression module and is used for providing node control signals for the output module and the leakage current suppression module;
the grid electrode of the switch tube is connected with a second power signal input end, the first pole of the switch tube is connected with the leakage current suppression module, and the second pole of the switch tube is connected with the output module;
the leakage current suppression module is connected with the second power signal input end and a second pole of the switch tube and used for suppressing the potential of the second pole of the switch tube when the switch tube leaks current;
the output module is connected with the first power signal input end and the second power signal input end and used for outputting a grid driving signal according to the node control signal and the input signal.
2. The gate driving circuit of claim 1, wherein the leakage current suppression module comprises a first transistor, a second transistor, and a third transistor;
a gate of the first transistor is connected to an output terminal of the node control module, a first pole of the first transistor is connected to the second power signal input terminal, a second pole of the first transistor is connected to a second pole of the second transistor and a gate of the third transistor, a first pole of the second transistor and a first pole of the third transistor are connected to an output terminal of the input module, a gate of the second transistor is connected to a second pole of the switch, and a second pole of the third transistor is connected to a first pole of the switch.
3. A gate driving circuit according to claim 2, wherein the output module comprises a fourth transistor, a fifth transistor, a first capacitor and a second capacitor;
the gate of the fourth transistor and the first pole of the first capacitor are connected to the output terminal of the node control module, the first pole of the fourth transistor and the second pole of the first capacitor are connected to the first power signal input terminal, the second pole of the fourth transistor and the second pole of the fifth transistor are connected to the second pole of the fifth transistor, the gate of the fifth transistor and the first pole of the second capacitor are connected to the second pole of the switching tube, the first pole of the fifth transistor and the second power signal input terminal are connected, and the second pole of the fifth transistor and the second pole of the second capacitor are connected to serve as the output terminal of the output module.
4. A gate drive circuit as claimed in claim 3, wherein the output module further comprises a sixth transistor and a seventh transistor;
the gate of the sixth transistor is connected to the gate of the fourth transistor, the first pole of the fourth transistor is connected to the first power signal input terminal through the sixth transistor, the gate of the seventh transistor is connected to the output terminal of the output module, the first pole of the seventh transistor is connected to the second power signal input terminal, and the second pole of the seventh transistor is connected to the first pole of the fourth transistor.
5. The gate driving circuit according to claim 4, wherein the node control module comprises an eighth transistor, a ninth transistor, a tenth transistor and a third capacitor;
the gate of the eighth transistor is connected to the input signal terminal, the first pole of the eighth transistor and the first pole of the tenth transistor are connected to the first power signal input terminal, the second pole of the eighth transistor is connected to the gate of the ninth transistor and the first pole of the third capacitor, the first pole of the ninth transistor and the second pole of the third capacitor are connected to the clock signal input terminal, the second pole of the ninth transistor is connected to the second pole of the tenth transistor and serves as the output terminal of the node control module, and the gate of the tenth transistor is connected to the output terminal of the input module.
6. A gate drive circuit as claimed in claim 5, wherein the input block comprises an eleventh transistor;
the gate of the eleventh transistor is connected to the clock signal input terminal, the first pole of the eleventh transistor is connected to the input signal terminal, and the second pole of the eleventh transistor serves as the output terminal of the input module.
7. The gate driver circuit according to claim 6, wherein the first to eleventh transistors are P-type transistors; the first power signal provided by the first power signal input terminal is at a high level, and the second power signal provided by the second power signal input terminal is at a low level.
8. A driving method of a gate driving circuit for driving the gate driving circuit according to any one of claims 1 to 7; it is characterized by comprising:
in the first stage, the node control signal output by the node control module controls the gate driving signal output by the output module to be at a low level, and simultaneously controls the leakage current suppression module to output the input signal provided by the input module to the output module;
in the second stage, the leakage current suppression module transmits the input signal provided by the input module and controls the gate drive signal output by the output module to be at a low level;
in a third phase, the leakage current suppression module suppresses leakage current between the input module and the switch tube.
9. The driving method of the gate driving circuit according to claim 8, wherein the drain current suppressing module includes a first transistor, a second transistor, and a third transistor;
a gate of the first transistor is connected to an output terminal of the node control module, a first pole of the first transistor is connected to the second power signal input terminal, a second pole of the first transistor is connected to a second pole of the second transistor and a gate of the third transistor, a first pole of the second transistor and a first pole of the third transistor are connected to an output terminal of the input module, a gate of the second transistor is connected to a second pole of the switch, and a second pole of the third transistor is connected to a first pole of the switch;
the driving method of the grid driving circuit comprises the following steps;
in the third stage, the second transistor is turned on, so that the potentials of the grid electrode, the source electrode and the drain electrode of the third transistor are controlled to be equal, and the third transistor is turned off.
10. A display panel comprising the gate driver circuit according to any one of claims 1 to 7.
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