CN114333684A

CN114333684A - Shift register, gate drive circuit and drive method of shift register

Info

Publication number: CN114333684A
Application number: CN202111629908.5A
Authority: CN
Inventors: 郭恩卿; 李俊峰; 盖翠丽; 潘康观
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2021-12-28
Filing date: 2021-12-28
Publication date: 2022-04-12

Abstract

The invention discloses a shift register, a grid drive circuit and a drive method of the shift register, wherein the shift register comprises a first output control module, a second output control module, a first output module and a second output module; the first output control module controls the transmission of a first input signal and a second input signal to a first node according to a first clock signal and a starting signal; the second output control module controls the transmission of a third input signal and a third potential signal to a second node according to the initial signal and the potential of the first node; the first output module controls the transmission of the second potential signal to the first output end according to the potential of the first node; the second output module controls the transmission of the second clock signal to the first output end according to the electric potential of the control end. The absolute value of the voltage value of the third potential signal is greater than the absolute value of the voltage value of the first signal in the second clock signal, so that the shift register can tolerate a larger drift range of the threshold voltage.

Description

Shift register, gate drive circuit and drive method of shift register

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a shift register, a grid driving circuit and a driving method of the shift register.

Background

With the development of display technology, the requirements on display quality are higher and higher.

The conventional display panel generally includes a gate driving circuit, which includes a multi-stage shift register, where the shift register shifts a start signal and outputs the shifted start signal to a pixel circuit of the display panel, so as to drive the pixel circuit.

The gate driving circuit comprises a shift register which comprises a transistor, and the threshold voltage of the transistor is easy to drift along with the use of the transistor, so that the abnormal operation of the gate driving circuit is easy to cause.

Disclosure of Invention

The invention provides a shift register, a grid drive circuit and a drive method of the shift register, which aim to realize the tolerance of the shift register to the drift of threshold voltage and improve the working reliability of the shift register.

In a first aspect, an embodiment of the present invention provides a shift register, including a first output control module, a second output control module, a first output module, and a second output module;

the first output control module is used for controlling the transmission of a first input signal and a second input signal to a first node according to a first clock signal and a starting signal; the first input signal comprises a first clock signal or a first potential signal; the second input signal comprises a second clock signal or a second potential signal;

the second output control module is used for controlling the transmission of a third input signal and a third potential signal to a second node according to the initial signal and the potential of the first node; the third input signal is an initial signal or a first potential signal; the second node is electrically connected with the control end of the second output module;

the first output module is used for controlling the transmission of the second potential signal to the first output end of the shift register according to the potential of the first node;

the second output module is used for controlling the transmission of a second clock signal to the first output end of the shift register according to the potential of the control end of the second output module;

the absolute value of the voltage value of the third potential signal is greater than the absolute value of the voltage value of the first signal in the second clock signal, wherein the first signal of the second clock signal is the same as the second potential signal and the third potential signal in positive or negative.

Optionally, an absolute value of a voltage value of the second potential signal is less than or equal to an absolute value of a voltage value of the third potential signal;

optionally, the second input signal includes one of a second clock signal, a second potential signal, and a third potential signal.

Optionally, the first output control module includes a first output control unit and a second output control unit;

the first output control unit is used for controlling the transmission of a first input signal to a first node according to a first clock signal;

the second output control unit is used for controlling the transmission of the second input signal to the first node according to the starting signal.

Optionally, the first output control unit includes a first transistor, a gate of the first transistor is connected to the first clock signal, a first pole of the first transistor is connected to the first input signal, and a second pole of the first transistor is electrically connected to the first node;

the second output control unit comprises a second transistor, the grid electrode of the second transistor is connected with the initial signal, the first pole of the second transistor is connected with the second input signal, and the second pole of the second transistor is electrically connected with the first node;

the width-to-length ratio of the second transistor is greater than the width-to-length ratio of the first transistor.

Optionally, the second output control module includes a third output control unit and a fourth output control unit;

the third output control unit is used for controlling the transmission of a third input signal to the second node according to the starting signal;

the fourth output control unit is used for controlling the transmission of the third potential signal to the second node according to the potential of the first node.

Optionally, the third output control unit includes a third transistor, a gate of the third transistor is connected to the start signal, a first pole of the third transistor is connected to the third input signal, and a second pole of the third transistor is electrically connected to the second node;

the fourth output control unit comprises a fourth transistor, the grid electrode of the fourth transistor is electrically connected with the first node, the first pole of the fourth transistor is connected with the third potential signal, and the second pole of the fourth transistor is electrically connected with the second node.

Optionally, the first output module includes a fifth transistor and a first capacitor;

a grid electrode of the fifth transistor is used as a control end of the first output module and is electrically connected with the first node, a first pole of the fifth transistor is connected with the second potential signal, and a second pole of the fifth transistor is electrically connected with the first output end of the shift register;

the first end of the first capacitor is electrically connected with the second potential signal, and the second end of the first capacitor is electrically connected with the grid electrode of the fifth transistor.

Optionally, the second output module includes a sixth transistor and a second capacitor;

a grid electrode of the sixth transistor is used as a control end of the second output module, a first pole of the sixth transistor is connected to the second clock signal, and a second pole of the sixth transistor is electrically connected with the first output end of the shift register;

the second capacitor is used for coupling the potential of the grid electrode of the sixth transistor according to the jump of the second clock signal;

optionally, the shift register further includes a seventh transistor, the second node is electrically connected to a gate of the sixth transistor through the seventh transistor, and the gate of the seventh transistor is connected to the first potential signal.

Optionally, the shift register further includes a third output module and a fourth output module;

the control end of the third output module is electrically connected with the first node, and the third output module is used for controlling the transmission of a third potential signal to the second output end of the shift register according to the potential of the first node;

the control end of the fourth output module is electrically connected with the second node, and the fourth output module is used for controlling the transmission of the second clock signal to the second output end of the shift register according to the potential of the control end of the fourth output module;

optionally, an absolute value of a voltage value of the first potential signal is greater than an absolute value of a voltage value of a second signal in the second clock signal, where the second signal of the second clock signal is the same positive or the same negative as the first potential signal;

optionally, a first end of the second capacitor is electrically connected to the control end of the second output module, a second end of the second capacitor is electrically connected to the first output end of the shift register, or a second end of the second capacitor is electrically connected to the second output end of the shift register, or a second end of the second capacitor is connected to the second clock signal;

optionally, the third output module includes an eighth transistor, a gate of the eighth transistor is used as a control end of the third output module, a first pole of the eighth transistor is electrically connected to the third potential signal, and a second pole of the eighth transistor is electrically connected to the second output end of the shift register;

the fourth output module comprises a ninth transistor, a grid electrode of the ninth transistor is used as a control end of the fourth output module, a first pole of the ninth transistor is electrically connected with the second clock signal, and a second pole of the ninth transistor is electrically connected with the second output end of the shift register.

In a second aspect, an embodiment of the present invention further provides a gate driving circuit, where the gate driving circuit includes any one of the shift registers in the first aspect, and the gate driving circuit includes at least two shift registers connected in series, and each shift register includes a start signal input end, and in two adjacent shift registers, a first output signal at a first output end of a previous shift register is used as a start signal accessed by a start signal input end of a next shift register, or a second output signal at a second output end of the previous shift register is used as a start signal accessed by a start signal input end of a next shift register.

In a third aspect, an embodiment of the present invention further provides a driving method of a shift register, which is used to drive the shift register of the first aspect, and the driving method of the shift register includes:

providing a first clock signal, a start signal, a first input signal and a second input signal to a first output control module, so that the first output control module controls the transmission of the first input signal and the second input signal to a first node according to the first clock signal and the start signal; the first input signal comprises a first clock signal or a first potential signal; the second input signal comprises a second clock signal or a second potential signal;

providing the start signal, the third input signal and the third potential signal to the second output control module, so that the second output control module controls the transmission of the third input signal and the third potential signal to the second node according to the start signal and the potential of the first node; the third input signal is an initial signal or a first potential signal; the second node is electrically connected with the control end of the second output module;

the first output module controls the transmission of the second potential signal to the first output end of the shift register according to the potential of the first node;

the second output module controls the transmission of a second clock signal to the first output end of the shift register according to the potential of the control end of the second output module;

The embodiment of the invention provides a shift register, a grid drive circuit and a drive method of the shift register, wherein the shift register comprises a first output control module, a second output control module, a first output module and a second output module; the first output control module is used for controlling the transmission of a first input signal and a second input signal to a first node according to a first clock signal and a starting signal; the second output control module is used for controlling the transmission of a third input signal and a third potential signal to a second node according to the initial signal and the potential of the first node; the second node is electrically connected with the control end of the second output module; the first output module is used for controlling the transmission of the second potential signal to the first output end of the shift register according to the potential of the first node; the second output module is used for controlling the transmission of the second clock signal to the first output end of the shift register according to the electric potential of the control end of the second output module. The absolute value of the voltage value of the third potential signal is greater than the absolute value of the voltage value of the first signal in the second clock signal, and the first signal of the second clock signal is the same as the second potential signal and the third potential signal in positive or negative. When the absolute value of the voltage value of the third potential signal is greater than the absolute value of the voltage value of the first signal in the second clock signal, the second output module can be normally turned off even if the threshold voltage of the switching device included in the second output module drifts, and therefore the first output module is not influenced by the second output module when being turned on to output the second potential signal. Therefore, the shift register can tolerate a larger drift range of the threshold voltage, the second output module can be normally turned off, and the reliability of the shift register is improved.

Drawings

Fig. 1 is a schematic diagram of a shift register in the prior art.

Fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of another shift register according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of another shift register according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another shift register according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another shift register according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating an alternative shift register according to an embodiment of the present invention;

FIG. 8 is a timing diagram illustrating an operation of a shift register according to an embodiment of the present invention;

FIG. 9 is a diagram illustrating an alternative shift register according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention;

fig. 11 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 12 is a flowchart of a driving method of a shift register according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As described in the background art, as the transistor is used, the threshold voltage of the transistor is liable to drift, which is liable to cause an abnormal operation of the gate driver circuit. The inventors have found that the IGZO transistor is more likely to have a shift in threshold voltage, so that the shift register and the gate driver circuit including the IGZO transistor are more likely to have an abnormal operation. The reason for the above problem is that IGZO transistors have a large threshold voltage drift range and low mobility. Fig. 1 is a schematic structural diagram of a shift register in the prior art, where fig. 1 only schematically illustrates a partial structure of the shift register, and referring to fig. 1, the output control module includes a control transistor T11, the first output module includes a first output transistor T12, the second output module includes a second output transistor T13, a gate of the control transistor T11 is connected to the first node N1, a first pole of the control transistor T11 is connected to a fixed potential signal V1, a second pole of the control transistor T11 is connected to a gate of the second output transistor T13, a first pole of the second output transistor T13 is connected to the second clock signal CK2, a first pole of the second output transistor T13 is electrically connected to an output terminal OUT of the shift register, a first pole of the first output transistor T12 is connected to a fixed potential signal V1, and a second pole is connected to the output terminal OUT of the shift register. In the figure, the transistors are all N-type transistors, and the fixed potential signal V1 is at a low potential. When the first output transistor T12 is turned on, the control transistor T11 is turned on, and the fixed potential signal V1 is transmitted to the gate of the second output transistor T13, so that the second output transistor T13 is turned off, and the second clock signal CK2 is no longer transmitted to the output terminal OUT. If the threshold voltage of the second output transistor T13 is negatively floated, that is, the threshold voltage becomes a negative value, and the second clock signal CK2 is at a low potential, the second output transistor T13 is very easy to cause the voltage difference between the gate and the source of the second output transistor T13 to be greater than the threshold voltage of the second output transistor T13 because the potential of the gate is not low enough, so that the second output transistor T13 cannot be normally turned off, and when the first output transistor T11 is turned on, the output signal is affected by the fact that the second output transistor T13 cannot be turned off, which causes the output signal to be inaccurate, and the shift register operates abnormally.

Based on the above problems, an embodiment of the present invention provides a shift register, and fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention, referring to fig. 2, the shift register includes a first output control module 110, a second output control module 120, a first output module 130, and a second output module 140;

the first output control module 110 is configured to control transmission of the first input signal and the second input signal to the first node N1 according to the first clock signal CK1 and the start signal SIN; the first input signal includes the first clock signal CK1 or the first potential signal VGH.

The second input signal comprises a second clock signal CK2 or a second potential signal VGL 1;

the second output control module 120 is configured to control transmission of the third input signal and the third potential signal VGL2 to the second node N2 according to the start signal SIN and the potential of the first node N1; the third input signal is the start signal SIN or the first potential signal VGH; the second node N2 is electrically connected to the control terminal of the second output module 140;

the first output module 130 is configured to control transmission of the second potential signal VGL1 to the first output terminal OUT1 of the shift register according to the potential of the first node N1;

the second output module 140 is used for controlling the transmission of the second clock signal CK2 to the first output terminal OUT1 of the shift register according to the potential of the control terminal thereof;

the absolute value of the voltage of the third voltage signal VGL2 is greater than the absolute value of the voltage of the first voltage signal in the second clock signal CK2, wherein the first voltage signal of the second clock signal CK2 is either positive or negative with respect to the second voltage signal VGL1 and the third voltage signal VGL 2. The first potential signal VGH is opposite in sign to the second potential signal VGL1, and the first potential signal VGH is opposite in sign to the third potential signal VGL 2.

The first output control module 110 is configured to control transmission of the first input signal and the second input signal to the first node N1 according to the first clock signal CK1 and the start signal SIN, and may refer to that the first output control module 110 controls transmission of the first input signal to the first node N1 according to the first clock signal CK1, specifically, when the first clock signal CK1 is an active potential signal, the first output control module 110 transmits the first input signal to the first node N1; the first output control module 110 controls the transmission of the second input signal to the first node N1 according to the start signal SIN, the second input signal may be the second clock signal CK2 or the second potential signal VGL1, and specifically, when the start signal SIN is the active potential signal, the first output control module 110 transmits the second input signal to the first node N1.

The second output control module 120 is configured to control transmission of a third input signal and a third potential signal VGL2 to the second node N2 according to the start signal SIN, the potential of the first node N1, which may refer to the second output control module 120 controlling transmission of the third input signal to the second node N2 according to the start signal SIN, the third input signal may be the start signal SIN or the first potential signal VGH, and when the start signal SIN is an active potential signal, the second output control module 120 transmits the third input signal to the second node N2; and the second output control module 120 controls the transmission of the third voltage signal VGL2 to the second node N2 according to the voltage level of the first node N1, and when the voltage level signal of the first node N1 is the active voltage level signal, the second output control module 120 transmits the third voltage signal VGL2 to the second node N2.

The first output module 130 is configured to control transmission of the second potential signal VGL1 to the first output terminal OUT1 of the shift register according to the potential of the first node N1, which may mean that when the potential of the first node N1 is an active potential signal, the first output module 130 transmits the second potential signal VGL1 to the first output terminal OUT1 of the shift register.

The second output module 140 is used for controlling the transmission of the second clock signal CK2 to the first output terminal OUT1 of the shift register according to the voltage level of the control terminal thereof, which may mean that when the voltage level of the control terminal thereof of the second output module 140 is an active voltage signal, the second output module 140 transmits the second clock signal CK2 to the first output terminal OUT1 of the shift register.

In this embodiment, the control terminal of the second output module 140 is electrically connected to the second node N2, and the control terminal of the second output module 140 is electrically connected to the second node N2, which may be directly or indirectly (i.e., a switch element, such as a transistor, may be connected between the control terminal of the second output module 140 and the second node N2, and the switch element may be normally open). Therefore, when the potential of the second node N2 is the active potential signal, the potential of the control terminal of the second output module 140 is the active potential signal.

For example, in the present embodiment, the third potential signal VGL2 and the second potential signal VGL1 are both low, the first signal in the second clock signal CK2 is also low, the first potential signal VGH is high, accordingly, the transistor included in the second output module 140 is an N-type transistor (for example, an IGZO transistor), that is, when the control terminal of the second output module 140 is low, the second output module 140 is turned off. The zero potential is set as the ground potential, and in the embodiment and the following embodiments, the high potential is greater than the zero potential, and the low potential is less than the zero potential. When the transistors included in the second output module 140 are N-type transistors, the first signal is less than zero, i.e. the voltage value of the first signal is less than 0, and the voltage values of the second voltage signal VGL1 and the second voltage signal VGL2 are both less than 0. As the operation time of the shift register is prolonged, the threshold voltage of the transistor included in the second output module 140 may drift, and when the threshold voltage of the transistor included in the second output module 140 drifts negatively, the threshold voltage is a negative value, and if the voltage of the third potential signal VGL2 is greater than the low potential of the second clock signal CK2 or the voltage of the third potential signal VGL2 is equal to the low potential of the second clock signal CK2, the voltage difference between the gate and the source of the transistor included in the second output module 140 is greater than the threshold voltage, and the second output module 140 cannot be turned off. Therefore, when the third voltage signal VGL2 and the second voltage signal VGL1 are both low voltage, the first signal in the second clock signal CK2 is also low voltage, and when the absolute value of the voltage value of the third voltage signal VGL2 is greater than the absolute value of the voltage value of the first signal in the second clock signal CK2, the voltage value of the third voltage signal VGL2 is less than the voltage value of the first signal in the second clock signal CK2, the gate-source voltage difference of the transistor included in the second output module 140 is a negative value, so that even when the threshold voltage of the transistor included in the second output module 140 is negatively floated, the turn-off condition can be easily satisfied, and the second output module 140 is further ensured to be normally turned off. Therefore, the shift register in the present embodiment can tolerate a larger drift range of the threshold voltage. Specifically, in the present embodiment, when the potential of the first node N1 is the active potential, the first output module 130 is turned on to output the second potential signal VGL 1; and the second output control module 120 transmits the third potential signal VGL2 to the second node N2 according to the effective potential of the first node N1, as described above, by setting the absolute value of the voltage value of the third potential signal VGL2 to be greater than the absolute value of the voltage value of the first signal in the second clock signal CK2, when the first output module 130 is turned on to output the second potential signal VGL1, the second output module 140 can be normally turned off, thereby ensuring the accuracy of the output signal and improving the reliability of the shift register.

In the shift register provided in this embodiment, when the absolute value of the voltage value of the third voltage signal VGL2 is greater than the absolute value of the voltage value of the first signal in the second clock signal CK2, the second output module 140 can be normally turned off even if the threshold voltage of the switching device included in the second output module 140 drifts, and thus the first output module 130 is turned on to output the second voltage signal VGL1 without being affected by the second output module 140. Therefore, the shift register can tolerate a larger drift range of the threshold voltage, ensure that the second output module 140 can be normally turned off, and improve the reliability of the shift register.

With continued reference to fig. 2, optionally, the absolute value of the voltage value of the second potential signal VGL1 is less than or equal to the absolute value of the voltage value of the third potential signal VGL 2;

when the second potential signal VGL1 is equal to the third potential signal VGL2, the second potential signal VGL1 and the third potential signal VGL2 can be provided by the same circuit.

Optionally, the second input signal includes one of the second clock signal CK2, the second potential signal VGL1, and the third potential signal VGL 2.

When the second input signal is the second clock signal CK2, the first output control module 130 transmits the second clock signal CK2 to the first node N1 when the start signal SIN is the active level signal; when the second input signal is the second potential signal VGL1, the first output control module 130 transmits the second potential signal VGL1 to the first node N1 when the start signal SIN is the active potential signal; when the second input signal is the third potential signal VGL2, the first output control module 130 transmits the third potential VGL2 signal VGL2 to the first node N1 when the start signal SIN is the active potential signal.

Fig. 3 is a schematic structural diagram of another shift register provided in an embodiment of the present invention, and referring to fig. 3, optionally, the first output control module 110 includes a first output control unit 111 and a second output control unit 112;

the first output control unit 111 is configured to control transmission of the first input signal to the first node N1 according to the first clock signal CK 1;

the second output control unit 112 is configured to control transmission of the second input signal to the first node N1 according to the start signal SIN.

The first output control unit 111 is used for controlling the transmission of the first input signal to the first node N1 according to the first clock signal CK1, which may mean that when the first clock signal CK1 is an active potential signal, the first output control unit 111 transmits the first input signal (the first clock signal CK1 or the first potential signal VGH) to the first node N1. The second output control unit 112 is configured to control the transmission of the second input signal to the first node N1 according to the start signal SIN, which may mean that when the start signal SIN is an active potential signal, the second output control unit 112 transmits the second input signal to the first node N1. The second input signal in the present embodiment may be one of the second clock signal CK2, the second potential signal VGL1, and the third potential signal VGL 2.

With continued reference to fig. 3, optionally, the first output control unit 111 includes a first transistor T1, a gate of the first transistor T1 is connected to the first clock signal CK1, a first pole of the first transistor T1 is connected to the first input signal, and a second pole of the first transistor T1 is electrically connected to the first node N1;

the second output control unit 112 includes a second transistor T2, a gate of the second transistor T2 is connected to the start signal SIN, a first pole of the second transistor SIN is connected to the second input signal, and a second pole of the second transistor T2 is electrically connected to the first node N1;

the width-to-length ratio of the second transistor T2 is greater than that of the first transistor T1.

The first transistor T1 is turned on or off according to the first clock signal CK1, and when the first clock signal CK1 is an active potential signal, the first transistor T1 is turned on and transmits the first clock signal CK1 or the first potential signal VGH to the first node N1. The second transistor T2 is turned on or off according to the start signal SIN, and when the start signal SIN is an active potential signal, the second transistor T2 is turned on and transmits the second potential signal VGL1, the second clock signal CK2, or the third potential signal VGL2 to the first node N1. When the first clock signal CK1 and the start signal SIN are both active potential signals, that is, the first transistor T1 and the second transistor T2 are turned on simultaneously, since the aspect ratio of the second transistor T2 is greater than that of the first transistor T1, the degree to which the second transistor T2 writes the second input signal into the first node N1 is greater than that to which the first transistor T1 writes the first input signal into the first node N1, and therefore, the potential of the first node N1 is equal to the potential of the second input signal.

Fig. 4 is a schematic structural diagram of another shift register according to an embodiment of the present invention, and referring to fig. 4, optionally, the second output control module 120 includes a third output control unit 121 and a fourth output control unit 122;

the third output control unit 121 is configured to control transmission of the third input signal to the second node N2 according to the start signal SIN;

the fourth output control unit 122 is configured to control the transmission of the third potential signal VGL2 to the second node N2 according to the potential of the first node N1.

The third output control unit 121 is configured to control the transmission of the third input signal to the second node N2 according to the start signal SIN, which may mean that when the start signal SIN is an active potential signal, the third output control unit 121 transmits the third input signal to the second node N2. The fourth output control unit 122 is configured to control the transmission of the third potential signal VGL2 to the second node N2 according to the potential of the first node N1, which may mean that when the potential of the first node N1 is an active potential signal, the fourth output control unit 122 transmits the third potential signal VGL2 to the second node N2.

With continued reference to fig. 4, optionally, the third output control unit 121 includes a third transistor T3, a gate of the third transistor T3 is connected to the start signal SIN, a first pole of the third transistor T3 is connected to the third input signal, and a second pole of the third transistor T3 is electrically connected to the second node N2;

the fourth output control unit 122 includes a fourth transistor T4, a gate of the fourth transistor T4 is electrically connected to the first node N1, a first pole of the fourth transistor T4 is connected to the third potential signal VGL2, and a second pole of the fourth transistor T4 is electrically connected to the second node N2.

Specifically, the third transistor T3 is turned on or off according to the start signal, and when the start signal is the active potential signal, the third transistor T3 is turned on and transmits the third input signal to the second node N2. The fourth transistor T4 is turned on or off according to the potential of the first node N1, and when the potential of the first node N1 is the active potential signal, the fourth transistor T4 is turned on and transmits the third potential signal VGL2 to the second node N2.

Fig. 5 is a schematic structural diagram of another shift register provided in the embodiment of the present invention, and referring to fig. 5, optionally, the first output module 130 includes a fifth transistor T5 and a first capacitor C1;

a gate of the fifth transistor T5 is electrically connected to the first node N1 as a control terminal of the first output module 130, a first pole of the fifth transistor T5 is connected to the second potential signal VGL1, and a second pole of the fifth transistor T5 is electrically connected to the first output terminal OUT1 of the shift register;

a first end of the first capacitor C1 is electrically connected to the second potential signal VGL1, and a second end of the first capacitor C1 is electrically connected to the gate of the fifth transistor T5.

Specifically, the fifth transistor T5 turns on or off according to the potential of its gate, and when the potential of its gate is the active potential signal, the fifth transistor T5 turns on and transmits the second potential signal VGL1 to the first output terminal OUT1 of the shift register. The first capacitor C1 may store a gate potential of the fifth transistor T1.

Fig. 6 is a schematic structural diagram of another shift register provided in the embodiment of the present invention, and referring to fig. 6, optionally, the second output module 150 includes a sixth transistor T6 and a second capacitor C2;

a gate of the sixth transistor T6 is used as a control terminal of the second output module 140, a first pole of the sixth transistor T6 is connected to the second clock signal CK2, and a second pole of the sixth transistor T6 is electrically connected to the first output terminal OUT1 of the shift register;

the second capacitor C2 is used for coupling the potential of the gate of the sixth transistor T6 according to the transition of the second clock signal CK 2.

Specifically, the sixth transistor T6 turns on or off according to the potential of its gate, and when the potential of its gate is an active potential signal, the sixth transistor T6 turns on and transmits the second clock signal CK2 to the first output terminal OUT1 of the shift register. Optionally, a first end of the second capacitor C2 is electrically connected to the gate of the sixth transistor T6, a second end of the second capacitor C2 is connected to the second clock signal CK2, or a second end of the second capacitor C2 is electrically connected to the first output end OUT1 of the shift register. In the present embodiment, it is exemplarily shown that the second terminal of the second capacitor C2 is electrically connected to the first output terminal OUT1 of the shift register. The second capacitor C2 may store a potential of the gate of the sixth transistor T6, and the second capacitor C2 may also have a bootstrap function, when the sixth transistor T6 is turned on, the second clock signal CK2 is transmitted to the first output terminal OUT1 through the sixth transistor T6, when the second clock signal CK2 makes a transition, the first output signal of the first output terminal OUT1 also makes a transition, and when the first output signal of the first output terminal OUT1 of the shift register has a potential transition, the second capacitor C2 may couple a potential transition variable of the first output terminal OUT1 of the shift register to the gate of the sixth transistor T6. The second capacitor C2 is configured to enable the potential of the control terminal of the second output module 140 to change with a potential jump of the first output terminal OUT1 of the shift register, that is, with a potential jump of the second clock signal CK2, for example, when the high potential signal is an effective potential signal of the second output module 140, and the potential of the first output terminal OUT1 of the shift register jumps from a low potential signal to a high potential signal, the potential of the control terminal of the second output module 140 can be further increased, so as to ensure that the opening degree of the sixth transistor T6 included in the second output module 140 is relatively complete, thereby facilitating improvement of stability of the output signal.

With continued reference to fig. 6, optionally, the shift register further includes a seventh transistor T7, the second node N2 is electrically connected to the gate of the sixth transistor T6 through the seventh transistor T7, and the gate of the seventh transistor T7 is connected to the first potential signal VGH.

Specifically, the first potential signal VGH may be an active potential signal for the seventh transistor T7, so that the seventh transistor T7 is a normally-on transistor.

Fig. 7 is a schematic structural diagram of another shift register according to an embodiment of the present invention, referring to fig. 7, the shift register includes a first output control module 110, a second output control module 120, a first output module 130, and a second output module 140, where the first output control module 110 includes a first output control unit 111 and a second output control unit 112, the second output control module 120 includes a third output control unit 121 and a fourth output control unit 122, the first output control unit 111 includes a first transistor T1, the second output control unit 112 includes a second transistor T2, the third output control unit 121 includes a third transistor T3, the fourth output control unit 122 includes a fourth transistor T4, the first output module 130 includes a fifth transistor T5 and a first capacitor C1, and the second output module 140 includes a sixth transistor T6 and a second capacitor C2. The shift register further includes a seventh transistor T7. In fig. 7, each transistor is illustrated as an N-type transistor, and when each transistor is an N-type transistor (for example, an IGZO transistor), the second potential signal VGL1 and the third potential signal VGL2 are both low potential signals, the first potential signal VGH is a high potential signal, and the effective potential signals of the transistors are both high potential signals. The present embodiment exemplarily shows that the first input signal is the first clock signal CK1, the second input signal is the second potential signal VGL1, and the third input signal is the start signal SIN.

Fig. 8 is a timing diagram of an operation of a shift register according to an embodiment of the present invention, which can be applied to the shift register shown in fig. 7. Referring to fig. 7 and 8, the operation of the shift register includes a plurality of stages.

In the first stage T01, the first clock signal CK1 and the second clock signal CK2 are both high-level signals, the start signal SIN is a low-level signal, the first transistor T1 is turned on, the second transistor T2 is turned off, the first transistor N1 transmits the high-level signal to the first node N1, so that the fifth transistor T5 is turned on, the second-level signal VGL1 is transmitted to the first output terminal OUT1, and the first output terminal OUT1 outputs a low-level signal. The start signal SIN is a low-level signal, such that the third transistor T3 is turned off, the potential of the first node N1 is a high-level signal, such that the fourth transistor T4 is turned on, the fourth transistor T4 transmits the third potential signal VGL2 to the second node N2, and the normally-on seventh transistor T7 transmits a low-level signal at the second node N2 to the gate N3 of the sixth transistor T6, such that the sixth transistor T6 is turned off. The first stage t01 may be defined as an initialization stage, the display panel and the display apparatus generally include a gate driving circuit, the gate driving circuit includes a plurality of cascaded shift registers, each shift register may be connected to at least one row of pixel circuits in the display panel, when the gate driving circuit including the shift register is applied to the display panel and the display apparatus, the first stage t01 may correspond to a power-on stage of the display apparatus, and the first output terminals OUT1 of all the shift registers output a low potential, which may correspond to an inactive potential for driving the pixel circuits, so that the pixel circuits cannot drive the light emitting devices to work, thereby completing initialization of the display panel and improving display effect after power-on.

In the second stage T02, the start signal SIN is a low-level signal, the second transistor T2 and the third transistor T3 are turned off, when the first clock signal CK1 has a high-level signal, the first transistor T1 is turned on when the first clock signal CK1 is a high-level signal, and transmits the high-level signal to the first node N1, and the high-level signal of the first node N1 is stored in the first capacitor C1, so that the first transistor T1 is turned off due to the first clock signal CK1 being a low-level signal, and the potential signal of the first node N1 is still kept at a high level when the second transistor T2 is turned off. When the first node N1 is at a high level, the fourth transistor T4 is turned on and transmits the third potential signal VGL2 to the second node N2, and the sixth transistor T6 is turned off because the gate N3 thereof is at a low level. The fifth transistor T5 is turned on due to the first node N1 being high, so as to transmit the second potential signal VGL1 to the first output terminal OUT1 of the shift register. That is, in the second stage t02, the first output terminal OUT1 of the shift register outputs a low potential. When the fourth transistor T4 is turned on and transmits the third potential signal VGL2 to the gate N3 of the sixth transistor T6 to turn off the sixth transistor T6, and the second clock signal CK2 is a low potential signal, and as the use time of the shift register is prolonged, when the threshold voltage Vth of the sixth transistor T6 is negatively floated and the threshold voltage Vth is a negative value, if the voltage of the third potential signal VGL2 is greater than the low potential of the second clock signal CK2 or the voltage of the third potential signal VGL2 is equal to the low potential of the second clock signal CK2, the gate-source voltage difference Vgs of the sixth transistor T6 is greater than the threshold voltage Vth of the sixth transistor T6, and the sixth transistor T6 cannot be turned off. Therefore, when the absolute value of the voltage value of the third potential signal VGL2 is greater than the absolute value of the voltage value of the first signal in the second clock signal CK2 (i.e., the voltage value of the third potential signal VGL2 is less than the voltage value of the first signal in the second clock signal CK 2), the gate-source voltage difference Vgs of the sixth transistor T6 is a negative value, so that even if the threshold voltage Vth of the sixth transistor T6 is negatively floated, the turn-off condition can be more easily satisfied, and the sixth transistor T6 is normally turned off. Therefore, the shift register in the present embodiment can tolerate a larger drift range of the threshold voltage. Specifically, in the present embodiment, when the potential of the first node N1 is an active potential, i.e., a high potential, the fifth transistor T5 is turned on, and the second potential signal VGL1 is output; and the fourth transistor T4 transmits the third potential signal VGL2 to the second node N2 according to the effective potential of the first node N1, as described above, by setting the absolute value of the voltage value of the third potential signal VGL2 to be greater than the absolute value of the voltage value of the first signal in the second clock signal CK2, when the fifth transistor T5 is turned on to output the second potential signal VGL1, the sixth transistor T6 can be normally turned off, thereby ensuring the accuracy of the output signal and improving the reliability of the shift register.

In other embodiments, when the transistors of the shift register are all P-type transistors, the threshold voltage of the transistors is negative, and the threshold voltage is prone to positive drift. The P-type transistor is turned on when the gate-source voltage difference Vgs is less than or equal to the threshold voltage of the transistor, and correspondingly, is turned off when the gate-source voltage difference Vgs is greater than the threshold voltage of the transistor. When the transistors of the shift register are all P-type transistors, the second voltage signal VGL1 and the third voltage signal VGL2 are both high voltage signals, and the first voltage signal VGH is a low voltage signal. If the zero potential is set as the ground potential, when the transistors of the shift register are all P-type transistors, the first signal is greater than the zero potential, i.e., the voltage value of the first signal is greater than 0, and the voltage values of the second potential signal VGL1 and the third potential signal VGL2 are also greater than 0. When the absolute value of the voltage value of the third voltage signal VGL2 is greater than the absolute value of the voltage value of the first signal in the second clock signal CK2, (i.e., the voltage value of the third voltage signal VGL2 is greater than the voltage value of the first signal in the second clock signal CK 2), the gate-source voltage difference Vgs of the sixth transistor T6 is a positive value, so that even if the threshold voltage Vth of the sixth transistor T6 is shifted, compared to the case where the voltage value of the third voltage signal VGL2 is less than or equal to the voltage value of the first signal in the second clock signal CK2, the turn-off condition can be more easily satisfied, and the sixth transistor T6 is ensured to be normally turned off.

In the third stage T03, the first clock signal CK1 is a high-level signal, so that the first transistor T1 is turned on, the start signal SIN is a high-level signal, so that the second transistor T2 and the third transistor T3 are turned on, the first transistor T1 transmits the first clock signal CK1 to the first node N1, and the second transistor T2 transmits the second potential signal VGL1 to the first node N1, since the width-to-length ratio of the second transistor T2 is greater than that of the first transistor T1, the signal at the first node N1 is finally the second potential signal VGL1, i.e. a low-level, and the fifth transistor T5 and the fourth transistor T4 are turned off. The turned-on third transistor T3 transmits the start signal SIN to the gate N3 of the sixth transistor T6 through the seventh transistor T7, so that the sixth transistor T6 is turned on, the turned-on sixth transistor T6 transmits the second clock signal CK2 to the first output terminal OUT1 of the shift register, and the second clock signal CK2 is a low-level signal, so that the first output terminal OUT1 of the shift register outputs a low-level signal in the third stage T03.

In the fourth stage T04, the first clock signal CK1 is at a low level, the first transistor T1 is turned off, the start signal SIN is at a low level, the second transistor T2 and the third transistor T3 are turned off, and the first node N1 keeps at the low level in the previous stage, so the fourth transistor T4 and the fifth transistor T5 are turned off. The gate N3 of the sixth transistor T6 maintains the high level at the previous stage, so that the sixth transistor T6 continues to be turned on, and the second clock signal CK2 transits to the high level signal at the fourth stage T04, the sixth transistor T6 transmits the second clock signal CK2 to the first output terminal OUT1 of the shift register, and the first output terminal OUT1 of the shift register outputs the high level. When the first output terminal OUT1 jumps from the low potential to the high potential, due to the coupling effect of the second capacitor C2, the potential of the gate N3 of the sixth transistor T6 is increased, so that the sixth transistor T6 enters the deep linear region, the sixth transistor T6 is turned on more thoroughly, the capability of the sixth transistor T6 to transmit the second clock signal CK2 is improved, and the high potential output by the first output terminal OUT1 is kept well.

In the fifth phase T05, the first clock signal CK1 becomes a high level signal, the first transistor T1 is turned on and transmits the first clock signal CK1 to the first node N1. The start signal SIN is a low signal, the second transistor T2 and the third transistor T3 are turned off, since the first node N1 is a high signal, the fourth transistor T4 is turned on, the fifth transistor T5 is turned on, the fourth transistor T4 transmits the third potential signal VGL2 to the gate N3 of the sixth transistor T6 through the seventh transistor T7, and the sixth transistor T6 is turned off. The turned-on fifth transistor T5 transmits the second potential signal VGL1 to the first output terminal OUT1 of the shift register, and thus, the first output terminal OUT1 of the shift register outputs a low potential signal. In the fifth stage T05, the gate N3 of the sixth transistor T6 is the third potential signal VGL2, and the second clock signal CK2 is the first signal, i.e., the low potential signal, when the absolute value of the voltage value of the third potential signal VGL2 is greater than the absolute value of the voltage value of the first signal in the second clock signal CK2 (i.e., the voltage value of the third potential signal VGL2 is less than the voltage value of the first signal in the second clock signal CK 2), the gate-source voltage difference Vgs of the sixth transistor T6 is a negative value, so that even if the threshold voltage Vth of the sixth transistor T6 is negatively floated, the turn-off condition can be more easily satisfied, and the normal turn-off of the sixth transistor T6 is ensured. Therefore, the shift register in the present embodiment can tolerate a larger drift range of the threshold voltage. Specifically, in the present embodiment, when the potential of the first node N1 is an active potential, i.e., a high potential, the fifth transistor T5 is turned on, and the second potential signal VGL1 is output; and the fourth transistor T4 transmits the third potential signal VGL2 to the second node N2 according to the effective potential of the first node N1, as described above, by setting the absolute value of the voltage value of the third potential signal VGL2 to be greater than the absolute value of the voltage value of the first signal in the second clock signal CK2, when the fifth transistor T5 is turned on to output the second potential signal VGL1, the sixth transistor T6 can be normally turned off, thereby ensuring the accuracy of the output signal and improving the reliability of the shift register.

In this embodiment, the transistors in the shift register may be IGZO transistors, and thus the transistors in the pixel circuit may also be a display panel of IGZO transistors, so as to ensure that the leakage current of the pixel circuit is small, improve the display effect of the display panel, and simultaneously enable the shift register to tolerate a larger drift range of the threshold voltage, and improve the reliability of the shift register.

Fig. 9 is a schematic structural diagram of another shift register according to an embodiment of the present invention, and referring to fig. 9, the shift register further includes a third output module 150 and a fourth output module 160;

the control terminal of the third output module 150 is electrically connected to the first node N1, and the third output module 150 is configured to control the transmission of the third voltage signal VGL2 to the second output terminal OUT2 of the shift register according to the voltage level of the first node N1;

the control terminal of the fourth output module 160 is electrically connected to the second node N2, and the fourth output module 160 is used for controlling the transmission of the second clock signal CK2 to the second output terminal OUT2 of the shift register according to the potential of the control terminal thereof.

The third output module 150 is configured to control transmission of the third potential signal VGL2 to the second output terminal OUT2 of the shift register according to the potential of the first node N1, which may mean that when the potential of the first node N1 is an active potential signal, the third output module 150 transmits the third potential signal VGL2 to the second output terminal OUT2 of the shift register. The fourth output module 160 is configured to control the transmission of the second clock signal CK2 to the second output terminal OUT2 of the shift register according to the voltage level of its control terminal, and may refer to when the voltage level of the control terminal of the fourth output module 160 is an active voltage level signal, the fourth output module 160 transmits the second clock signal CK2 to the second output terminal OUT2 of the shift register. The control terminal of the fourth output module 160 is electrically connected to the second node N2, and the control terminal of the fourth output module 160 is electrically connected to the second node N2, which may be directly or indirectly (i.e., a switch element, such as a transistor, may be connected between the control terminal of the fourth output module 160 and the second node N2, and the switch element may be normally open). Therefore, when the potential of the second node N2 is the active potential signal, the potential of the control terminal of the fourth output module 160 is the active potential signal. In this embodiment, the control terminal of the fourth output module 160 is electrically connected to the second node N2 through the seventh transistor T7.

With reference to fig. 9, optionally, a first terminal of the second capacitor C2 is electrically connected to the control terminal of the second output module 140, a second terminal of the second capacitor C2 is electrically connected to the first output terminal OUT1 of the shift register, a second terminal of the second capacitor C2 is electrically connected to the second output terminal OUT2 of the shift register, or a second terminal of the second capacitor C2 is connected to the second clock signal CK 2.

The second capacitor C2 can couple the gate voltage of the sixth transistor according to the second clock signal CK2, the signal of the first output terminal OUT1 of the shift register, or the transition of the signal of the second output terminal OUT2 of the shift register, so as to improve the driving capability of the sixth transistor T6.

With continued reference to fig. 9, optionally, the third output module 150 includes an eighth transistor T8, a gate of the eighth transistor T8 is used as a control terminal of the third output module 150, a first pole of the eighth transistor T8 is electrically connected to the third potential signal VGL2, and a second pole of the eighth transistor T8 is electrically connected to the second output terminal OUT2 of the shift register;

the fourth output block 160 includes a ninth transistor T9, a gate of the ninth transistor T9 is used as a control terminal of the fourth output block 160, a first pole of the ninth transistor T9 is electrically connected to the second clock signal CK2, and a second pole of the ninth transistor T9 is electrically connected to the second output terminal OUT2 of the shift register.

Specifically, the eighth transistor T8 turns on or off according to the potential of its gate, and when the potential of its gate is an active potential signal, the eighth transistor T8 turns on and transmits the third potential signal VGL2 to the second output terminal OUT2 of the shift register. The ninth transistor T9 is turned on or off according to the potential of its gate, and when the potential of its gate is an active potential signal, the ninth transistor T9 is turned on and transmits the second clock signal CK2 to the second output terminal OUT2 of the shift register.

In this embodiment, the on/off states of the third output module 150 and the first output module 130 are the same, and the on/off states of the fourth output module 160 and the second output module 140 are the same, which is not described herein again. When the shift register is applied to a gate driving circuit to drive the pixel circuits of the display panel, the gate driving circuit may include at least two cascaded stages of shift registers, a signal output by the first output terminal OUT1 of the shift register may be connected to the pixel circuits of a corresponding row, and a signal output by the first output terminal OUT1 of the shift register may also be used as a start signal SIN of a next stage of the shift register; or the signal output by the first output terminal OUT1 of the shift register may be connected to the pixel circuits of the corresponding row, and the signal output by the second output terminal OUT2 of the shift register is used as the start signal SIN of the next stage of shift register. When the signal output by the first output end OUT1 of the shift register can be connected to the pixel circuit of the corresponding row, and the signal output by the second output end OUT2 of the shift register is used as the start signal SIN of the next shift register, the signal output by the second output end OUT2 of the shift register is only transmitted to the next shift register, and the second output end OUT2 of the shift register does not need to drive the pixel circuit, so that the load is small, the jump edge is fast, the stable operation of the next shift register is facilitated, and the problem of gradual degradation of the signal output by the output end of the shift register is further improved.

With continued reference to fig. 9, optionally, the absolute value of the voltage value of the first voltage signal VGH is greater than the absolute value of the voltage value of the second signal in the second clock signal CK2, wherein the second signal of the second clock signal CK2 is the same as positive or the same as negative of the first voltage signal VGH;

in this embodiment, the first voltage signal VGH is high, the second signal of the second clock signal CK2 is also high, and the zero voltage is set to the ground voltage, so that the second signal is greater than the zero voltage when the transistor included in the second output module 140 is an N-type transistor. When the first electrode of the third transistor T3 is connected to the first potential VGH signal, the third transistor T3 is turned on, and the first potential signal VGH is transmitted to the gate N3 of the sixth transistor T6, so that the sixth transistor T6 is turned on, the sixth transistor T6 transmits the second clock signal CK2 to the first output terminal OUT1, an absolute value of a voltage value of the first potential signal VGH is greater than an absolute value of a voltage value of the second signal in the second clock signal CK2, so that the on condition of the sixth transistor T6, that is, Vgs is greater than or equal to Vth, can be satisfied more easily, it is ensured that the sixth transistor T6 can be turned on normally, and the absolute value of the voltage value of the first potential signal VGH is greater, so that when the sixth transistor T6 is turned on, the on degree is greater, and the driving capability of the sixth transistor T6 is improved.

Fig. 10 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention, and referring to fig. 10, the gate driving circuit includes a shift register 01 according to any one of the above embodiments, the gate driving circuit includes at least two shift registers 01 connected in series, each shift register includes a start signal input terminal ASIN, in two adjacent shift registers 01, a first output signal of a first output terminal OUT1 of a previous shift register serves as a start signal accessed to the start signal input terminal ASIN of a next shift register 01, or a second output signal of a second output terminal OUT2 of the previous shift register 01 serves as a start signal accessed to the start signal input terminal ASIN of the next shift register 01. This embodiment exemplarily shows a case where the first output terminal OUT1 of the shift register is connected to the pixel circuits of the corresponding row, and the second output terminal OUT2 of the shift register outputs the second output signal as the start signal SIN of the next stage of the shift register.

Referring to fig. 11, the display panel includes the gate driving circuit in the above embodiment, and further includes a first clock signal line CLK1, a second clock signal line CLK2, an input signal line a1, and a pixel circuit 02, wherein a shift register 01 is used for driving a row of pixel circuits 02, the first clock signal line CLK1 is connected to a first clock signal terminal L1 of an odd-numbered shift register 01, and a second clock signal terminal L2 of an even-numbered shift register 01. The second clock signal line CLK2 connects the second clock signal terminal L2 of the odd-numbered line shift register 01 and the first clock signal terminal L1 of the even-numbered line shift register 01. The first clock signal terminal L1 is used for receiving the first clock signal, and the second clock signal terminal L2 is used for receiving the second clock signal. The input signal line a1 is connected to the start signal input terminal ASIN of the first polar shift register 01 for providing the start signal of the first polar shift register 01. The case of including the even row shift register 01 is exemplarily shown in fig. 11.

An embodiment of the present invention further provides a driving method of a shift register, which is used for driving the shift register in any of the above embodiments, fig. 12 is a flowchart of the driving method of the shift register provided in the embodiment of the present invention, and referring to fig. 12, the driving method of the shift register includes:

s101: providing a first clock signal, a start signal, a first input signal and a second input signal to a first output control module, so that the first output control module controls the transmission of the first input signal and the second input signal to a first node according to the first clock signal and the start signal; the first input signal comprises a first clock signal or a first potential signal; the second input signal comprises a second clock signal or a second potential signal;

s102: providing the start signal, the third input signal and the third potential signal to the second output control module, so that the second output control module controls the transmission of the third input signal and the third potential signal to the second node according to the start signal and the potential of the first node; the third input signal is an initial signal or a first potential signal; the second node is electrically connected with the control end of the second output module;

s103: the first output module controls the transmission of the second potential signal to the first output end of the shift register according to the potential of the first node;

s104: the second output module controls the transmission of a second clock signal to the first output end of the shift register according to the potential of the control end of the second output module;

The driving method of the shift register provided in the embodiment of the present invention is used to drive the shift register provided in any of the embodiments, and therefore, the driving method of the shift register has the same beneficial effects as those of the shift register in the embodiments, and details are not repeated here.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A shift register, comprising: the device comprises a first output control module, a second output control module, a first output module and a second output module;

the first output control module is used for controlling the transmission of a first input signal and a second input signal to a first node according to a first clock signal and a starting signal; the first input signal comprises the first clock signal or a first potential signal; the second input signal comprises a second clock signal or a second potential signal;

the second output control module is used for controlling transmission of a third input signal and a third potential signal to a second node according to the starting signal and the potential of the first node; the third input signal is an initial signal or a first potential signal; the second node is electrically connected with the control end of the second output module;

the second output module is used for controlling the transmission of the second clock signal to the first output end of the shift register according to the potential of the control end of the second output module;

the absolute value of the voltage value of the third potential signal is greater than the absolute value of the voltage value of the first signal in the second clock signal, wherein the first signal of the second clock signal is the same as the second potential signal and the third potential signal.

2. The shift register according to claim 1, wherein an absolute value of a voltage value of the second potential signal is smaller than or equal to an absolute value of a voltage value of the third potential signal;

preferably, the second input signal includes one of the second clock signal, the second potential signal, and the third potential signal.

3. The shift register according to claim 1 or 2, wherein the first output control module includes a first output control unit and a second output control unit;

the first output control unit is used for controlling the transmission of the first input signal to the first node according to the first clock signal;

4. The shift register according to claim 3, wherein the first output control unit comprises a first transistor, a gate of the first transistor is connected to the first clock signal, a first pole of the first transistor is connected to the first input signal, and a second pole of the first transistor is electrically connected to the first node;

the second output control unit comprises a second transistor, the grid electrode of the second transistor is connected with the starting signal, the first pole of the second transistor is connected with the second input signal, and the second pole of the second transistor is electrically connected with the first node;

5. The shift register according to claim 1, wherein the second output control module includes a third output control unit and a fourth output control unit;

the third output control unit is used for controlling the transmission of the third input signal to the second node according to the starting signal;

the fourth output control unit is used for controlling the transmission of the third potential signal to the second node according to the potential of the first node;

preferably, the third output control unit includes a third transistor, a gate of the third transistor is connected to the start signal, a first pole of the third transistor is connected to the third input signal, and a second pole of the third transistor is electrically connected to the second node;

the fourth output control unit comprises a fourth transistor, a gate of the fourth transistor is electrically connected with the first node, a first pole of the fourth transistor is connected to the third potential signal, and a second pole of the fourth transistor is electrically connected with the second node.

6. The shift register according to claim 1, wherein the first output block includes a fifth transistor and a first capacitor;

a gate of the fifth transistor is electrically connected to the first node as a control end of the first output module, a first pole of the fifth transistor is connected to the second potential signal, and a second pole of the fifth transistor is electrically connected to the first output end of the shift register;

7. The shift register according to claim 1, wherein the second output block includes a sixth transistor and a second capacitor;

a gate of the sixth transistor is used as a control end of the second output module, a first pole of the sixth transistor is connected to the second clock signal, and a second pole of the sixth transistor is electrically connected with the first output end of the shift register;

the second capacitor is used for coupling the potential of the grid electrode of the sixth transistor according to the transition of the second clock signal;

preferably, the shift register further includes a seventh transistor, the second node is electrically connected to a gate of the sixth transistor through the seventh transistor, and the gate of the seventh transistor is connected to the first potential signal.

8. The shift register according to any one of claims 1, 2, and 7, further comprising a third output module and a fourth output module;

the control end of the third output module is electrically connected with the first node, and the third output module is used for controlling the transmission of the third potential signal to the second output end of the shift register according to the potential of the first node;

the control end of the fourth output module is electrically connected with the second node, and the fourth output module is used for controlling the transmission of the second clock signal to the second output end of the shift register according to the control end potential;

preferably, an absolute value of a voltage value of the first potential signal is greater than an absolute value of a voltage value of a second signal in the second clock signal, wherein the second signal of the second clock signal is the same as the first potential signal in positive or negative;

preferably, a first end of a second capacitor is electrically connected to the control end of the second output module, a second end of the second capacitor is electrically connected to the first output end of the shift register, or a second end of the second capacitor is electrically connected to the second output end of the shift register, or a second end of the second capacitor is connected to the second clock signal;

preferably, the third output module includes an eighth transistor, a gate of the eighth transistor is used as a control terminal of the third output module, a first pole of the eighth transistor is electrically connected to the third potential signal, and a second pole of the eighth transistor is electrically connected to the second output terminal of the shift register;

the fourth output module comprises a ninth transistor, a gate of the ninth transistor is used as a control end of the fourth output module, a first pole of the ninth transistor is electrically connected with the second clock signal, and a second pole of the ninth transistor is electrically connected with the second output end of the shift register.

9. A gate driving circuit, comprising the shift register of any one of claims 1 to 8, wherein the gate driving circuit comprises at least two shift registers connected in series, and the shift registers comprise start signal input terminals, and in two adjacent stages of the shift registers, a first output signal of a first output terminal of a previous stage of the shift register is used as a start signal accessed to a start signal input terminal of a next stage of the shift register, or a second output signal of a second output terminal of a previous stage of the shift register is used as a start signal accessed to a start signal input terminal of a next stage of the shift register.

10. A method for driving a shift register according to any one of claims 1 to 8, the method comprising:

providing a first clock signal, a start signal, a first input signal and a second input signal to a first output control module, so that the first output control module controls the transmission of the first input signal and the second input signal to a first node according to the first clock signal and the start signal; the first input signal comprises the first clock signal or a first potential signal; the second input signal comprises a second clock signal or a second potential signal;

providing the start signal, a third input signal and a third potential signal to a second output control module, so that the second output control module controls the transmission of the third input signal and the third potential signal to a second node according to the start signal and the potential of the first node; the third input signal is an initial signal or a first potential signal; the second node is electrically connected with the control end of the second output module;

the first output module controls the transmission of the second potential signal to a first output end of the shift register according to the potential of the first node;

the second output module controls the transmission of the second clock signal to the first output end of the shift register according to the potential of the control end of the second output module;