CN112865495B - Ramp generating circuit and control method - Google Patents
Ramp generating circuit and control method Download PDFInfo
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- CN112865495B CN112865495B CN202110038219.0A CN202110038219A CN112865495B CN 112865495 B CN112865495 B CN 112865495B CN 202110038219 A CN202110038219 A CN 202110038219A CN 112865495 B CN112865495 B CN 112865495B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
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Abstract
The invention provides a slope generating circuit and a control method, wherein a voltage signal of an SW switch node is a signal which is formed by chopping an input voltage with a fixed duty ratio and is related to an input voltage and an output voltage, a high-frequency component is filtered out by using the voltage signal after the voltage signal passes through a low-pass filter circuit, a voltage value which is in direct proportion to the output voltage is obtained after the voltage signal is reduced, the voltage value is converted into a current by an operational amplifier, a capacitor is controlled to charge and discharge by a pulse switch signal synchronous with the switch signal, and the generated slope current is mirrored to obtain a self-adaptive slope voltage. The invention can be well adapted to the conditions of wide input voltage range and multiple output versions, so that the use of DC-DC products is more flexible; the obtained slope compensation voltage has following characteristics. And simultaneously, a PMOS input differential pair is adopted, so that a wider input common mode level range is adapted.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to an adaptive ramp generating circuit in a peak current control mode.
Background
With the development of social productivity, a large number of power management chips are needed in various electronic devices and industrial products to reduce energy dissipation, and peak current mode control is widely used in DC-DC products, wherein the key of the control mode is to sample compensation ramp voltage generated by inductor current, and most of ramp compensation circuits in products in the market have the defects that the compensation ramp value is fixed and cannot flexibly change along with output voltage and converter duty ratio, so that the designed ramp circuit has over-compensation or under-compensation conditions, the waveform of the output inductor current is unstable, the output voltage is unstable, and the good power supply requirement of application equipment cannot be met.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a ramp generating circuit and a control method, and provides an adaptive ramp generating circuit with wide input swing after the general thought of designing the ramp circuit is adopted.
The technical scheme adopted for solving the technical problems is as follows:
A ramp generating circuit as shown in fig. 1: the MOS transistor comprises P-channel enhancement type MOS transistors PM1-PM8, N-channel enhancement type MOS transistors NM1-NM8, capacitors C1-C3, resistors R1-R6, a current source IDC1, a VDD input port, a SW input port and a GND port;
The VDD port is connected with an external power supply; the SW port is connected with a switch Guan Jiedian connected with the inductor; the VPULSE port is connected with a switch MOS tube related to a clock to generate a pulse signal of ramp voltage; the ISLOPE port is connected with a current mirror for outputting a slope current, and a slope voltage is generated on the resistor; the GND port is connected to the ground potential.
The source electrode of the P channel enhancement type MOS tube PM1 is connected with the source electrodes of the current sources IDC1 and PM2, the grid electrode is connected with one end of the resistor R4 and the upper polar plate of the capacitor C2, and the drain electrode is connected with the drain electrode of the NM1, the grid electrode and the grid electrode of the NM 4; the source electrode of the P channel enhancement type MOS tube PM2 is connected with the source electrodes of the current sources IDC1 and PM1, the grid electrode is connected with one end of the resistor R5 and the source electrode of the NM5, and the drain electrode is connected with the drain electrode of the NM2, the grid electrode and the grid electrode of the NM 3; the main role of the PM1 and PM2 is as an input differential pair of voltage-to-current conversions. The source electrode of the P channel enhancement type MOS tube PM3 is connected with VDD, the grid electrode is connected with the drain electrode and the grid electrode of PM4, and the drain electrode is connected with the drain electrode of NM 3; the source electrode of the P channel enhancement type MOS tube PM4 is connected with VDD, the grid electrode is connected with the grid electrode of PM3, and the drain electrode is connected with the drain electrode of NM4 and the grid electrode of NM 5; the source electrode of the P channel enhancement type MOS tube PM5 is connected with VDD, and the grid electrode is connected with the drain electrode, the NM5 drain electrode and the PM6 grid electrode; the source electrode of the P channel enhancement type MOS tube PM6 is connected with VDD, the grid electrode is connected with the grid electrode of PM5, and the drain electrode is connected with the drain electrode of NM6, the grid electrode and the grid electrode of NM 8; the source electrode of the P channel enhancement type MOS tube PM7 is connected with VDD, and the grid electrode is connected with the drain electrode, the NM8 drain electrode and the PM8 grid electrode; the source electrode of the P channel enhancement type MOS tube PM8 is connected with VDD, the grid electrode is connected with the grid electrode and the drain electrode of PM7, the NM8 drain electrode is connected with ISLOPE ports. The main role of the PM3-PM8 is as a current mirror.
The drain electrode of the N-channel enhancement MOS tube NM1 is connected with the grid electrode, the drain electrode of the PM1 and the grid electrode of the NM4, and the source electrode of the NM1 is connected with GND; the drain electrode of the N-channel enhancement MOS tube NM2 is connected with the grid electrode, the grid electrode of NM3 and the drain electrode of PM2, and the source electrode is connected with GND; the grid electrode of the N-channel enhancement type MOS tube NM3 is connected with the grid electrode and the drain electrode of NM2 and the drain electrode of PM2, the drain electrode is connected with the drain electrode and the grid electrode of PM3 and the grid electrode of PM4, and the source electrode is connected with GND; the grid electrode of the N-channel enhancement type MOS tube NM4 is connected with the grid electrode of the NM1, the drain electrode is connected with the drain electrode of the PM4 and the grid electrode of the NM5, and the source electrode is connected with the GND; the drain electrode of the N-channel enhancement MOS tube NM5 is connected with the drain electrode of the PM5, the grid electrode of the PM6 and the grid electrode of one end PM2 of the resistor R5; the N-channel enhancement type MOS transistors NM1-NM4 are mainly used as current mirror loads of amplifiers, and the N-channel enhancement type MOS transistor NM5 is mainly used as an output buffer stage of a transconductance operational amplifier. The drain electrode of the N-channel enhancement MOS tube NM6 is connected with the grid electrode, the drain electrode of the PM6 and the grid electrode of the NM8, and the source electrode is connected with the drain electrode of the NM7 and the upper polar plate of the capacitor C3; the grid electrode of the N-channel enhancement type MOS tube NM7 is connected with a VPULSE port, and the source electrode is connected with a GND port; the grid electrode of the N-channel enhancement type MOS tube NM8 is connected with the grid electrode, the drain electrode and the PM6 drain electrode of the NM6, the drain electrode is connected with the grid electrode, the drain electrode and the grid electrode of the PM7, and the source electrode is connected with one end of the resistor R6. The N-channel enhancement type MOS transistors NM6-NM8 mainly have the function of generating slope voltage through switching signal pulse.
The upper polar plate of the capacitor C1 is connected with one ends of R3 and R4, and the lower polar plate is connected with GND; the upper polar plate of the capacitor C2 is connected with one end of the R4 and the PM1 grid electrode, and the lower polar plate is connected with the GND. The main function of the capacitors C1, C2 is to filter out high frequency components.
One end of the resistor R1 is connected with the SW port, and the other end of the resistor R1 is connected with one ends of the resistors R3 and R2 respectively; one end of the resistor R2 is connected with the other end of the resistor R1, and the other end of the resistor R2 is connected with GND. The resistors R1, R2 have the main function of stepping down a relatively high output voltage to within the common-mode input range of the PMOS differential pair. The resistors R3, R4 mainly function to form a low-pass filter together with the capacitance. One end of the resistor R5 is connected with the source electrode of the NM5 and the grid electrode of the PM2, and the other end of the resistor R5 is connected with the GND, and is mainly used for converting voltage quantity related to output voltage into current. One end of the resistor R6 is connected with the source electrode of the NM8, and the other end of the resistor R6 is connected with the GND, and the resistor R is mainly used for linearizing the voltage-current relationship of the NM8 to obtain a slope current.
The invention also provides a control method of the slope generating circuit, which comprises the following specific steps:
The voltage signal of the SW switch node is a signal which is formed by chopping an input voltage with a fixed duty ratio through a switch and is related to both input and output voltages, the voltage signal is utilized to filter high-frequency components after passing through a low-pass filter circuit, a voltage value which is in direct proportion to the output voltage is obtained after voltage reduction, the voltage value is converted into current through an operational amplifier, the capacitor is controlled to charge and discharge by a pulse switch signal synchronous with the switch signal, and the generated slope current is mirrored to obtain a self-adaptive slope voltage.
The invention has the beneficial effects that:
1. The slope voltage generated by the slope compensation circuit is positively correlated with the output voltage, so that the device can be well adapted to the conditions of wide input voltage range and multiple output versions, and the use of a DC-DC product is more flexible.
2. The voltage is converted into current by using a 2-stage transconductance operational amplifier and an output stage, the conversion precision is higher by using the 2-stage transconductance operational amplifier, and the obtained slope compensation voltage has following characteristics. And simultaneously, a PMOS input differential pair is adopted, so that a wider input common mode level range is adapted.
Drawings
Fig. 1 is a schematic diagram of an adaptive ramp generation circuit in a peak current control mode according to the present invention.
Detailed Description
The invention will be further described with reference to the drawings and examples.
The present invention will be described in further detail with reference to fig. 1. As shown in FIG. 1, the adaptive ramp generating circuit in the peak current control mode comprises P-channel enhancement MOS transistors PM1-PM8, N-channel enhancement MOS transistors NM1-NM8, capacitors C1-C3, resistors R1-R6, a current source IDC1, a VDD input port, a SW input port and a GND port. The VDD port is connected with an external power supply; the SW port is connected with a switch Guan Jiedian connected with the inductor; the VPULSE port is connected with a switch MOS tube related to a clock to generate a pulse signal of ramp voltage; the ISLOPE port is connected with a current mirror for outputting a slope current, and a slope voltage is generated on the resistor; the GND port is connected to the ground potential.
The source electrode of the P channel enhancement type MOS tube PM1 is connected with the source electrodes of the current sources IDC1 and PM2, the grid electrode is connected with one end of the resistor R4 and the upper polar plate of the capacitor C2, and the drain electrode is connected with the drain electrode of the NM1, the grid electrode and the grid electrode of the NM 4; the source electrode of the P channel enhancement type MOS tube PM2 is connected with the source electrodes of the current sources IDC1 and PM1, the grid electrode is connected with one end of the resistor R5 and the source electrode of the NM5, and the drain electrode is connected with the drain electrode of the NM2, the grid electrode and the grid electrode of the NM 3; the main role of the PM1 and PM2 is as an input differential pair of voltage-to-current conversions. The source electrode of the P channel enhancement type MOS tube PM3 is connected with VDD, the grid electrode is connected with the drain electrode and the grid electrode of PM4, and the drain electrode is connected with the drain electrode of NM 3; the source electrode of the P channel enhancement type MOS tube PM4 is connected with VDD, the grid electrode is connected with the grid electrode of PM3, and the drain electrode is connected with the drain electrode of NM4 and the grid electrode of NM 5; the source electrode of the P channel enhancement type MOS tube PM5 is connected with VDD, and the grid electrode is connected with the drain electrode, the NM5 drain electrode and the PM6 grid electrode; the source electrode of the P channel enhancement type MOS tube PM6 is connected with VDD, the grid electrode is connected with the grid electrode of PM5, and the drain electrode is connected with the drain electrode of NM6, the grid electrode and the grid electrode of NM 8; the source electrode of the P channel enhancement type MOS tube PM7 is connected with VDD, and the grid electrode is connected with the drain electrode, the NM8 drain electrode and the PM8 grid electrode; the source electrode of the P channel enhancement type MOS tube PM8 is connected with VDD, the grid electrode is connected with the grid electrode and the drain electrode of PM7, the NM8 drain electrode is connected with ISLOPE ports. The main role of the PM3-PM8 is as a current mirror.
The drain electrode of the N-channel enhancement MOS tube NM1 is connected with the grid electrode, the drain electrode of the PM1 and the grid electrode of the NM4, and the source electrode of the NM1 is connected with GND; the drain electrode of the N-channel enhancement MOS tube NM2 is connected with the grid electrode, the grid electrode of NM3 and the drain electrode of PM2, and the source electrode is connected with GND; the grid electrode of the N-channel enhancement type MOS tube NM3 is connected with the grid electrode and the drain electrode of NM2 and the drain electrode of PM2, the drain electrode is connected with the drain electrode and the grid electrode of PM3 and the grid electrode of PM4, and the source electrode is connected with GND; the grid electrode of the N-channel enhancement type MOS tube NM4 is connected with the grid electrode of the NM1, the drain electrode is connected with the drain electrode of the PM4 and the grid electrode of the NM5, and the source electrode is connected with the GND; the drain electrode of the N-channel enhancement MOS tube NM5 is connected with the drain electrode of the PM5, the grid electrode of the PM6 and the grid electrode of one end PM2 of the resistor R5; the N-channel enhancement type MOS transistors NM1-NM4 are mainly used as current mirror loads of amplifiers, and the N-channel enhancement type MOS transistor NM5 is mainly used as an output buffer stage of a transconductance operational amplifier. The drain electrode of the N-channel enhancement MOS tube NM6 is connected with the grid electrode, the drain electrode of the PM6 and the grid electrode of the NM8, and the source electrode is connected with the drain electrode of the NM7 and the upper polar plate of the capacitor C3; the grid electrode of the N-channel enhancement type MOS tube NM7 is connected with a VPULSE port, and the source electrode is connected with a GND port; the grid electrode of the N-channel enhancement type MOS tube NM8 is connected with the grid electrode, the drain electrode and the PM6 drain electrode of the NM6, the drain electrode is connected with the grid electrode, the drain electrode and the grid electrode of the PM7, and the source electrode is connected with one end of the resistor R6. The N-channel enhancement type MOS transistors NM6-NM8 mainly have the function of generating slope voltage through switching signal pulse.
The upper polar plate of the capacitor C1 is connected with one ends of R3 and R4, and the lower polar plate is connected with GND; the upper polar plate of the capacitor C2 is connected with one end of the R4 and the PM1 grid electrode, and the lower polar plate is connected with the GND. The main function of the capacitors C1, C2 is to filter out high frequency components.
One end of the resistor R1 is connected with the SW port, and the other end of the resistor R1 is connected with one ends of the resistors R3 and R2; one end of the resistor R2 is connected with the other end of the resistor R1, and the other end of the resistor R2 is connected with GND. The resistors R1, R2 have the main function of stepping down a relatively high output voltage to within the common-mode input range of the PMOS differential pair. The resistors R3, R4 mainly function to form a low-pass filter together with the capacitance. One end of the resistor R5 is connected with the source electrode of the NM5 and the grid electrode of the PM2, and the other end of the resistor R5 is connected with the GND, and is mainly used for converting voltage quantity related to output voltage into current. One end of the resistor R6 is connected with the source electrode of the NM8, and the other end of the resistor R6 is connected with the GND, and the resistor R is mainly used for linearizing the voltage-current relationship of the NM8 to obtain a slope current.
The working principle of the whole circuit is as follows in combination with the illustration of fig. 1: the voltage signal of the SW switch node is a signal which is formed by chopping the input voltage with a certain duty ratio through a switch and is related to the input voltage and the output voltage, the signal is utilized to filter out high-frequency components after passing through a low-pass filter circuit, a voltage value which is in direct proportion to the output voltage is obtained after voltage reduction, the voltage value is converted into current through an operational amplifier, the capacitor is controlled to charge and discharge by a pulse switch signal synchronous with the switch signal, and the generated slope current is mirrored to obtain a self-adaptive slope voltage.
In summary, the present invention provides an adaptive ramp generating circuit in a peak current control mode, and after the general idea of designing a ramp circuit is adopted, the present invention provides an adaptive ramp generating circuit with wide input swing, which has great advantages compared with the conventional ramp generating circuit in the occasions requiring a wide input voltage range and multiple output versions.
Embodiments of the method according to the invention are explained in the above description with reference to the drawings, but the method according to the invention is not limited to the specific details of the embodiments, but can be carried out in a number of simple variants within the scope of the technical idea, which are all within the scope of protection of the method according to the invention.
Claims (1)
1. A control method of a ramp generating circuit, characterized by comprising the steps of:
The voltage signal of the SW switch node is a signal which is formed by chopping an input voltage with a fixed duty ratio through a switch and is related to both the input voltage and the output voltage, the voltage signal is utilized to filter high-frequency components after passing through a low-pass filter circuit, a voltage value which is in direct proportion to the output voltage is obtained after voltage reduction, the voltage value is converted into a current through an operational amplifier, the capacitor is controlled to charge and discharge by a pulse switch signal synchronous with the switch signal, and the generated slope current is mirrored to obtain a self-adaptive slope voltage;
The slope generating circuit comprises P-channel enhancement type MOS transistors PM1-PM8, N-channel enhancement type MOS transistors NM1-NM8, capacitors C1-C3, resistors R1-R6, a current source IDC1, a VDD input port, a SW input port and a GND port;
The VDD input port is connected with an external power supply; the SW input port is connected with a switch Guan Jiedian connected with the inductor; the VPULSE port is connected with a switch MOS tube related to a clock to generate a pulse signal of ramp voltage; the ISLOPE port is connected with a current mirror for outputting a slope current, and a slope voltage is generated on the resistor; the GND port is connected with the ground potential;
The source electrode of the P channel enhancement type MOS tube PM1 is connected with the source electrodes of the current sources IDC1 and PM2, the grid electrode is connected with one end of the resistor R4 and the upper polar plate of the capacitor C2, and the drain electrode is connected with the drain electrode of the NM1, the grid electrode and the grid electrode of the NM 4; the source electrode of the P channel enhancement type MOS tube PM2 is connected with the source electrodes of the current sources IDC1 and PM1, the grid electrode is connected with one end of the resistor R5 and the source electrode of the NM5, and the drain electrode is connected with the drain electrode of the NM2, the grid electrode and the grid electrode of the NM 3; the main roles of the PM1 and PM2 are input differential pairs of voltage-current conversion; the source electrode of the P channel enhancement type MOS tube PM3 is connected with the VDD input port, the grid electrode is connected with the drain electrode and the PM4 grid electrode, and the drain electrode is connected with the NM3 drain electrode; the source electrode of the P channel enhancement type MOS tube PM4 is connected with the VDD input port, the grid electrode is connected with the grid electrode of the PM3, and the drain electrode is connected with the drain electrode of the NM4 and the grid electrode of the NM 5; the source electrode of the P channel enhancement type MOS tube PM5 is connected with the VDD input port, and the grid electrode is connected with the drain electrode, the NM5 drain electrode and the PM6 grid electrode; the source electrode of the P channel enhancement type MOS tube PM6 is connected with the VDD input port, the grid electrode is connected with the grid electrode of the PM5, and the drain electrode is connected with the drain electrode of the NM6, the grid electrode and the grid electrode of the NM 8; the source electrode of the P channel enhancement type MOS tube PM7 is connected with the VDD input port, and the grid electrode is connected with the drain electrode, the NM8 drain electrode and the PM8 grid electrode; the source electrode of the P channel enhancement MOS tube PM8 is connected with the VDD input port, the grid electrode is connected with the grid electrode and the drain electrode of PM7, the NM8 drain electrode is connected with the ISLOPE port; the PM3-PM8 is a current mirror;
The drain electrode of the N-channel enhancement MOS tube NM1 is connected with the grid electrode, the drain electrode of the PM1 and the grid electrode of the NM4, and the source electrode of the NM1 is connected with the GND port; the drain electrode of the N-channel enhancement MOS tube NM2 is connected with the grid electrode, the grid electrode of NM3 and the drain electrode of PM2, and the source electrode is connected with the GND port; the grid electrode of the N-channel enhancement type MOS tube NM3 is connected with the grid electrode and the drain electrode of NM2 and the drain electrode of PM2, the drain electrode is connected with the drain electrode and the grid electrode of PM3 and the grid electrode of PM4, and the source electrode is connected with the GND port; the grid electrode of the N-channel enhancement type MOS tube NM4 is connected with the grid electrode of the NM1, the drain electrode is connected with the drain electrode of the PM4 and the grid electrode of the NM5, and the source electrode is connected with the GND port; the drain electrode of the N-channel enhancement MOS tube NM5 is connected with the drain electrode and the grid electrode of the PM5 and the grid electrode of the PM6, and the source electrode is connected with one end of the resistor R5 and the grid electrode of the PM 2; the N-channel enhancement type MOS transistors NM1-NM4 are mainly used as current mirror loads of amplifiers, and the N-channel enhancement type MOS transistor NM5 is mainly used as an output buffer stage of a transconductance operational amplifier; the drain electrode of the N-channel enhancement MOS tube NM6 is connected with the grid electrode, the drain electrode of the PM6 and the grid electrode of the NM8, and the source electrode is connected with the drain electrode of the NM7 and the upper polar plate of the capacitor C3; the grid electrode of the N-channel enhancement type MOS tube NM7 is connected with a VPULSE port, and the source electrode is connected with a GND port; the grid electrode of the N-channel enhancement type MOS tube NM8 is connected with the grid electrode, the drain electrode and the PM6 drain electrode of the NM6, the drain electrode is connected with the grid electrode, the drain electrode and the grid electrode of the PM7, and the source electrode is connected with one end of the resistor R6; the N-channel enhancement type MOS transistors NM6-NM8 mainly have the function of generating slope voltage through switching signal pulse;
The upper polar plate of the capacitor C1 is connected with one end of R3 and the other end of R4, and the lower polar plate is connected with the GND port; the upper polar plate of the capacitor C2 is connected with one end of the R4 and the PM1 grid electrode, and the lower polar plate is connected with the GND port;
One end of the resistor R1 is connected with the SW input port, and the other end of the resistor R1 is connected with the other end of the resistor R3 and one end of the resistor R2 respectively; one end of the resistor R2 is connected with the other end of the resistor R1, and the other end of the resistor R2 is connected with the GND port; the resistors R1 and R2 have the main function of reducing relatively higher output voltage to be in the common-mode input range of the PMOS differential pair; the resistors R3 and R4 and the capacitor form a low-pass filter; one end of the resistor R5 is connected with the source electrode of the NM5 and the grid electrode of the PM2, and the other end of the resistor R5 is connected with the GND port to convert voltage quantity related to output voltage into current; one end of the resistor R6 is connected with the source electrode of the NM8, and the other end of the resistor R6 is connected with the GND port, and the resistor R is mainly used for linearizing the voltage-current relationship of the NM8 to obtain a slope current.
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| CN104506035A (en) * | 2014-12-10 | 2015-04-08 | 中山大学 | Self-adaptive slope compensation circuit |
| CN108574410A (en) * | 2018-05-21 | 2018-09-25 | 福建江夏学院 | Realize the circuit and method of self-adaptable slop compensation quick high accuracy |
| CN108900069A (en) * | 2018-07-05 | 2018-11-27 | 电子科技大学 | A kind of Adaptive Second slope compensation circuit based on duty ratio |
| CN215452775U (en) * | 2021-01-12 | 2022-01-07 | 西安拓尔微电子有限责任公司 | Wide-swing self-adaptive slope generation circuit |
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- 2021-01-12 CN CN202110038219.0A patent/CN112865495B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104506035A (en) * | 2014-12-10 | 2015-04-08 | 中山大学 | Self-adaptive slope compensation circuit |
| CN108574410A (en) * | 2018-05-21 | 2018-09-25 | 福建江夏学院 | Realize the circuit and method of self-adaptable slop compensation quick high accuracy |
| CN108900069A (en) * | 2018-07-05 | 2018-11-27 | 电子科技大学 | A kind of Adaptive Second slope compensation circuit based on duty ratio |
| CN215452775U (en) * | 2021-01-12 | 2022-01-07 | 西安拓尔微电子有限责任公司 | Wide-swing self-adaptive slope generation circuit |
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