CN112820240B

CN112820240B - Pixel circuit

Info

Publication number: CN112820240B
Application number: CN202110019549.5A
Authority: CN
Inventors: 郑贸熏; 洪嘉泽
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2020-08-26
Filing date: 2021-01-07
Publication date: 2022-12-23
Anticipated expiration: 2041-01-07
Also published as: CN112820240A; TWI734597B; TW202209285A

Abstract

The invention discloses a pixel circuit which comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor and a second capacitor. The pixel circuit can solve the problem of insufficient compensation of the threshold voltage, and avoid the display quality reduction caused by leakage current in the low frame rate mode.

Description

Pixel circuit

Technical Field

The present invention relates to a pixel circuit, and more particularly, to a pixel circuit disposed on a flexible printed circuit board for reducing cost and improving display quality.

Background

In the application of display devices, wearable display devices are products that are well paid attention to by consumers, and whether the wearable display devices are head-mounted devices or various smart bands, watches, and the like, displays with different sizes and resolutions can be set according to requirements. These display devices include a plurality of pixel circuits in a display area, and the pixel circuits are driven by a driving circuit chip provided in a peripheral area, thereby controlling each pixel in the display area to emit light to display a picture.

In the conventional design, most of the driving circuit chips are disposed on a Chip on film (Chip on film), and the driving signals are transmitted to the pixel circuits respectively through a multiplexer circuit. However, the cost of the flip chip on film is high, and the driver circuit chips are expected to be disposed on a Flexible printed circuit board (Flexible printed board) due to the cost of the product. However, due to the limitation of the pitch of the contact pins, the flexible printed circuit board cannot provide the number of pins arranged on the flip-chip type thin film, so that the number of rows to be controlled by each contact is increased, which causes the insufficient time for compensating the transistor threshold voltage in the pixel circuit and affects the display quality. On the other hand, if the display device operates at a low frequency, the gate voltage of the driving transistor may be difficult to maintain at a predetermined potential due to a leakage current, which may also affect the quality of the display screen.

In view of the foregoing, the present inventors have devised and designed a pixel circuit to solve the problems of the prior art and further improve the industrial application.

Disclosure of Invention

In view of the problems of the prior art, an object of the present invention is to provide a pixel circuit for solving the problems of insufficient threshold voltage compensation time and leakage current during low frequency operation when the pixel circuit is disposed on a flexible printed circuit board.

In view of the above, the present invention provides a pixel circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor. The first terminal of the first transistor is coupled to the first voltage source, the second terminal of the first transistor is coupled to the first node, the first terminal of the second transistor receives a data signal, the second terminal of the second transistor is coupled to the second node, the first terminal of the third transistor is coupled to the second node, the second terminal of the third transistor is coupled to a first reference voltage, the first terminal of the first capacitor is coupled to the second node, the second terminal of the first capacitor is coupled to the third node, the first terminal of the second capacitor is coupled to the first node, the second terminal of the second capacitor is coupled to the second node, the first terminal of the fourth transistor is coupled to the first node, the second terminal of the fourth transistor is coupled to the fourth node, the control terminal of the fourth transistor is coupled to the third node, the first terminal of the fifth transistor is coupled to the fourth node, the first terminal of the sixth transistor is coupled to the first voltage source, the second terminal of the sixth transistor is coupled to the third node, the first terminal of the seventh transistor is coupled to the third node, the second terminal of the seventh transistor is coupled to the first reference voltage source, the first terminal of the eighth transistor is coupled to the fourth node, and the second terminal of the light emitting diode.

In an embodiment of the invention, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor may be P-type transistors, a control terminal of the sixth transistor receives the first control signal, a control terminal of the third transistor and a control terminal of the fifth transistor receive the second control signal, a control terminal of the seventh transistor receives the third control signal, a control terminal of the second transistor receives the scan signal, and a control terminal of the first transistor and a control terminal of the eighth transistor receive the light signal.

In an embodiment of the invention, during the first period, the first control signal, the second control signal and the light-emitting signal are low voltages, and the third control signal and the scan signal are high voltages. In the second period, the second control signal and the third control signal are low voltage, and the first control signal, the scan signal and the light emitting signal are high voltage. In the third period, the third control signal and the scan signal are low voltage, and the first control signal, the second control signal and the light-emitting signal are high voltage. In the fourth period, the light-emitting signal is at a low voltage, and the first control signal, the second control signal, the third control signal and the scan signal are at a high voltage.

In an embodiment of the invention, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the eighth transistor may be P-type transistors, the seventh transistor may be an N-type transistor, the control terminal of the sixth transistor receives the first control signal, the control terminals of the third transistor and the fifth transistor receive the second control signal, the control terminal of the second transistor receives the scan signal, and the control terminals of the first transistor, the seventh transistor, and the eighth transistor receive the light receiving signal.

In an embodiment of the present invention, in the first period, the first control signal, the second control signal and the light emitting signal are low voltage, the scan signal is high voltage, in the second period, the second control signal is low voltage, the first control signal, the scan signal and the light emitting signal are high voltage, in the third period, the scan signal is low voltage, the first control signal, the second control signal and the light emitting signal are high voltage, in the fourth period, the light emitting signal is low voltage, and the first control signal, the second control signal and the scan signal are high voltage.

In an embodiment of the invention, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor may be P-type transistors, the first transistor and the eighth transistor may be N-type transistors, the control terminal of the sixth transistor receives the first control signal, the control terminal of the third transistor and the control terminal of the fifth transistor receive the second control signal, the control terminal of the first transistor, the control terminal of the seventh transistor and the control terminal of the eighth transistor receive the third control signal, and the control terminal of the second transistor receives the scan signal.

In an embodiment of the present invention, in the first period, the first control signal and the second control signal are low voltage, the third control signal and the scan signal are high voltage, in the second period, the second control signal and the third control signal are low voltage, the first control signal and the scan signal are high voltage, in the third period, the third control signal and the scan signal are low voltage, the first control signal and the second control signal are high voltage, and in the fourth period, the first control signal, the second control signal, the third control signal and the scan signal are high voltage.

In an embodiment of the invention, the second terminal of the fifth transistor may be coupled to the second reference voltage.

In an embodiment of the invention, a control terminal of the fifth transistor may be coupled to the second terminal of the fifth transistor.

In an embodiment of the invention, one end of the light emitting diode may be coupled to a second voltage source.

In summary, the pixel circuit of the present invention can reduce the overall cost of wearing the display device and enhance the competitiveness of the display device by the arrangement of the circuit structure. For the reduction of the pin number of the driving chip to increase the number of control lines and further reduce the critical voltage compensation time, the present disclosure can achieve the expected voltage level through the independent voltage compensation period without being influenced by the reduction of the period time of the data signal. In addition, for the display device in the low frame rate mode, the problem of voltage potential reduction caused by leakage current can be avoided through the circuit structure, and the display quality of the picture of the display device is effectively improved.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Drawings

In order to make the technical features, contents and advantages of the present invention and the effects achieved thereby more obvious, the present invention will be described with reference to the accompanying drawings:

fig. 1 is a schematic diagram of a pixel circuit according to an embodiment of the invention.

FIG. 2 is a timing diagram illustrating the operation of a pixel circuit according to an embodiment of the present invention.

Fig. 3A to 3D are schematic diagrams illustrating the operation period of the pixel circuit according to the embodiment of the invention.

Fig. 4 is a schematic diagram of a pixel circuit according to another embodiment of the invention.

FIG. 5 is a timing diagram illustrating the operation of a pixel circuit according to another embodiment of the present invention.

Fig. 6 is a schematic diagram of a pixel circuit according to yet another embodiment of the invention.

FIG. 7 is a timing diagram illustrating the operation of a pixel circuit according to yet another embodiment of the present invention.

Wherein, the reference numbers:

10,20,30 pixel circuit

11,21,31 the first period

12,22,32: second period

13,23,33 the third period

14,24,34: fourth period

A is a first node

B, the second node

C, a third node

C1: first capacitor

C2: second capacitance

D, a fourth node

DATA is a DATA signal

E, light emitting diode

EM (electromagnetic radiation) light emitting signal

OVDD the first voltage source

OVSS secondary voltage source

SD scanning signal

S1 first control signal

S2. Second control signal

S3 third control signal

T1, T11 first transistor

T2: second transistor

T3: third transistor

T4 fourth transistor

T5 fifth transistor

T6: sixth transistor

T7, T71 seventh transistor

T8, T81 eighth transistor

V _REF1 A first reference voltage

V _REF2 The second reference voltage

Detailed Description

The structural and operational principles of the present invention are described in detail below with reference to the accompanying drawings:

in order to facilitate understanding of the technical features, contents, and advantages of the present invention and the effects achieved thereby, the present invention will be described in detail with reference to the accompanying drawings in the form of embodiments, wherein the drawings are provided for illustration and an auxiliary description, and are not necessarily to be construed as true in scale and precise in arrangement after the implementation of the present invention, and therefore, the drawings should not be construed as limiting the scope of the present invention in terms of the ratio and arrangement thereof.

In the drawings, the thickness or width of the substrate, panel, region, line, etc. is exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a substrate, panel, region or line is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected" to another element, there are no intervening elements present. As used herein, "connected," can refer to physical and/or electrical connections. Furthermore, an "electrical connection" or "coupling" may be the presence of other elements between the two elements. Further, it will be understood that, although the terms "first", "second", "third" and/or the like may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should be used to distinguish one element, component, region, layer and/or section from another element, component, region, layer and/or section. Therefore, they are used for descriptive purposes only and not to be construed as indicating or implying relative importance or order relationships thereof.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Please refer to fig. 1, which is a diagram illustrating a pixel circuit according to an embodiment of the present invention. As shown, the pixel circuit 10 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor C1, and a second capacitor C2, which is a pixel circuit with eight transistors and two capacitors (8T 2C). In the present embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all P-type transistors.

A first terminal of the first transistor T1 is coupled to the first voltage source OVDD, a second terminal of the first transistor T1 is coupled to the first node a, and a control terminal of the first transistor T1 receives and transmits the optical signal EM. A first terminal of the second transistor T2 receives the DATA signal DATA, a second terminal of the second transistor T2 is coupled to the second node B, and a control terminal of the second transistor T2 receives the scan signal SD. A first terminal of a third transistor T3 is coupled to the second node B, and a second terminal of the third transistor T3 is coupled to a first reference voltage V _REF1 The control terminal of the third transistor T3 receives the second control signal S2. The first terminal of the first capacitor C1 is coupled to the second node B, the second terminal of the first capacitor C1 is coupled to the third node C, the first terminal of the second capacitor C2 is coupled to the first node a, and the second terminal of the second capacitor C2 is coupled to the second node B. A first terminal of the fourth transistor is coupled to the first node,a second terminal of the fourth transistor T4 is coupled to the fourth node D, and a control terminal of the fourth transistor T4 is coupled to the third node C. A first terminal of the fifth transistor T5 is coupled to the fourth node D, and a second terminal of the fifth transistor T5 is coupled to the second reference voltage V _REF2 The control terminal of the fifth transistor T5 receives the second control signal S2. A first terminal of the sixth transistor T6 is coupled to the first voltage source OVDD, a second terminal of the sixth transistor T6 is coupled to the third node C, and a control terminal of the sixth transistor T6 receives the first control signal S1. A first terminal of the seventh transistor T7 is coupled to the third node C, and a second terminal of the seventh transistor T7 is coupled to the first reference voltage V _REF1 The control terminal of the seventh transistor T7 receives the third control signal S3. A first terminal of the eighth transistor T8 is coupled to the fourth node D, a second terminal of the eighth transistor T8 is coupled to the light emitting diode E, and a control terminal of the eighth transistor T8 receives the transmit-receive optical signal EM. One end of the light emitting diode E is coupled to the eighth transistor T8, and the other end is coupled to the second voltage source OVSS.

The actual operation flow of the pixel circuit 10 can be illustrated according to the following embodiments, please refer to fig. 2, which is a timing diagram of the operation of the pixel circuit according to the embodiment of the present invention. As shown in the figure, the signal control of the pixel circuit 10 is divided into four operation periods in terms of timing, which are a first period 11, a second period 12, a third period 13 and a fourth period 14. In different time, each signal source controls the switch of the connected transistor by the voltage potential of the control circuit. In the present embodiment, each transistor is controlled by a first control signal S1, a second control signal S2, a third control signal S3, a scan signal SD, and an emission signal EM. The detailed operation of each operation period will be described in the schematic diagrams of the pixel circuit operation periods in fig. 3A to 3D, in which fig. 3A is a schematic diagram of the pixel circuit in a first period, fig. 3B is a schematic diagram of the pixel circuit in a second period, fig. 3C is a schematic diagram of the pixel circuit in a third period, and fig. 3D is a schematic diagram of the pixel circuit in a fourth period.

Referring to fig. 2 and 3A, in the first period 11, the first control signal S1, the second control signal S2 and the emission signal EM are low voltage, and the third control signal S is3 and the scan signal SD is high voltage. As shown, the sixth transistor T6 controlled by the first control signal S1, the third transistor T3 controlled by the second control signal S2, and the first transistor T1 and the eighth transistor T8 controlled by the emission signal EM are turned on. The seventh transistor T7 controlled by the third control signal S3 and the second transistor T2 controlled by the scan signal SD are turned off. At this stage, the first node A and the third node C of the pixel circuit 10 are respectively charged to the voltage level of the first voltage source OVDD, and the second node B is charged to the first reference voltage V _REF1 At a fourth node D at a second reference voltage V _REF2 Voltage potential of (2).

Referring to fig. 2 and 3B, in the second period 12, the second control signal S2 and the third control signal S3 are at a low voltage, and the first control signal S1, the scan signal SD and the emission signal EM are at a high voltage. As shown, the third transistor T3 controlled by the second control signal S2 and the seventh transistor T7 controlled by the third control signal S3 are turned on. The sixth transistor T6 controlled by the first control signal S1, the second transistor T2 controlled by the scan signal SD, and the first transistor T1 and the eighth transistor T8 controlled by the emission signal EM are turned off. At this stage, the first transistor T1 of the pixel circuit 10 is turned off, so that the third node C and the second node B are coupled to the same first reference voltage V _REF1 The fourth node D is maintained at the same second reference voltage V _REF2 Voltage potential of (2). At this time, the first node A is converted into the first reference voltage V from the voltage potential of the first voltage source OVDD _REF1 In addition to the threshold voltage of the fourth transistor T4, the second transistor T2 is not turned on by the scan signal SD in the voltage compensation stage, and is not affected by the period length of the DATA signal DATA.

In the timing diagram of the present embodiment, the intervals of the respective timing sequences are only examples, and the length of each operation period can be independently adjusted according to the requirement, for example, when the operation time allocated to the DATA signal DATA is short, the pixel circuit 10 of the present embodiment can independently adjust the size of the second period 12, so that the voltage can be compensated to the required voltage, thereby avoiding the situation that the voltage cannot be compensated to the sufficient voltage due to the insufficient operation time of the DATA signal DATA, and preventing the display quality of the image from being affected.

Referring to fig. 2 and 3C, in the third period 13, the third control signal S3 and the scan signal SD are low, and the first control signal S1, the second control signal S2 and the emission signal EM are high. As shown, the seventh transistor T7 controlled by the third control signal S3 and the second transistor T2 controlled by the scan signal SD are turned on. The sixth transistor T6 controlled by the first control signal S1, the third transistor T3 controlled by the second control signal S2, and the first transistor T1 and the eighth transistor T8 controlled by the emission signal EM are turned off. At this stage, the second node B of the pixel circuit 10 is driven by the first reference voltage V _REF1 Is converted into a voltage level provided by the DATA signal DATA, the first node A is driven by a first reference voltage V _REF1 Plus the threshold voltage of the fourth transistor T4, is converted into the voltage level of the DATA signal DATA plus the threshold voltage level of the fourth transistor T4. The third node is maintained at the first reference voltage V _REF1 The fourth node D is maintained at the same second reference voltage V _REF2 Voltage potential of (2).

Referring to fig. 2 and fig. 3D, in the fourth period 14, the emission signal EM is at a low voltage, and the first control signal S1, the second control signal S2, the third control signal S3 and the scan signal SD are at a high voltage. As shown, the first transistor T1 and the eighth transistor T8 controlled by the emission signal EM are turned on. The sixth transistor T6 controlled by the first control signal S1, the third transistor T3 controlled by the second control signal S2, the seventh transistor T7 controlled by the third control signal S3, and the second transistor T2 controlled by the scan signal SD are turned off. At this stage, the first node a of the pixel circuit 10 is converted to the voltage potential of the first voltage source OVDD, and the second node B is further coupled to the third node C, so that the fourth transistor T4 is turned on to enable the current flowing through the light emitting diode E to emit light.

At this stage, the voltage at the third node C may not be maintained at the required level due to the leakage current, and the display quality of the display screen may be reduced especially in the operation mode of the display screen at the low frame rate. In the bookIn the embodiment, in the fourth period 14, when the first control signal S1 and the third control signal S3 are both high voltage, that is, the sixth transistor T6 and the seventh transistor T7 are both off. Although the sixth transistor T6 and the seventh transistor T7 still have the current leakage, since the first voltage source OVDD connected to one end of the sixth transistor T6 is at a high voltage level, the first reference voltage V connected to the seventh transistor T7 _REF1 The voltage level of the sixth transistor T6 is low, and therefore, in the direction of current leakage, the sixth transistor T6 flows from the first terminal to the third terminal C connected to the second terminal, and the seventh transistor T7 flows from the first terminal to the second terminal connected to the third terminal C, so that the voltage level of the third node C can be maintained at the required level. Therefore, the present embodiment can not only independently adjust the voltage compensation time, but also avoid the display quality from being degraded due to the leakage current in the low frame rate mode.

Please refer to fig. 4, which is a diagram illustrating a pixel circuit according to another embodiment of the present invention. As shown in the figure, the pixel circuit 20 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T71, an eighth transistor T8, a first capacitor C1, and a second capacitor C2, which is a pixel circuit with two capacitors (8T 2C) including eight transistors. In the present embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the eighth transistor T8 are all P-type transistors, and the seventh transistor T71 is an N-type transistor.

A first terminal of the first transistor T1 is coupled to the first voltage source OVDD, a second terminal of the first transistor T1 is coupled to the first node a, and a control terminal of the first transistor T1 receives and transmits the optical signal EM. A first terminal of the second transistor T2 receives the DATA signal DATA, a second terminal of the second transistor T2 is coupled to the second node B, and a control terminal of the second transistor T2 receives the scan signal SD. A first terminal of a third transistor T3 is coupled to the second node B, and a second terminal of the third transistor T3 is coupled to a first reference voltage V _REF1 The control terminal of the third transistor T3 receives the second control signal S2. A first terminal of the first capacitor C1 is coupled to the second node B, and a second terminal of the first capacitor C1 is coupled to the first node BAt the third node C, a first end of the second capacitor C2 is coupled to the first node a, and a second end of the second capacitor C2 is coupled to the second node B. A first terminal of the fourth transistor T4 is coupled to the first node, a second terminal of the fourth transistor T4 is coupled to the fourth node D, and a control terminal of the fourth transistor T4 is coupled to the third node C. A first terminal of the fifth transistor T5 is coupled to the fourth node D, and a control terminal of the fifth transistor T5 receives the second control signal S2. A first terminal of the sixth transistor T6 is coupled to the first voltage source OVDD, a second terminal of the sixth transistor T6 is coupled to the third node C, and a control terminal of the sixth transistor T6 receives the first control signal S1. A first terminal of the seventh transistor T71 is coupled to the third node C, and a second terminal of the seventh transistor T71 is coupled to the first reference voltage V _REF1 The control terminal of the seventh transistor T71 receives the optical signal EM. A first terminal of the eighth transistor T8 is coupled to the fourth node D, a second terminal of the eighth transistor T8 is coupled to the light emitting diode E, and a control terminal of the eighth transistor T8 receives the optical signal EM. One end of the light emitting diode E is coupled to the eighth transistor T8, and the other end is coupled to the second voltage source OVSS.

In the present embodiment, the control terminal of the seventh transistor T71 receives the optical signal EM instead of the third control signal S3 of the previous embodiment. In addition, a second terminal of the fifth transistor T5 of the pixel circuit 20 is coupled to the control terminal of the fifth transistor T5, forming a diode connection without being additionally connected to the reference voltage. The difference setting can reduce the third control signal S3 and the second reference voltage V _REF2 The signal source circuit is arranged, and the space required by circuit wiring is reduced. The operation of which is further illustrated by the following timing diagram.

Please refer to fig. 5, which is a timing diagram illustrating an operation of a pixel circuit according to another embodiment of the present invention. As shown, the signal control of the pixel circuit 20 is divided into four operation periods in terms of timing, namely a first period 21, a second period 22, a third period 23 and a fourth period 24. In the first period 21, the first control signal S1, the second control signal S2 and the emission signal EM are low voltage, the scan signal SD is high voltage, in the second period 22, the second control signal S2 is low voltage, the first control signal S1, the scan signal SD and the emission signal EM are high voltage, in the third period 23, the scan signal SD is low voltage, the first control signal S1, the second control signal S2 and the emission signal EM are high voltage, in the fourth period 24, the emission signal EM is low voltage, and the first control signal S1, the second control signal S2 and the scan signal SD are high voltage.

In the present embodiment, since the seventh transistor T71 is an N-type transistor, the transistor is turned off when the control signal is low voltage, and on the contrary, the transistor is turned on when the control signal is high voltage. Therefore, the seventh transistor T71 is turned off in the first period 21 and the fourth period 24, and turned on in the second period 22 and the third period 23, and the turning on and off operations are the same as those in the previous embodiment, and the corresponding operations are not repeated. The present embodiment reduces the space required for disposing the signal source lines by changing the types of transistors so as to be able to share the same control signal in operation.

Please refer to fig. 6, which is a diagram illustrating a pixel circuit according to another embodiment of the present invention. As shown, the pixel circuit 30 includes a first transistor T11, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T81, a first capacitor C1, and a second capacitor C2, which is a pixel circuit with eight transistors and two capacitors (8T 2C). In the present embodiment, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T71 are P-type transistors, and the first transistor T11 and the eighth transistor T81 are N-type transistors.

A first terminal of the first transistor T11 is coupled to the first voltage source OVDD, a second terminal of the first transistor T11 is coupled to the first node a, and a control terminal of the first transistor T11 receives the third control signal S3. A first terminal of the second transistor T2 receives the DATA signal DATA, a second terminal of the second transistor T2 is coupled to the second node B, and a control terminal of the second transistor T2 receives the scan signal SD. A first terminal of the third transistor T3 is coupled to the second node B, and a second terminal of the third transistor T3 is coupled to the first reference voltage V _REF1 Third, aThe control terminal of the transistor T3 receives the second control signal S2. A first terminal of the first capacitor C1 is coupled to the second node B, a second terminal of the first capacitor C1 is coupled to the third node C, a first terminal of the second capacitor C2 is coupled to the first node a, and a second terminal of the second capacitor C2 is coupled to the second node B. A first terminal of the fourth transistor T4 is coupled to the first node, a second terminal of the fourth transistor T4 is coupled to the fourth node D, and a control terminal of the fourth transistor T4 is coupled to the third node C. A first terminal of the fifth transistor T5 is coupled to the fourth node D, and a second terminal of the fifth transistor T5 is coupled to the second reference voltage V _REF2 The control terminal of the fifth transistor T5 receives the second control signal S2. A first terminal of the sixth transistor T6 is coupled to the first voltage source OVDD, a second terminal of the sixth transistor T6 is coupled to the third node C, and a control terminal of the sixth transistor T6 receives the first control signal S1. A first terminal of the seventh transistor T7 is coupled to the third node C, and a second terminal of the seventh transistor T7 is coupled to the first reference voltage V _REF1 The control terminal of the seventh transistor T7 receives the third control signal S3. A first terminal of the eighth transistor T8 is coupled to the fourth node D, a second terminal of the eighth transistor T8 is coupled to the light emitting diode E, and a control terminal of the eighth transistor T8 receives the third control signal S3. One end of the light emitting diode E is coupled to the eighth transistor T8, and the other end is coupled to the second voltage source OVSS.

In the present embodiment, the control terminal of the first transistor T11 and the control terminal of the eighth transistor T81 receive the third control signal S3 instead of the emission signal EM of the previous embodiment. As can be seen from the timing diagram of fig. 2, the third control signal S3 and the emission signal EM are opposite control signals, so that the transistors can share the signal source of the third control signal S3 to achieve the same operation by setting the first transistor T11 and the eighth transistor T81 as N-type transistors, and no signal line for providing the emission signal EM is required.

Please refer to fig. 7, which is a timing diagram illustrating the operation of a pixel circuit according to another embodiment of the present invention. As shown, the signal control of the pixel circuit 20 is divided into four operation periods in terms of timing, namely, a first period 31, a second period 32, a third period 33 and a fourth period 34. In the first period 31, the first control signal S1 and the second control signal S2 are low voltage, the third control signal and the scan signal SD are high voltage, in the second period 32, the second control signal S2 and the third control signal S3 are low voltage, the first control signal S1 and the scan signal SD are high voltage, in the third period 33, the third control signal S3 and the scan signal SD are low voltage, the first control signal S1 and the second control signal S2 are high voltage, and in the fourth period 44, the first control signal S1, the second control signal S2, the third control signal S3 and the scan signal SD are high voltage.

In the present embodiment, since the first transistor T11 and the eighth transistor T81 are N-type transistors, the transistors are turned off when the control signal is low voltage, and on the contrary, the transistors are turned on when the control signal is high voltage. Therefore, the first transistor T11 and the eighth transistor T81 are turned on during the first period 21 and the fourth period 24, and turned off during the second period 22 and the third period 23, and the operations of turning on and off are the same as those in the previous embodiment, and the corresponding operations are not repeated. The present embodiment reduces the space required for disposing the signal source lines by changing the types of transistors so as to be able to share the same control signal in operation.

The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A pixel circuit, comprising:

a first transistor, a first terminal of which is coupled to a first voltage source and a second terminal of which is coupled to a first node;

a second transistor, a first end of the second transistor receiving a data signal, a second end of the second transistor being coupled to a second node;

a third transistor, wherein a first terminal of the third transistor is coupled to the second node, and a second terminal of the third transistor is coupled to a first reference voltage;

a first capacitor, a first end of which is coupled to the second node, and a second end of which is coupled to a third node;

a second capacitor, wherein a first end of the second capacitor is coupled to the first node, and a second end of the second capacitor is coupled to the second node;

a fourth transistor, a first terminal of which is coupled to the first node, a second terminal of which is coupled to a fourth node, and a control terminal of which is coupled to the third node;

a fifth transistor, a first end of which is coupled to the fourth node;

a sixth transistor, a first terminal of which is coupled to the first voltage source and a second terminal of which is coupled to the third node;

a seventh transistor, a first terminal of which is coupled to the third node and a second terminal of which is coupled to the first reference voltage; and

an eighth transistor, a first terminal of which is coupled to the fourth node and a second terminal of which is coupled to a light emitting diode;

the first voltage source is at a high potential, and the first reference voltage is at a low potential.

2. The pixel circuit according to claim 1, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are P-type transistors, a control terminal of the sixth transistor receives a first control signal, a control terminal of the third transistor and a control terminal of the fifth transistor receive a second control signal, a control terminal of the seventh transistor receives a third control signal, a control terminal of the second transistor receives a scan signal, and a control terminal of the first transistor and a control terminal of the eighth transistor receive a light emitting signal.

3. The pixel circuit according to claim 2, wherein the first control signal, the second control signal and the emission signal are low voltage, the third control signal and the scan signal are high voltage during a first period, the second control signal and the third control signal are low voltage, the first control signal, the scan signal and the emission signal are high voltage during a second period, the third control signal and the scan signal are low voltage, the first control signal, the second control signal and the emission signal are high voltage during a third period, and the emission signal is low voltage, the first control signal, the second control signal and the emission signal are high voltage during a fourth period.

4. The pixel circuit according to claim 1, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the eighth transistor are P-type transistors, the seventh transistor is an N-type transistor, the control terminal of the sixth transistor receives a first control signal, the control terminals of the third transistor and the fifth transistor receive a second control signal, the control terminal of the second transistor receives a scan signal, and the control terminals of the first transistor, the seventh transistor and the eighth transistor receive a light emitting signal.

5. The pixel circuit according to claim 4, wherein the first control signal, the second control signal and the light emitting signal are low voltage and the scan signal is high voltage during a first period, the second control signal is low voltage and the first control signal, the scan signal and the light emitting signal are high voltage during a second period, the scan signal is low voltage and the first control signal, the second control signal and the light emitting signal are high voltage during a third period, the light emitting signal is low voltage and the first control signal, the second control signal and the light emitting signal are high voltage during a fourth period.

6. The pixel circuit according to claim 1, wherein the second, third, fourth, fifth, sixth and seventh transistors are P-type transistors, the first and eighth transistors are N-type transistors, the control terminal of the sixth transistor receives a first control signal, the control terminals of the third and fifth transistors receive a second control signal, the control terminals of the first, seventh and eighth transistors receive a third control signal, and the control terminal of the second transistor receives a scan signal.

7. The pixel circuit according to claim 6, wherein the first control signal and the second control signal are low voltage and the third control signal and the scan signal are high voltage during a first period, the second control signal and the third control signal are low voltage and the first control signal and the scan signal are high voltage during a second period, the third control signal and the scan signal are low voltage and the first control signal and the second control signal are high voltage during a third period, and the first control signal, the second control signal, the third control signal and the scan signal are high voltage during a fourth period.

8. The pixel circuit of claim 1 wherein a second terminal of the fifth transistor is coupled to a second reference voltage.

9. The pixel circuit of claim 1, wherein a control terminal of the fifth transistor is coupled to a second terminal of the fifth transistor.

10. The pixel circuit of claim 1, wherein one end of the light emitting diode is coupled to a second voltage source.