TWI696993B - Pixel circuit - Google Patents

Pixel circuit Download PDF

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TWI696993B
TWI696993B TW108117194A TW108117194A TWI696993B TW I696993 B TWI696993 B TW I696993B TW 108117194 A TW108117194 A TW 108117194A TW 108117194 A TW108117194 A TW 108117194A TW I696993 B TWI696993 B TW I696993B
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transistor
signal
circuit
terminal
voltage
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TW108117194A
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TW202044225A (en
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鄭貿薰
陳奕冏
洪嘉澤
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友達光電股份有限公司
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Priority to TW108117194A priority Critical patent/TWI696993B/en
Priority to CN202010000817.4A priority patent/CN111341251B/en
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Publication of TW202044225A publication Critical patent/TW202044225A/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

A pixel circuit includes a driving transistor, a first transistor, a second transistor, a data writing circuit, a first switching circuit, a second switching circuit, a reset circuit, a capacitor, and a light-emitting unit. The driving transistor is coupled to a first node, a second node, and a third node. The first transistor is selectively turned on according to a first signal. The second transistor is selectively turned on according to a second signal. The data writing circuit delivers a data voltage to the first node in response to a third signal. The first switching circuit delivers the first voltage to the driving transistor in response to a control signal. The second switching circuit connects the driving transistor to the light-emitting circuit in response to the control signal. The reset circuit delivers a second voltage to the driving transistor in response to the first signal.

Description

畫素電路 Pixel circuit

本揭示文件係關於一種畫素電路，特別是一種能夠改善穩定性的畫素電路。 This disclosure relates to a pixel circuit, especially a pixel circuit that can improve stability.

發光電路兩端的電壓差會隨著當前發光亮度的不同而有差異，這樣的差異會使得畫素電路面臨到不一致的電壓操作起始點，此不一致性會影響到後續畫素電路電壓操作的一致性以及發光電路的發光表現。 The voltage difference between the two ends of the light-emitting circuit will vary with the current light-emitting brightness. Such a difference will cause the pixel circuit to face an inconsistent voltage operation starting point. This inconsistency will affect the consistency of the subsequent pixel circuit voltage operation And the luminous performance of the light emitting circuit.

另外，當畫素電路以較低頻率進行更新時，非導通狀態電晶體之漏電流會因而長時間影響畫素電路內部節點的電壓而導致發光電路的亮度不穩定。 In addition, when the pixel circuit is updated at a lower frequency, the leakage current of the non-conducting state transistor may affect the voltage of the internal node of the pixel circuit for a long time, resulting in unstable brightness of the light emitting circuit.

基於上述兩因素，使畫素電路能不受發光元件兩端的電壓差而有一致的電壓操作起始點以及不受低更新頻率時長時間受到電晶體漏電流之影響是相當重要的課題。 Based on the above two factors, it is a very important issue to enable the pixel circuit to have a consistent voltage operation starting point without being affected by the voltage difference across the light-emitting element and to be affected by transistor leakage current for a long period of time at a low refresh frequency.

本揭示文件的一實施例中，一種畫素電路包含驅動電晶體、第一電晶體、第二電晶體、資料寫入電路、 第一開關電路、第二開關電路、重置電路、電容及發光電路。驅動電晶體、第一電晶體及第二電晶體包含第一端、第二端及控制端。該驅動電晶體的該第一端耦接於第一節點，驅動電晶體的第二端耦接於第二節點，驅動電晶體的控制端耦接於第三節點。第一電晶體的第一端耦接於驅動電晶體的控制端，第一電晶體該第二端耦接於驅動電晶體的第一端，第一電晶體的控制端用以接收第一訊號，第一電晶體根據第一訊號而選擇性地導通。第二電晶體的第一端耦接於驅動電晶體的控制端，第二電晶體的第二端耦接於驅動電晶體的第二端，第二電晶體的控制端用以接收第二訊號，第二電晶體根據第二訊號而選擇性地導通。資料寫入電路耦接於驅動電晶體的第一端，資料寫入電路接收資料電壓並響應於第三訊號而傳遞資料電壓到第一節點。第一開關電路耦接於驅動電晶體的第一端，用以接收第一電壓，第一開關電路響應於控制訊號而傳遞第一電壓到驅動電晶體的第一端。第二開關電路耦接於驅動電晶體的該第二端，用以接收第二節點的電壓，第二開關電路響應於控制訊號而將驅動電晶體與發光單元連接。重置電路耦接於驅動電晶體的第二端，用以接收第二電壓，重置電路響應於第一訊號而傳遞第二電壓到驅動電晶體的第二端。電容，包含第一端及第二端，電容的第一端耦接於第一開關電路，電容的第二端耦接於驅動電晶體的控制端、第一電晶體的第一端及第二電晶體的第一端。發光電路耦接於第二開關電路，用以響應於第二開關電路的導通狀態而選擇 性地發光。 In an embodiment of the present disclosure, a pixel circuit includes a driving transistor, a first transistor, a second transistor, a data writing circuit, The first switch circuit, the second switch circuit, the reset circuit, the capacitor and the light emitting circuit. The driving transistor, the first transistor, and the second transistor include a first end, a second end, and a control end. The first end of the driving transistor is coupled to the first node, the second end of the driving transistor is coupled to the second node, and the control end of the driving transistor is coupled to the third node. The first end of the first transistor is coupled to the control end of the driving transistor, the second end of the first transistor is coupled to the first end of the driving transistor, and the control end of the first transistor is used to receive the first signal , The first transistor is selectively turned on according to the first signal. The first end of the second transistor is coupled to the control end of the driving transistor, the second end of the second transistor is coupled to the second end of the driving transistor, and the control end of the second transistor is used to receive the second signal , The second transistor is selectively turned on according to the second signal. The data writing circuit is coupled to the first end of the driving transistor. The data writing circuit receives the data voltage and transmits the data voltage to the first node in response to the third signal. The first switch circuit is coupled to the first end of the driving transistor to receive the first voltage. The first switch circuit transmits the first voltage to the first end of the driving transistor in response to the control signal. The second switch circuit is coupled to the second end of the driving transistor to receive the voltage of the second node. The second switching circuit connects the driving transistor and the light emitting unit in response to the control signal. The reset circuit is coupled to the second end of the driving transistor to receive the second voltage. The reset circuit transmits the second voltage to the second end of the driving transistor in response to the first signal. The capacitor includes a first terminal and a second terminal. The first terminal of the capacitor is coupled to the first switching circuit, and the second terminal of the capacitor is coupled to the control terminal of the driving transistor, the first terminal of the first transistor, and the second terminal The first end of the transistor. The light emitting circuit is coupled to the second switch circuit for selecting in response to the conduction state of the second switch circuit Glowing sexually.

綜上所述，藉由控制第一節點、第二節點及第三節點的電壓，穩定畫素電路中不同節點的電壓，改善畫素電路操作時的穩定性。 In summary, by controlling the voltages of the first node, the second node, and the third node, the voltages of different nodes in the pixel circuit are stabilized, and the stability of the pixel circuit during operation is improved.

100‧‧‧顯示面板 100‧‧‧Display panel

110‧‧‧源極驅動器 110‧‧‧ source driver

120‧‧‧閘極驅動器 120‧‧‧Gate driver

122‧‧‧移位暫存電路 122‧‧‧shift temporary storage circuit

130‧‧‧發光控制器 130‧‧‧Light Controller

132‧‧‧發光控制電路 132‧‧‧Lighting control circuit

140‧‧‧影像顯示區 140‧‧‧Image display area

142、142-1、142-2‧‧‧畫素電路 142, 142-1, 142-2 ‧‧‧ pixel circuit

142a‧‧‧資料寫入電路 142a‧‧‧Data writing circuit

142b‧‧‧第一開關電路 142b‧‧‧ First switch circuit

142c‧‧‧第二開關電路 142c‧‧‧Second switch circuit

142d‧‧‧重置電路 142d‧‧‧Reset circuit

142e‧‧‧發光電路 142e‧‧‧Lighting circuit

T1~T7‧‧‧電晶體 T1~T7‧‧‧‧transistor

OVDD、OVSS、VINT‧‧‧電壓 OVDD, OVSS, VINT‧‧‧ voltage

VD‧‧‧資料電壓 VD‧‧‧Data voltage

CS‧‧‧電容 CS‧‧‧Capacitor

S1[N-1]、S1[N]、S2[N]‧‧‧訊號 S1[N-1], S1[N], S2[N]‧‧‧signal

EM[N]‧‧‧控制訊號 EM[N]‧‧‧Control signal

A、B、C‧‧‧節點 A, B, C ‧‧‧ node

GL1、GL2、GL3、GLN、GLM、EL1、EL2、EL3、ELN、ELM‧‧‧掃描線 GL1, GL2, GL3, GLN, GLM, EL1, EL2, EL3, ELN, ELM ‧‧‧ scanning line

SL1、SL2、SL3、SLK‧‧‧資料線 SL1, SL2, SL3, SLK‧‧‧‧ data cable

TP1‧‧‧第一重置時間 TP1‧‧‧First reset time

TP2‧‧‧第二重置時間 TP2‧‧‧Second reset time

TP3‧‧‧資料寫入時間 TP3‧‧‧Data writing time

TP3a‧‧‧維持時間 TP3a‧‧‧Maintain time

TP4‧‧‧發光時間 TP4‧‧‧Lighting time

第1圖繪示根據本揭示文件之一實施例的顯示面板示意圖。 FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present disclosure.

第2圖繪示根據本揭示文件之一實施例的顯示面板功能方塊圖。 FIG. 2 is a functional block diagram of a display panel according to an embodiment of the present disclosure.

第3圖繪示根據本揭示文件之一實施例的畫素電路圖。 FIG. 3 shows a pixel circuit diagram according to an embodiment of this disclosure.

第4圖繪示對應於第3圖畫素電路的訊號時序圖。 FIG. 4 shows a signal timing diagram corresponding to the third pixel circuit.

第5圖繪示根據本揭示文件之一實施例的畫素電路於第一重置時間的操作示意圖。 FIG. 5 is a schematic diagram illustrating the operation of the pixel circuit at the first reset time according to an embodiment of the present disclosure.

第6圖繪示根據本揭示文件之一實施例的畫素電路於第二重置時間的操作示意圖。 FIG. 6 is a schematic diagram illustrating the operation of the pixel circuit according to an embodiment of the present disclosure at the second reset time.

第7圖繪示根據本揭示文件之一實施例的畫素電路於寫入時間的操作示意圖。 FIG. 7 is a schematic diagram illustrating the operation of the pixel circuit at the writing time according to an embodiment of the present disclosure.

第8圖繪示根據本揭示文件之一實施例的畫素電路於發光時間的操作示意圖。 FIG. 8 is a schematic diagram illustrating the operation of the pixel circuit during the light-emitting time according to an embodiment of the disclosure.

第9圖繪示根據本揭示文件之另一實施例的畫素電路圖。 FIG. 9 shows a pixel circuit diagram according to another embodiment of this disclosure.

第10圖繪示根據本揭示文件之另一實施例的畫素電路 圖。 FIG. 10 shows a pixel circuit according to another embodiment of this disclosure Figure.

第11圖繪示根據本揭示文件之另一實施例的訊號時序圖。 FIG. 11 shows a signal timing diagram according to another embodiment of this disclosure.

在本文中所使用的用詞「包含」、「具有」等等，均為開放性的用語，即意指「包含但不限於」。此外，本文中所使用之「及/或」，包含相關列舉項目中一或多個項目的任意一個以及其所有組合。 The terms "including", "having", etc. used in this article are all open terms, meaning "including but not limited to." In addition, "and/or" as used in this document includes any one or more of the listed items and all combinations thereof.

於本文中，當一元件被稱為「連結」或「耦接」時，可指「電性連接」或「電性耦接」。「連結」或「耦接」亦可用以表示二或多個元件間相互搭配操作或互動。此外，雖然本文中使用「第一」、「第二」、...等用語描述不同元件，該用語僅是用以區別以相同技術用語描述的元件或操作。除非上下文清楚指明，否則該用語並非特別指稱或暗示次序或順位，亦非用以限定本揭示文件。 In this article, when an element is referred to as "connected" or "coupled", it can be referred to as "electrically connected" or "electrically coupled." "Link" or "coupling" can also be used to indicate that two or more components cooperate or interact with each other. In addition, although terms such as "first", "second", etc. are used herein to describe different elements, the terms are only used to distinguish elements or operations described in the same technical terms. Unless the context clearly dictates, the term does not specifically refer to or imply the order or order, nor is it intended to limit the present disclosure.

請參考第1圖，第1圖繪示根據本揭示文件之一實施例的顯示面板示意圖。如第1圖所示，顯示面板100包含源極驅動器110、閘極驅動器120、發光控制器130及影像顯示區140。影像顯示區140由多個掃描線GL1~GLM、多個發光控制線EL1~ELM及多個資料線SL1~SLK交錯配置而成，包含多個畫素電路142。數量K與M可以根據實際應用的面板解析度而有所調整。源極驅動器110藉由K個資料線SL1~SLK輸出源極驅動訊號到影像顯示區140給對應 的畫素電路142。閘極驅動器120藉由M個掃描線GL1~GLM輸出閘極驅動訊號到影像顯示區140給對應的畫素電路142。於一實施例中，顯示面板100為解析度1920x1080的螢幕，M為1080，K為1920。 Please refer to FIG. 1, which illustrates a schematic diagram of a display panel according to an embodiment of the present disclosure. As shown in FIG. 1, the display panel 100 includes a source driver 110, a gate driver 120, a light emitting controller 130 and an image display area 140. The image display area 140 is composed of a plurality of scan lines GL1 to GLM, a plurality of light emission control lines EL1 to ELM and a plurality of data lines SL1 to SLK, and includes a plurality of pixel circuits 142. The quantity K and M can be adjusted according to the actual panel resolution. The source driver 110 outputs the source driving signal to the image display area 140 through the K data lines SL1~SLK to the corresponding 的Pixel circuit 142. The gate driver 120 outputs the gate driving signal to the image display area 140 through the M scanning lines GL1~GLM to the corresponding pixel circuit 142. In one embodiment, the display panel 100 is a screen with a resolution of 1920x1080, M is 1080, and K is 1920.

請參考第2圖，第2圖繪示根據本揭示文件之一實施例的顯示面板功能方塊圖。閘極驅動器120包含複數個移位暫存電路122彼此串接，移位暫存電路122用以輸出脈波訊號到對應的畫素電路142。 Please refer to FIG. 2, which illustrates a functional block diagram of a display panel according to an embodiment of the present disclosure. The gate driver 120 includes a plurality of shift register circuits 122 connected in series with each other. The shift register circuit 122 is used to output a pulse signal to the corresponding pixel circuit 142.

應注意的是，為了方便說明，在第2圖中僅繪示第一級及第二級移位暫存電路122，實際數量不以此為限。第一級移位暫存電路122用以產生訊號S1[1]及訊號S2[1]，第二級移位暫存電路122用以產生訊號S1[2]及訊號S2[2]，以此類推，第N級移位暫存電路用以產生輸出訊號S1[N]及S2[N]。而每一級的移位暫存電路的輸出訊號會再輸入到下一級移位暫存電路，如第2圖所示，每一級的移位暫存電路都藉由上一級的輸出訊號當作輸入訊號，達到當前一級連動下一級的效果。 It should be noted that, for convenience of description, only the first-stage and second-stage shift register circuits 122 are shown in FIG. 2, and the actual number is not limited to this. The first-stage shift register circuit 122 is used to generate the signal S1[1] and the signal S2[1], and the second-stage shift register circuit 122 is used to generate the signal S1[2] and the signal S2[2]. By analogy, the Nth stage shift register circuit is used to generate output signals S1[N] and S2[N]. The output signal of the shift register circuit of each stage will be input to the shift register circuit of the next stage. As shown in Figure 2, the shift register circuit of each stage uses the output signal of the previous stage as the input The signal achieves the effect of linking the next level with the current level.

發光控制器130包含複數個發光控制電路132彼此串接，發光控制電路132用以輸出脈波訊號到對應的畫素電路142。相同地，為了方便說明，在第2圖中僅繪示第一級及第二級發光控制電路132，實際數量不以此為限。第一級發光控制電路132用以產生控制訊號EM[1]，第二級發光控制電路132用以產生控制訊號EM[2]，以此類推，第N級發光控制電路132用以產生控制訊號EM[N]。每一級的發 光控制電路的輸出訊號會再輸入到下一級發光控制電路，如第2圖所示。 The light emitting controller 130 includes a plurality of light emitting control circuits 132 connected in series with each other. The light emitting control circuit 132 is used to output a pulse signal to the corresponding pixel circuit 142. Similarly, for convenience of description, only the first-stage and second-stage light emission control circuits 132 are shown in FIG. 2, and the actual number is not limited to this. The first-level light-emission control circuit 132 is used to generate the control signal EM[1], the second-level light-emission control circuit 132 is used to generate the control signal EM[2], and so on, the N-th level light-emission control circuit 132 is used to generate the control signal EM[N]. Hair at each level The output signal of the light control circuit will be input to the next stage of the light emission control circuit, as shown in Figure 2.

第N排的畫素電路142接收由移位暫存電路122輸出的訊號S1[N]及訊號S2[N]、發光控制電路132輸出的控制訊號EM[N]及源極驅動器110輸出的資料電壓VD。於一實施例中，畫素電路142接收由當級移位暫存電路122輸出的訊號S1[N]、訊號S2[N]及上一級移位暫存電路122輸出的訊號S1[N-1]。 The pixel circuit 142 in the Nth row receives the signals S1[N] and S2[N] output from the shift register circuit 122, the control signal EM[N] output from the light emission control circuit 132, and the data output from the source driver 110 Voltage VD. In one embodiment, the pixel circuit 142 receives the signal S1[N], the signal S2[N] output by the current stage shift register circuit 122 and the signal S1[N-1 output by the previous stage shift register circuit 122 ].

請參考第3圖，第3圖繪示根據本揭示文件之一實施例的畫素電路圖。此實施例以第N個畫素電路作為例子說明，畫素電路142包含電晶體T1、電晶體T2、電晶體T3、資料寫入電路142a、第一開關電路142b、第二開關電路142c、重置電路142d、發光電路142e及電容CS。 Please refer to FIG. 3, which illustrates a pixel circuit diagram according to an embodiment of the present disclosure. This embodiment uses the Nth pixel circuit as an example. The pixel circuit 142 includes a transistor T1, a transistor T2, a transistor T3, a data writing circuit 142a, a first switching circuit 142b, a second switching circuit 142c, and The circuit 142d, the light emitting circuit 142e, and the capacitor CS.

電晶體T1、電晶體T2及電晶體T3均包含第一端、第二端及控制端。電晶體T1的第一端耦接於節點A，電晶體T1的第二端耦接於節點B，電晶體T1的控制端耦接於節點C，電晶體T1根據節點C的電壓而產生決定發光電路142e亮度之驅動電流。電晶體T2的第一端耦接於電晶體T1的控制端，電晶體T2的第二端耦接於電晶體T1的第一端，電晶體T2的控制端用以接收訊號S1[N-1]，電晶體T2根據訊號S1[N-1]而選擇性地導通。電晶體T3的第一端耦接於電晶體T1的控制端，電晶體T3的第二端耦接於電晶體T1的第二端，電晶體T3的控制端用以接收訊號S1[N]，其中電晶體T3根據訊號S1[N]而選擇性地導通。 Transistor T1, transistor T2 and transistor T3 all include a first end, a second end and a control end. The first end of the transistor T1 is coupled to the node A, the second end of the transistor T1 is coupled to the node B, the control end of the transistor T1 is coupled to the node C, and the transistor T1 generates the determined light according to the voltage of the node C Drive current for the brightness of circuit 142e. The first end of the transistor T2 is coupled to the control end of the transistor T1, the second end of the transistor T2 is coupled to the first end of the transistor T1, and the control end of the transistor T2 is used to receive the signal S1[N-1 ], the transistor T2 is selectively turned on according to the signal S1 [N-1]. The first end of the transistor T3 is coupled to the control end of the transistor T1, the second end of the transistor T3 is coupled to the second end of the transistor T1, and the control end of the transistor T3 is used to receive the signal S1[N], The transistor T3 is selectively turned on according to the signal S1[N].

資料寫入電路142a耦接於電晶體T1的第一端，用以接收資料電壓VD，資料寫入電路142a響應於訊號S2[N]而傳遞資料電壓VD到節點A。第一開關電路142b耦接於電晶體T1的第一端，第一開關電路142b用以接收電壓OVDD，電壓OVDD可以是但不限於一高電壓，第一開關電路142b響應於控制訊號EM[N]而傳遞電壓OVDD到電晶體T1的第一端。第二開關電路142c耦接於電晶體T1的第二端，第二開關電路142c響應於控制訊號EM[N]而將電晶體T1與發光電路連接。重置電路142d耦接於電晶體T1的第二端，重置電路142d用以接收電壓VINT，重置電路142d響應於訊號S1[N-1]而傳遞電壓VINT到電晶體T1的第二端。電容CS包含第一端及第二端，電容CS的第一端耦接於第一開關電路142b，電容CS的第二端耦接於電晶體T1的控制端、電晶體T2的第一端及電晶體T3的第一端。發光電路142e耦接於第二開關電路142c，並用以響應於第二開關電路142c的導通狀態而選擇性地發光。 The data writing circuit 142a is coupled to the first end of the transistor T1 for receiving the data voltage VD. The data writing circuit 142a transmits the data voltage VD to the node A in response to the signal S2[N]. The first switch circuit 142b is coupled to the first end of the transistor T1. The first switch circuit 142b is used to receive the voltage OVDD. The voltage OVDD may be but not limited to a high voltage. The first switch circuit 142b is responsive to the control signal EM[N ] And transfer the voltage OVDD to the first end of the transistor T1. The second switch circuit 142c is coupled to the second end of the transistor T1. The second switch circuit 142c connects the transistor T1 and the light emitting circuit in response to the control signal EM[N]. The reset circuit 142d is coupled to the second terminal of the transistor T1. The reset circuit 142d is used to receive the voltage VINT. The reset circuit 142d transmits the voltage VINT to the second terminal of the transistor T1 in response to the signal S1[N-1]. . The capacitor CS includes a first terminal and a second terminal. The first terminal of the capacitor CS is coupled to the first switch circuit 142b, and the second terminal of the capacitor CS is coupled to the control terminal of the transistor T1 and the first terminal of the transistor T2 and The first end of transistor T3. The light emitting circuit 142e is coupled to the second switch circuit 142c, and is used to selectively emit light in response to the on state of the second switch circuit 142c.

於一實施例中，資料寫入電路142a包含電晶體T4，電晶體T4包含第一端、第二端及控制端，電晶體T4的第一端用以接收資料電壓VD，電晶體T4的第二端耦接於電晶體T1的第一端，電晶體T4的控制端用以接收訊號S2[N]，並根據訊號S2[N]而選擇性地導通。第一開關電路142b包含電晶體T5，電晶體T5包含第一端、第二端及控制端，電晶體T5的第一端用以接收電壓OVDD，電晶體T5的第二端耦接於電晶體T1的第一端，電晶體T5的控制端用以 接收控制訊號EM[N]，電晶體T5根據控制訊號EM[N]而選擇性地導通。第二開關電路142c包含電晶體T6，電晶體T6包含第一端、第二端及控制端，電晶體T6的第一端耦接於電晶體T1的第二端，電晶體T6的第二端耦接於發光電路142e，電晶體T6的控制端用以接收控制訊號EM[N]，電晶體T6根據控制訊號EM[N]而選擇性地導通。 In one embodiment, the data writing circuit 142a includes a transistor T4. The transistor T4 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor T4 is used to receive the data voltage VD, and the first terminal of the transistor T4 The two ends are coupled to the first end of the transistor T1, and the control end of the transistor T4 is used to receive the signal S2[N] and selectively conduct according to the signal S2[N]. The first switching circuit 142b includes a transistor T5. The transistor T5 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor T5 is used to receive the voltage OVDD. The second terminal of the transistor T5 is coupled to the transistor The first end of T1, the control end of transistor T5 is used to Receiving the control signal EM[N], the transistor T5 is selectively turned on according to the control signal EM[N]. The second switching circuit 142c includes a transistor T6. The transistor T6 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor T6 is coupled to the second terminal of the transistor T1, and the second terminal of the transistor T6 Coupled to the light emitting circuit 142e, the control terminal of the transistor T6 is used to receive the control signal EM[N], and the transistor T6 is selectively turned on according to the control signal EM[N].

於一實施例中，重置電路142d包含電晶體T7，電晶體T7包含第一端、第二端及控制端，電晶體T7的第一端耦接於電晶體T1的第二端，電晶體T7的第二端用以接收電壓VINT，電壓VINT可以是但不限於一低電壓，電晶體T7的控制端用以接收訊號S1[N-1]，電晶體T7根據訊號S1[N-1]而選擇性地導通。電容CS包含第一端及第二端，電容CS的第一端耦接於第一開關電路142b，電容CS的第二端耦接於電晶體T1的控制端、電晶體T2的第一端及電晶體T3的第一端。發光電路142e包含第一端及第二端，發光電路142e的第一端耦接於第二開關電路142c，發光電路142e的第二端耦接於電壓OVSS，電壓OVSS可以是但不限於一低電壓，發光電路142e響應於第二開關電路142c的導通狀態而選擇性地發光，發光電路142e可以以一發光二極體實作。 In one embodiment, the reset circuit 142d includes a transistor T7. The transistor T7 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor T7 is coupled to the second terminal of the transistor T1. The second terminal of T7 is used to receive the voltage VINT. The voltage VINT may be but not limited to a low voltage. The control terminal of the transistor T7 is used to receive the signal S1[N-1]. The transistor T7 is based on the signal S1[N-1] And selectively turn on. The capacitor CS includes a first terminal and a second terminal. The first terminal of the capacitor CS is coupled to the first switch circuit 142b, and the second terminal of the capacitor CS is coupled to the control terminal of the transistor T1 and the first terminal of the transistor T2 and The first end of transistor T3. The light emitting circuit 142e includes a first end and a second end. The first end of the light emitting circuit 142e is coupled to the second switch circuit 142c. The second end of the light emitting circuit 142e is coupled to the voltage OVSS. The voltage OVSS may be but not limited to a low In response to the voltage, the light emitting circuit 142e selectively emits light in response to the on state of the second switching circuit 142c, and the light emitting circuit 142e may be implemented with a light emitting diode.

請參考第4圖，第4圖繪示對應於第3圖畫素電路的訊號時序圖。第4圖包含第一重置時間TP1、第二重置時間TP2、寫入時間TP3及發光時間TP4。在此實施例中，訊號S1[N]及控制訊號EM[N]為兩個電壓位準相反的訊 號，以下詳細介紹畫素電路142在各個時間區間中的操作模式。 Please refer to FIG. 4, which shows a signal timing diagram corresponding to the third pixel circuit. FIG. 4 includes the first reset time TP1, the second reset time TP2, the write time TP3, and the light emission time TP4. In this embodiment, the signal S1[N] and the control signal EM[N] are two signals with opposite voltage levels No., the operation mode of the pixel circuit 142 in each time interval is described in detail below.

第5圖繪示根據本揭示文件之一實施例的畫素電路於第一重置時間TP1的操作示意圖。為使第5圖所示之操作模式易於理解，請同時參考第4圖及第5圖。於第一重置時間TP1中，訊號S1[N-1]為低電位，訊號S1[N]為高電位，訊號S2[N]為高電位，控制訊號EM[N]為低電位。電晶體T2、T5、T6及T7導通，電晶體T5將電壓OVDD傳遞到節點A，電晶體T2將節點A的電壓傳遞到節點C。電晶體T6及T7導通將電壓VINT傳遞到發光電路142e中的發光二極體的陽極端，電壓VINT小於電壓OVSS與發光二極體的臨界電壓之和，使得發光二極體關閉。在第一重置時間TP1區間時，節點A及節點C的電壓皆等同於電壓OVDD，電晶體T1的源極端與閘極端的電壓差VSG沒有大於臨界電壓VTH，因此電晶體T1關閉，使節點B保持在電壓VINT。於第一重置時間TP1的操作中，藉由控制節點B的電壓為電壓VINT，以重置發光二極體的陽極端的電壓。 FIG. 5 is a schematic diagram illustrating the operation of the pixel circuit at the first reset time TP1 according to an embodiment of the present disclosure. To make the operation mode shown in Figure 5 easy to understand, please refer to Figure 4 and Figure 5 at the same time. During the first reset time TP1, the signal S1[N-1] is low, the signal S1[N] is high, the signal S2[N] is high, and the control signal EM[N] is low. Transistors T2, T5, T6 and T7 are turned on, transistor T5 passes the voltage OVDD to node A, and transistor T2 passes the voltage of node A to node C. The transistors T6 and T7 are turned on to transfer the voltage VINT to the anode terminal of the light-emitting diode in the light-emitting circuit 142e. The voltage VINT is less than the sum of the voltage OVSS and the critical voltage of the light-emitting diode, so that the light-emitting diode is turned off. During the first reset time TP1, the voltages of node A and node C are equal to the voltage OVDD, and the voltage difference V SG between the source terminal and the gate terminal of transistor T1 is not greater than the threshold voltage V TH , so transistor T1 is turned off, Keep node B at voltage VINT. During the operation of the first reset time TP1, the voltage at the anode end of the light emitting diode is reset by controlling the voltage of the node B to be the voltage VINT.

第6圖繪示根據本揭示文件之一實施例的畫素電路於第二重置時間TP2的操作示意圖。為使第6圖所示之操作模式易於理解，請同時參考第4圖及第6圖。於第二重置時間TP2中，訊號S1[N-1]為低電位，訊號S1[N]為低電位，訊號S2[N]為高電位，控制訊號EM[N]為高電位。電晶體T2、電晶體T3及電晶體T7導通，使電壓VINT傳遞到節點A、節點B及節點C。同樣地，由於節點A及節點C的電 壓相同，電晶體T1的源極端與閘極端的電壓差值VSG小於臨界電壓VTH，因此電晶體T1關閉。因電晶體T6關閉，發光二極體的陽極端的電壓維持為第一重置時間TP1中所接收到的電壓VINT，電壓VINT小於電壓OVSS與發光二極體的臨界電壓之和，使得發光二極體關閉。於第二重置時間TP2的操作中，藉由控制節點A、節點B及節點C的電壓，以重置電晶體T1的三個端點的電壓，使得畫素電路142有一致的電壓操作起始點。 FIG. 6 is a schematic diagram illustrating the operation of the pixel circuit at the second reset time TP2 according to an embodiment of the present disclosure. To make the operation mode shown in Figure 6 easy to understand, please refer to Figure 4 and Figure 6 at the same time. During the second reset time TP2, the signal S1[N-1] is low, the signal S1[N] is low, the signal S2[N] is high, and the control signal EM[N] is high. The transistor T2, the transistor T3, and the transistor T7 are turned on, so that the voltage VINT is transmitted to the node A, the node B, and the node C. Similarly, since the voltages at the nodes A and C are the same, the voltage difference V SG between the source terminal and the gate terminal of the transistor T1 is less than the critical voltage V TH , so the transistor T1 is turned off. Because the transistor T6 is turned off, the voltage at the anode end of the light-emitting diode is maintained at the voltage VINT received in the first reset time TP1, and the voltage VINT is less than the sum of the voltage OVSS and the critical voltage of the light-emitting diode, so that the light-emitting diode The polar body is turned off. During the operation of the second reset time TP2, the voltages of the three terminals of the transistor T1 are reset by controlling the voltages of the nodes A, B, and C, so that the pixel circuit 142 has a consistent voltage operation Starting point.

第7圖繪示根據本揭示文件之一實施例的畫素電路於寫入時間TP3的操作示意圖。為使第7圖所示之操作模式易於理解，請同時參考第4圖及第7圖。於寫入時間TP3中，訊號S1[N-1]為高電位，訊號S1[N]為低電位，訊號S2[N]為低電位，控制訊號EM[N]為高電位，電晶體T3、T4導通。電晶體T4輸出資料電壓VD到節點A，此時，電晶體T1的源極端與閘極端的電壓差值VSG大於臨界電壓VTH，電晶體T1導通，資料電壓VD經由電晶體T1的第一端節點A對電晶體T1的第二端節點B與控制端節點C充電。節點A的電壓為資料電壓VD，節點B及節點C的電壓為資料電壓VD減掉電晶體T1的臨界電壓VTH(VD-VTH)。因電晶體T6關閉，發光二極體的陽極端的電壓維持為第一重置時間TP1中所接收到的電壓VINT，電壓VINT小於電壓OVSS與發光二極體的臨界電壓之和，使得發光二極體關閉。 FIG. 7 is a schematic diagram illustrating the operation of the pixel circuit at the writing time TP3 according to an embodiment of the present disclosure. To make the operation mode shown in Figure 7 easy to understand, please refer to Figure 4 and Figure 7 at the same time. In the writing time TP3, the signal S1[N-1] is high potential, the signal S1[N] is low potential, the signal S2[N] is low potential, the control signal EM[N] is high potential, the transistor T3, T4 is on. Transistor T4 outputs the data voltage VD to node A. At this time, the voltage difference V SG between the source terminal and the gate terminal of transistor T1 is greater than the critical voltage V TH , transistor T1 is turned on, and the data voltage VD passes through the first of transistor T1 The terminal node A charges the second terminal node B and the control terminal node C of the transistor T1. The voltage at node A is the data voltage VD, and the voltages at node B and node C are the data voltage VD minus the critical voltage V TH (VD-V TH ) of the transistor T1. Because the transistor T6 is turned off, the voltage at the anode end of the light-emitting diode is maintained at the voltage VINT received in the first reset time TP1, and the voltage VINT is less than the sum of the voltage OVSS and the critical voltage of the light-emitting diode, so that the light-emitting diode The polar body is turned off.

第8圖繪示根據本揭示文件之一實施例的畫素電路於發光時間TP4的操作示意圖。為使第8圖所示之操作 模式易於理解，請同時參考第4圖及第8圖。於發光時間TP4中，訊號S1[N-1]為高電位，訊號S1[N]為高電位，訊號S2[N]為高電位，控制訊號EM[N]為低電位，電晶體T5及T6導通。節點C的電壓維持在上一階段的資料電壓VD-臨界電壓VTH，而節點A的電壓因為電晶體T5導通而為電壓OVDD。 FIG. 8 is a schematic diagram illustrating the operation of the pixel circuit during the light-emitting time TP4 according to an embodiment of the present disclosure. To make the operation mode shown in Figure 8 easy to understand, please refer to Figure 4 and Figure 8 at the same time. In the lighting time TP4, the signal S1[N-1] is high potential, the signal S1[N] is high potential, the signal S2[N] is high potential, the control signal EM[N] is low potential, the transistors T5 and T6 Turn on. The voltage of the node C is maintained at the data voltage VD-threshold voltage V TH of the previous stage, and the voltage of the node A is the voltage OVDD because the transistor T5 is turned on.

因此電晶體T5、T1及T6將形成一個驅動路徑，產生電流IOLED驅動發光二極體。於一實施例中，電流IOLED的大小可藉由電晶體飽和區電流公式表示為：IOLED=(1/2)k(OVDD-VD)2，其中，k表示電晶體T1的載子遷移率(carrier mobility)、閘極氧化層的單位電容大小以及閘極寬長比三者的乘積。由上述式子可知，驅動電流IOLED的大小與電晶體T1的臨界電壓無關，所以畫素電路142搭配第4圖的運作實施例可有效補償電晶體T1的臨界電壓變異。 Therefore, the transistors T5, T1 and T6 will form a driving path and generate a current I OLED to drive the light-emitting diode. In an embodiment, the size of the current I OLED can be expressed by the transistor saturation region current formula: I OLED =(1/2)k(OVDD-VD) 2 , where k represents the carrier migration of the transistor T1 The product of carrier mobility, unit capacitance of the gate oxide layer, and gate width to length ratio. It can be seen from the above formula that the size of the driving current I OLED is independent of the threshold voltage of the transistor T1, so the pixel circuit 142 combined with the operation embodiment of FIG. 4 can effectively compensate for the threshold voltage variation of the transistor T1.

特別注意到，於發光時間TP4時，為了維持電晶體T1***作在飽和區，電晶體T1之第二端節點B的電壓必須小於電晶體T1之控制端節點C的電壓，因此透過關閉的電晶體T3會對於電晶體T1之控制端節點C形成一個低凖位電壓的漏電路徑，而本揭示文件的畫素電路142於發光時間TP4時，透過關閉的電晶體T2將電晶體T1第一端節點A與控制端節點C連接，節點A接收到電壓OVDD且會高於節點C的電壓，因而電晶體T2會對於電晶體T1之控制端節點C形成一個高凖位電壓的漏電路徑。藉由上述一低凖位電壓的漏電路徑與一高準位電壓的漏電路徑的平衡，以穩定電晶體T1之控制端節點C的 電壓，使得發光二極體於發光時間TP4時的亮度更為穩定。 In particular, at the light emission time TP4, in order to maintain the transistor T1 in the saturation region, the voltage of the second terminal node B of the transistor T1 must be less than the voltage of the control terminal node C of the transistor T1. The crystal T3 will form a low voltage leakage path to the control terminal node C of the transistor T1, and the pixel circuit 142 of the present disclosure will turn the transistor T1 on the first end through the closed transistor T2 at the light emitting time TP4 The node A is connected to the control node C. The node A receives the voltage OVDD and will be higher than the voltage of the node C. Therefore, the transistor T2 will form a high voltage leakage path for the control node C of the transistor T1. By balancing the leakage path of a low voltage and the leakage path of a high voltage, the control terminal node C of the transistor T1 is stabilized The voltage makes the brightness of the light emitting diode more stable at the light emitting time TP4.

於另一實施例中，第一開關電路142b及第二開關電路142c中的電晶體T5及T6為n型電晶體，請參考第9圖，第9圖繪示根據本揭示文件之另一實施例的畫素電路圖。畫素電路142-1中，電晶體T5及電晶體T6的控制端用以接收訊號S1[N]，電晶體T5及電晶體T6根據訊號S1[N]而選擇性地導通。在此實施例中，將電晶體T5及電晶體T6的控制端訊號從控制訊號EM[N]改為訊號S1[N]，使畫素電路142從使用四種訊號改為使用三種，進而減少電路複雜度。 In another embodiment, the transistors T5 and T6 in the first switching circuit 142b and the second switching circuit 142c are n-type transistors, please refer to FIG. 9, which illustrates another implementation according to the present disclosure Example pixel circuit diagram. In the pixel circuit 142-1, the control terminals of the transistor T5 and the transistor T6 are used to receive the signal S1[N], and the transistor T5 and the transistor T6 are selectively turned on according to the signal S1[N]. In this embodiment, the control signals of the transistors T5 and T6 are changed from the control signal EM[N] to the signal S1[N], so that the pixel circuit 142 is changed from using four types of signals to using three types, thereby reducing Circuit complexity.

於另一實施例中，電晶體T3為n型電晶體。請參考第10圖，第10圖繪示根據本揭示文件之另一實施例的畫素電路圖。畫素電路142-2中，電晶體T3的控制端用以接收控制訊號EM[N]，電晶體T3根據控制訊號EM[N]而選擇性地導通。在此實施例中，將電晶體T3的控制端訊號從訊號S1[N]改為控制訊號EM[N]，使畫素電路142從使用四種訊號改為使用三種，進而減少電路複雜度。 In another embodiment, the transistor T3 is an n-type transistor. Please refer to FIG. 10, which illustrates a pixel circuit diagram according to another embodiment of the present disclosure. In the pixel circuit 142-2, the control terminal of the transistor T3 is used to receive the control signal EM[N], and the transistor T3 is selectively turned on according to the control signal EM[N]. In this embodiment, the control signal of the transistor T3 is changed from the signal S1[N] to the control signal EM[N], so that the pixel circuit 142 is changed from using four types of signals to using three types, thereby reducing circuit complexity.

請參考第11圖，第11圖繪示根據本揭示文件之另一實施例的訊號時序圖。第11圖包含第一重置時間TP1、第二重置時間TP2、寫入時間TP3、維持時間TP3a及發光時間TP4。在此實施例中，將訊號S2[N]的低電位脈波寬度設計成與訊號S1[N-1]及訊號S1[N]的寬度相同，移位暫存電路122設計時，能夠使用同樣的電路架構，進而簡化整體電路的設計複雜度。具體來說，訊號S1[N-1]為訊號 S1[N]的上一級訊號，訊號S2[N]為S1[N]的下一級訊號。 Please refer to FIG. 11, which illustrates a signal timing diagram according to another embodiment of the present disclosure. FIG. 11 includes a first reset time TP1, a second reset time TP2, a write time TP3, a sustain time TP3a, and a light-emitting time TP4. In this embodiment, the low-potential pulse width of the signal S2[N] is designed to be the same as the width of the signal S1[N-1] and the signal S1[N]. The design of the shift temporary storage circuit 122 can use the same Circuit architecture, which simplifies the design complexity of the overall circuit. Specifically, the signal S1[N-1] is a signal The upper level signal of S1[N], the signal S2[N] is the next level signal of S1[N].

綜上所述，藉由在不同操作時間中控制節點A、節點B及節點C的電壓，穩定畫素電路中不同元件的端點電壓，更考慮過往畫素電路於較低頻率的工作模式時，電晶體漏電流造成的畫面不穩定的影響，本揭示文件的畫素電路架構能夠使漏電路徑互相平衡，增加畫素電路的穩定性。 In summary, by controlling the voltages of node A, node B, and node C at different operating times, the terminal voltages of different components in the pixel circuit are stabilized, and the past pixel circuit is considered at a lower frequency operating mode In this case, the pixel circuit architecture of the disclosed document can balance the leakage paths and increase the stability of the pixel circuit.

本領域技術人員應當明白，在各個實施例中，各個電路單元可以由各種類型的數位或類比電路實現，亦可分別由不同的積體電路晶片實現。各個元件亦可整合至單一的積體電路晶片。上述僅為例示，本揭示內容並不以此為限。電子元件如電阻、電容、二極體、電晶體開關等等，皆可由各種適當的元件。舉例來說，電晶體T1~T7可根據需求選用金氧半場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)、雙極性接面型電晶體(Bipolar Junction Transistor，BJT)或其他各種類型的電晶體實作。 Those skilled in the art should understand that, in various embodiments, each circuit unit may be implemented by various types of digital or analog circuits, or may be implemented by different integrated circuit chips. Each component can also be integrated into a single integrated circuit chip. The above is only an example, and the disclosure is not limited thereto. Electronic components such as resistors, capacitors, diodes, transistor switches, etc., can be made of various suitable components. For example, the transistors T1~T7 can be selected according to the requirements of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), Bipolar Junction Transistor (BJT) or other various Types of transistors are implemented.

雖然本揭示內容已以實施方式揭露如上，然其並非用以限定本揭示內容，任何熟習此技藝者，在不脫離本揭示內容之精神和範圍內，當可作各種更動與潤飾，因此本揭示內容之保護範圍當視後附之申請專利範圍所界定者為準。 Although this disclosure has been disclosed as above by way of implementation, it is not intended to limit this disclosure. Anyone who is familiar with this skill can make various changes and modifications within the spirit and scope of this disclosure, so this disclosure The protection scope of the content shall be deemed as defined by the scope of the attached patent application.

142‧‧‧畫素電路 142‧‧‧Pixel circuit

142a‧‧‧資料寫入電路 142a‧‧‧Data writing circuit

142b‧‧‧第一開關電路 142b‧‧‧ First switch circuit

142c‧‧‧第二開關電路 142c‧‧‧Second switch circuit

142d‧‧‧重置電路 142d‧‧‧Reset circuit

142e‧‧‧發光電路 142e‧‧‧Lighting circuit

T1~T7‧‧‧電晶體 T1~T7‧‧‧‧transistor

OVDD、OVSS、VINT‧‧‧電壓 OVDD, OVSS, VINT‧‧‧ voltage

VD‧‧‧資料電壓 VD‧‧‧Data voltage

CS‧‧‧電容 CS‧‧‧Capacitor

S1[N-1]、S1[N]、S2[N]‧‧‧訊號 S1[N-1], S1[N], S2[N]‧‧‧signal

EM[N]‧‧‧控制訊號 EM[N]‧‧‧Control signal

A、B、C‧‧‧節點 A, B, C ‧‧‧ node

Claims (14)

一種畫素電路，包含：一驅動電晶體，包含一第一端、一第二端及一控制端，該驅動電晶體的該第一端耦接於該畫素電路的一第一節點，該驅動電晶體的該第二端耦接於該畫素電路的一第二節點，該驅動電晶體的該控制端耦接於該畫素電路的一第三節點；一第一電晶體，包含一第一端、一第二端及一控制端，該第一電晶體的該第一端耦接於該驅動電晶體的該控制端，該第一電晶體的該第二端耦接於該驅動電晶體的該第一端，該第一電晶體的該控制端用以接收一第一訊號，其中該第一電晶體根據該第一訊號而選擇性地導通；一第二電晶體，包含一第一端、一第二端及一控制端，該第二電晶體的該第一端耦接於該驅動電晶體的該控制端，該第二電晶體的該第二端耦接於該驅動電晶體的該第二端，該第二電晶體的該控制端用以接收一第二訊號，其中該第二電晶體根據該第二訊號而選擇性地導通；一資料寫入電路，耦接於該驅動電晶體的該第一端，用以接收一資料電壓，其中該資料寫入電路響應於一第三訊號而傳遞該資料電壓到該第一節點；一第一開關電路，耦接於該驅動電晶體的該第一端，用以接收一第一電壓，其中該第一開關電路響應於一控制訊號而傳遞該第一電壓到該驅動電晶體的該第一端；一第二開關電路，耦接於該驅動電晶體的該第二端， 用以接收該第二節點的電壓，其中該第二開關電路響應於該控制訊號而選擇性地導通；一重置電路，耦接於該驅動電晶體的該第二端，用以接收一第二電壓，其中該重置電路響應於該第一訊號而傳遞該第二電壓到該驅動電晶體的該第二端；一電容，包含一第一端及一第二端，該電容的該第一端耦接於該第一開關電路，該電容的該第二端耦接於該驅動電晶體的該控制端、該第一電晶體的該第一端及該第二電晶體的該第一端；以及一發光電路，耦接於該第二開關電路，用以響應於該第二開關電路的導通狀態而選擇性地發光。 A pixel circuit includes: a driving transistor including a first terminal, a second terminal and a control terminal, the first terminal of the driving transistor is coupled to a first node of the pixel circuit, the The second end of the driving transistor is coupled to a second node of the pixel circuit, the control end of the driving transistor is coupled to a third node of the pixel circuit; a first transistor includes a A first end, a second end and a control end, the first end of the first transistor is coupled to the control end of the drive transistor, and the second end of the first transistor is coupled to the drive The first end of the transistor, the control end of the first transistor is used to receive a first signal, wherein the first transistor is selectively turned on according to the first signal; a second transistor includes a A first end, a second end and a control end, the first end of the second transistor is coupled to the control end of the drive transistor, and the second end of the second transistor is coupled to the drive The second end of the transistor, the control end of the second transistor is used to receive a second signal, wherein the second transistor is selectively turned on according to the second signal; a data writing circuit is coupled The first end of the driving transistor is used to receive a data voltage, wherein the data writing circuit transmits the data voltage to the first node in response to a third signal; a first switch circuit is coupled to The first end of the driving transistor is used to receive a first voltage, wherein the first switch circuit transmits the first voltage to the first end of the driving transistor in response to a control signal; a second switch A circuit, coupled to the second end of the driving transistor, For receiving the voltage of the second node, wherein the second switch circuit is selectively turned on in response to the control signal; a reset circuit is coupled to the second end of the driving transistor to receive a first Two voltages, wherein the reset circuit transmits the second voltage to the second terminal of the driving transistor in response to the first signal; a capacitor includes a first terminal and a second terminal, and the first terminal of the capacitor One end is coupled to the first switching circuit, the second end of the capacitor is coupled to the control end of the driving transistor, the first end of the first transistor, and the first end of the second transistor And a light-emitting circuit, coupled to the second switch circuit, for selectively emitting light in response to the conduction state of the second switch circuit. 如請求項1所述之畫素電路，其中該資料寫入電路包含：一第三電晶體，包含一第一端、一第二端及一控制端，該第三電晶體的該第一端用以接收該資料電壓，該第三電晶體的該第二端耦接於該驅動電晶體的該第一端，該第三電晶體的該控制端用以接收該第三訊號，其中該第三電晶體根據該第三訊號而選擇性地導通。 The pixel circuit according to claim 1, wherein the data writing circuit includes: a third transistor including a first terminal, a second terminal and a control terminal, and the first terminal of the third transistor For receiving the data voltage, the second end of the third transistor is coupled to the first end of the driving transistor, the control end of the third transistor is used to receive the third signal, wherein the first The transistors are selectively turned on according to the third signal. 如請求項1所述之畫素電路，其中該第一開關電路包含：一第四電晶體，包含一第一端、一第二端及一控制端，該第四電晶體的該第一端用以接收該第一電壓，該第 四電晶體的該第二端耦接於該驅動電晶體的該第一端，該第四電晶體的該控制端用以接收該控制訊號，其中該第四電晶體根據該控制訊號而選擇性地導通。 The pixel circuit according to claim 1, wherein the first switching circuit includes: a fourth transistor including a first terminal, a second terminal and a control terminal, and the first terminal of the fourth transistor For receiving the first voltage, the first The second end of the quad transistor is coupled to the first end of the driving transistor, and the control end of the fourth transistor is used to receive the control signal, wherein the fourth transistor is selectively selected according to the control signal Ground conduction. 如請求項3所述之畫素電路，其中該第二開關電路包含：一第五電晶體，包含一第一端、一第二端及一控制端，該第五電晶體的該第一端耦接於該驅動電晶體的該第二端，該第五電晶體的該第二端耦接於該發光電路，該第五電晶體的該控制端用以接收該控制訊號，其中該第五電晶體根據該控制訊號而選擇性地導通。 The pixel circuit according to claim 3, wherein the second switching circuit includes: a fifth transistor including a first terminal, a second terminal and a control terminal, and the first terminal of the fifth transistor The second end of the fifth transistor is coupled to the second end of the driving transistor, the second end of the fifth transistor is coupled to the light emitting circuit, the control end of the fifth transistor is used to receive the control signal, wherein the fifth The transistor is selectively turned on according to the control signal. 如請求項4所述之畫素電路，其中該第四電晶體及該第五電晶體的每一者包含一n型電晶體及一p型電晶體的其中至少一者，該第四電晶體及該第五電晶體的該控制端用以接收該第二訊號，其中該第四電晶體及該第五電晶體根據該第二訊號而選擇性地導通。 The pixel circuit according to claim 4, wherein each of the fourth transistor and the fifth transistor includes at least one of an n-type transistor and a p-type transistor, the fourth transistor And the control terminal of the fifth transistor is used to receive the second signal, wherein the fourth transistor and the fifth transistor are selectively turned on according to the second signal. 如請求項1所述之畫素電路，其中該重置電路包含：一第六電晶體，包含一第一端、一第二端及一控制端，該第六電晶體的該第一端耦接於該驅動電晶體的該第二端，該第六電晶體的該第二端用以接收該第二電壓，該第六電晶體的該控制端用以接收該第一訊號，其中該第六 電晶體根據該第一訊號而選擇性地導通。 The pixel circuit according to claim 1, wherein the reset circuit includes: a sixth transistor including a first terminal, a second terminal and a control terminal, and the first terminal of the sixth transistor is coupled Connected to the second terminal of the driving transistor, the second terminal of the sixth transistor is used to receive the second voltage, and the control terminal of the sixth transistor is used to receive the first signal, wherein the first six The transistor is selectively turned on according to the first signal. 如請求項1所述之畫素電路，其中該第二電晶體包含一n型電晶體及一p型電晶體的其中至少一者，該第二電晶體的該控制端用以接收該控制訊號，其中該第二電晶體根據該控制訊號而選擇性地導通。 The pixel circuit according to claim 1, wherein the second transistor includes at least one of an n-type transistor and a p-type transistor, and the control terminal of the second transistor is used to receive the control signal , Wherein the second transistor is selectively turned on according to the control signal. 如請求項1所述之畫素電路，其中該第二訊號及該控制訊號為兩個電壓波型相位相反的訊號。 The pixel circuit according to claim 1, wherein the second signal and the control signal are two signals with opposite phases of the voltage waveform. 如請求項1所述之畫素電路，其中該第二訊號為一當級訊號，該第一訊號為一上一級訊號。 The pixel circuit as described in claim 1, wherein the second signal is a local signal and the first signal is an upper-level signal. 如請求項9所述之畫素電路，其中該第二訊號為一當級訊號，該第三訊號為一下一級訊號。 The pixel circuit according to claim 9, wherein the second signal is a local signal and the third signal is a next-level signal. 如請求項1所述之畫素電路，其中該畫素電路操作於一第一重置時間，於該第一重置時間區間時該第一訊號及該控制訊號為低電位，該第一開關電路傳遞該第一電壓到該第一節點，該第一電晶體導通以傳遞該第一節點的電壓到該第三節點，該重置電路傳遞該第二電壓到該第二節點。 The pixel circuit according to claim 1, wherein the pixel circuit operates at a first reset time, and the first signal and the control signal are at a low potential during the first reset time interval, and the first switch The circuit passes the first voltage to the first node, the first transistor is turned on to pass the voltage of the first node to the third node, and the reset circuit passes the second voltage to the second node. 如請求項11所述之畫素電路，其中該畫 素電路操作於一第二重置時間，於該第二重置時間區間時該第一訊號及該第二訊號為低電位，該重置電路傳遞該第二電壓到該第二節點，該第二電晶體導通以傳遞該第二節點的電壓到該第三節點，該第一電晶體導通以傳遞該第三節點的電壓到該第一節點。 The pixel circuit as described in claim 11, wherein the picture The element circuit operates at a second reset time. During the second reset time interval, the first signal and the second signal are at a low potential. The reset circuit transmits the second voltage to the second node. The two transistors are turned on to pass the voltage of the second node to the third node, and the first transistor is turned on to pass the voltage of the third node to the first node. 如請求項12所述之畫素電路，其中該畫素電路操作一寫入時間，於該寫入時間區間時該第二訊號及該第三訊號為低電位，該資料寫入電路傳遞該資料電壓到該第一節點，該驅動電晶體導通以該資料電壓對該第二節點與該第三節點充電。 The pixel circuit as described in claim 12, wherein the pixel circuit operates for a writing time, and the second signal and the third signal are at a low potential during the writing time interval, and the data writing circuit transmits the data When the voltage reaches the first node, the driving transistor is turned on to charge the second node and the third node with the data voltage. 如請求項13所述之畫素電路，其中該畫素電路操作於一發光時間，於該發光時間區間時該控制訊號為低電位，該第一開關電路傳遞該第一電壓到該第一節點，該第二開關電路連接該驅動電晶體及該發光電路，該驅動電晶體產生一驅動電流流經該發光電路，該發光電路響應於該驅動電流而產生相對應的一亮度。 The pixel circuit according to claim 13, wherein the pixel circuit operates at a light-emitting time, the control signal is at a low potential during the light-emitting time interval, and the first switch circuit transmits the first voltage to the first node The second switching circuit is connected to the driving transistor and the light-emitting circuit. The driving transistor generates a driving current to flow through the light-emitting circuit, and the light-emitting circuit generates a corresponding brightness in response to the driving current.
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