CN112736071A - High-power chip embedded packaging heat dissipation structure and preparation method thereof - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/54—Encapsulations having a particular shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/641—Heat extraction or cooling elements characterized by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/642—Heat extraction or cooling elements characterized by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0075—Processes relating to semiconductor body packages relating to heat extraction or cooling elements
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
A high power chip embedded package heat dissipation structure, comprising: the high-power chip embedded package comprises a high-power chip array and a substrate, wherein the high-power chip array comprises at least one high-power chip subunit, the substrate comprises at least one through hole, and the high-power chip array is embedded into the through hole and connected with the radiator through the substrate. The invention solves the technical problems of poor heat dissipation, short service life and low efficiency of the existing chip, shortens the heat dissipation path, improves the heat dissipation performance of the high-power chip and breaks through the limitation of the traditional heat dissipation.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a high-power chip heat dissipation technology.
Background
The light emitting diode with the obvious advantages of high lumen efficiency, long service life, low driving voltage and the like is widely applied to the fields of display, illumination, decoration and the like. With the requirement of application scenes, higher requirements are put forward on the heat dissipation design of a high-power chip with high power and high brightness. The prior high-power chip radiating structure has the technical problems of premature decay of a light source, shortened service life and reduced luminous efficiency caused by poor radiating performance.
Disclosure of Invention
In order to overcome the defects of the prior art and solve the technical problems of premature decay of a light source, shortened service life and reduced luminous efficiency caused by poor heat dissipation of the original high-power chip structure, the invention discloses a high-power chip embedded packaging heat dissipation structure, which comprises:
a high power chip package, a heat sink,
the high power chip package includes a high power chip array, a substrate,
the high-power chip array comprises at least one high-power chip subunit, the substrate comprises at least one through hole,
the high-power chip array is embedded into the through hole and connected with the radiator through the substrate.
Preferably, the substrate includes a via region, and an edge region outside the via region, the edge region including at least one pad.
Preferably, the length and the width of the through hole region are respectively greater than the length and the width of the high-power chip array.
Preferably, the high-power chip is a light emitting diode chip, the high-power chip array comprises m × n high-power chip subunits, m is greater than or equal to 1, n is greater than or equal to 1, each row/column of high-power chip subunits are connected in series or in parallel or in series and parallel in a lead bonding mode, and the bonded leads are bonded to the bonding pad.
The preferred high-power chip array comprises a triangle, a square, a rectangle, a pentagon, a hexagon, a circle and other arbitrary self-defined shapes; the shape of the through hole of the substrate comprises a triangle, a square, a rectangle, a pentagon, a hexagon, a circle and other arbitrary self-defined shapes.
The preferred substrates include organic substrates, ceramic substrates, glass substrates, metal core printed circuit boards and other composite substrates; the radiator comprises a silicon-based/metal-based/ceramic-based liquid cooling plate, a heat diffusion plate and a heat sink; the radiator material comprises copper, tungsten copper, molybdenum copper, aluminum, silicon and other composite materials.
A method for preparing a high-power chip embedded package heat dissipation structure comprises
S1: preparing a substrate including at least one through hole;
s2: bonding a high power chip array structure to the substrate;
s3: plastic packaging; heating to separate the high-power module from the carrier plate;
s4: sputtering a metallization layer on the bottom surface of the radiator;
s5: the high power chip package is soldered directly to the heat sink.
Preferably, the S1 includes:
s1.1: processing a through hole of the substrate by a laser grooving or mechanical grooving process;
s1.2: temporarily bonding the substrate to a carrier plate by using a heat release adhesive tape, wherein the carrier plate is made of stainless steel, glass and other composite materials; the substrate comprises a substrate through hole region and an edge region located outside the substrate through hole region, wherein the edge region comprises at least one bonding pad.
Preferably, the high power chip is a light emitting diode chip, and the S2 includes:
s2.1: each row/column of high-power chip subunits are connected in series or in parallel or in series and parallel in a wire bonding mode;
s2.2: wire bonding a peripheral chip to a pad on the substrate; the pad is located at the outer edge of the through hole.
Preferably, the S3 includes:
s3.1: the high-power module is plastically packaged by materials such as silica gel and epoxy resin;
s3.2: and heating the carrier plate to the temperature required by the heat release of the adhesive tape so as to separate the substrate from the carrier plate.
Preferably, the S4 includes: performing plate-level physical vapor deposition on the substrate, and sputtering at least one first metallization layer on the substrate, wherein the first metallization layer comprises Ti/Cu, Ni/Au and Ag; and sputtering one or more second metallization layers on the bottom surface of the heat radiator, wherein the metallization layers comprise Ni/Au, Ag, Ti/Cu and Cu/Sn.
According to the invention, the high-power chip array embedded into the through hole of the substrate is directly bonded to the radiator, so that the radiating path is shortened, the radiating performance of the high-power chip is improved, and the limitation of the traditional radiating is broken through.
Drawings
Fig. 1 is a side view of an embodiment of a heat dissipation structure for an embedded package of a high power led chip.
Fig. 2 is a top view of an embodiment of an embedded heat dissipation structure of a high power led chip.
Fig. 3 is a side view of the substrate of the method for manufacturing the heat dissipation structure of the embedded package of high power led chip according to the second embodiment.
Fig. 4 is a side view of the substrate and the temporary carrier plate of the method for manufacturing the heat dissipation structure of the embedded package of the high power led chip according to the second embodiment.
Fig. 5 is a side view of a high-power chip of a bonding substrate in the method for manufacturing an embedded heat dissipation structure of a high-power led chip according to the second embodiment.
Fig. 6 is a side view of a high-power chip bonded to a high-power chip array according to the method for manufacturing the heat dissipation structure for an embedded package of a high-power led chip provided in the second embodiment.
Fig. 7 is a side view of the plastic packaged high-power chip according to the method for manufacturing the heat dissipation structure for embedded package of high-power led chip provided in the second embodiment.
Fig. 8 is a side view of the high-power chip without the carrier plate according to the method for manufacturing the heat dissipation structure of the embedded package of the high-power light emitting diode chip provided in the second embodiment.
Fig. 9 is a side view of a high-power chip with metallization layers according to the method for manufacturing the heat dissipation structure of the embedded package of high-power led chip in the second embodiment.
Fig. 10 is a side view of a high power chip of an assembled heat sink of the method for manufacturing an embedded heat dissipation structure of a high power led chip according to the second embodiment
001 is a substrate, 001a is a substrate through hole edge region, 001b is a substrate through hole, 001c is a substrate lead, 001d is a substrate bonding pad, 001e is a high-power chip packaging anode, and 001f is a high-power chip packaging cathode; 002 is heat release tape; 003 is a stainless steel carrier plate; 004 for high power chip sub-unit, 004a for high power chip bonding pad; 005 is a lead wire; 006 is high transparent silica gel; 007 a back metallization layer of the high-power chip module; 008 is the liquid cooling board, 008a is the liquid cooling board fin, 008b is the liquid cooling board fluid passage, 008c is the liquid cooling board back metallization layer.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, the following examples of which are intended to be illustrative only and are not to be construed as limiting the scope of the invention.
Example one
The present embodiment provides a heat dissipation structure for embedded package of high power light emitting diode chip, as shown in fig. 1-2, including: high power chip package, the radiator, high power chip package includes high power chip array, high power chip package positive pole 001e, high power chip package negative pole 001f, base plate 001, high power chip array includes at least one high power chip subunit 004, the base plate includes a through-hole 001b, high power chip array embedding in the through-hole, be connected with the radiator through the base plate. The substrate comprises a substrate through hole region and an edge region 001a positioned outside the substrate through hole region, wherein the edge region comprises at least one heating pad 001d and at least one substrate lead 001 c; the high power chip array includes a plurality of high power chip sub-units 004 arranged in rows or columns. The heat sink shown includes 005 as leads; 006 is silica gel or epoxy resin; 007 the high power chip package back side metallization layer.
In another preferred embodiment, the through hole may be provided in plural, and the high power chip array is directly soldered to the heat sink through the plural through holes.
The high-power chip package and the radiator are connected in a welding mode.
The high-power chip array is embedded into the through hole of the substrate, the high-power sub-chip unit array comprises a triangle, a square, a rectangle, a pentagon, a hexagon, a circle and other arbitrary self-defined shapes, and each row or column of chips are connected in series by a lead bonding mode and then bonded to a bonding pad on the outer edge of the through hole of the substrate by the lead bonding mode; the substrate through holes comprise triangles, squares, rectangles, pentagons, hexagons, circles and other arbitrary self-defined shapes; the high-power chip and the upper surface of the lead are protected by materials such as silica gel and epoxy resin.
The heat radiator comprises a silicon-based/metal-based/ceramic-based liquid cooling plate, a heat diffusion plate and a heat sink.
The substrate comprises an organic substrate, a ceramic substrate, a glass substrate, a metal core printed circuit board and other composite substrates; the radiator material comprises copper, tungsten copper, molybdenum copper, aluminum, silicon and other composite materials.
When the high-power chip is a multi-pin chip such as a power device or a radio frequency device, a single chip can be used as the high-power module and is directly connected with the heat dissipation module through the through hole.
Example two
The embodiment provides a method for preparing an embedded package heat dissipation structure of a high-power light emitting diode chip, as shown in fig. 3-10, the steps are as follows:
1) processing the through hole of the substrate by a laser grooving or mechanical grooving process to obtain the substrate with the through hole, as shown in fig. 3;
2) temporarily bonding the substrate with the through hole to a stainless steel carrier plate by using a heat release adhesive tape;
3) temporarily bonding the high-power chip or the high-power chip array to the carrier plate, as shown in fig. 4;
4) the electrical connection between the chips is realized by means of wire bonding, and the chips are finally bonded to the bonding pads at the outer edges of the through holes of the substrate, for example, the back surfaces of the high-power chips or the high-power chip arrays are temporarily bonded to the carrier plate in the figure 5, and the chips are electrically interconnected and bonded to the bonding pads of the substrate through the wire bonding as shown in the figure 6;
5) plastically packaging the high-power chip by using the processes of silica gel, epoxy resin and the like, as shown in fig. 7;
6) when the temperature is heated to the temperature required by the heat release of the adhesive tape, the back surface of the chip and the substrate can be automatically separated from the carrier plate, as shown in fig. 8;
7) performing plate-level physical vapor deposition according to subsequent welding requirements, and sputtering one or more metallization layers, wherein the metallization layers comprise Ti/Cu, Ni/Au and Ag; depositing metallization layers required for soldering by means of physical vapor deposition as shown in fig. 9;
8) the sputtering metallization layer on the bottom surface of the radiator comprises Ni/Au, Ag, Ti/Cu and Cu/Sn;
9) the high power chip array package is assembled on the heat sink by soldering, sintering and other processes, and the high power chip including the directly attached heat sink structure as shown in fig. 10 is obtained.
When the high-power chip is a multi-pin chip such as a power device or a radio frequency device, a single chip can be used as a high-power module and temporarily bonded to the carrier plate to realize contact with the radiator.
According to the invention, the high-power chip array embedded into the through hole of the substrate is directly bonded to the radiator, so that the technical problems of poor heat dissipation, short service life and low efficiency are solved, the heat dissipation path is shortened, the heat dissipation performance of the high-power chip is improved, and the limitation of the traditional heat dissipation is broken through.
Although exemplary embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions, substitutions and the like can be made in form and detail without departing from the scope and spirit of the invention as disclosed in the accompanying claims, all of which are intended to fall within the scope of the claims, and that various steps in the various sections and methods of the claimed product can be combined together in any combination. Therefore, the description of the embodiments disclosed in the present invention is not intended to limit the scope of the present invention, but to describe the present invention. Accordingly, the scope of the present invention is not limited by the above embodiments, but is defined by the claims or their equivalents.
Claims (11)
1. A high power chip embedded package heat dissipation structure, comprising:
high power chip embedded packages, heat sinks,
the high-power chip embedded package comprises a high-power chip array and a substrate,
the high-power chip array comprises at least one high-power chip subunit, the substrate comprises at least one through hole,
and embedding the high-power chip array into the through hole of the substrate, and connecting the high-power chip array with a radiator through the substrate.
2. The high power chip embedded package heat dissipation structure of claim 1, wherein the substrate comprises a via region, and an edge region outside the via region, the edge region comprising at least one pad.
3. The high power chip embedded package heat dissipation structure of claim 2, wherein the length and width of the via region are greater than the length and width of the high power chip array, respectively.
4. The embedded package heat dissipation structure of claim 1, wherein the high power chip is a light emitting diode chip, the high power chip array comprises m × n high power chip subunits, m is greater than or equal to 1, n is greater than or equal to 1, each row/column of high power chip subunits are connected in series or in parallel or in series and parallel by wire bonding, and the high power chip array is wire bonded to the pad at the edge of the through hole of the substrate.
5. The high power chip embedded package heat dissipation structure of claim 4, wherein the high power chip array comprises a triangle, a square, a rectangle, a pentagon, a hexagon, a circle, and any other custom shape; the substrate through holes comprise triangles, squares, rectangles, pentagons, hexagons, circles and other arbitrary self-defined shapes.
6. The high power chip embedded package heat dissipation structure of claim 1, wherein the substrate comprises an organic substrate, a ceramic substrate, a glass substrate, a metal core printed circuit board, and other composite substrates; the radiator comprises a silicon-based/metal-based/ceramic-based liquid cooling plate, a heat diffusion plate and a heat sink; the radiator material comprises copper, tungsten copper, molybdenum copper, aluminum, silicon and other composite materials.
7. A preparation method of a high-power chip embedded package heat dissipation structure is characterized by comprising the following steps:
s1: preparing a substrate including at least one through hole;
s2: temporarily bonding the high-power chip array to the carrier plate, and realizing electrical connection among the chips, the peripheral chips and the substrate bonding pads in a lead bonding mode; (ii) a
S3: plastic packaging; heating to separate the high-power module from the carrier plate;
s4: preparing a radiator, and sputtering a metallization layer which can be welded with the high-power chip on the bottom surface of the radiator; (ii) a
S5: and directly welding the high-power chip embedded packaging module to the radiator.
8. The method for preparing the heat dissipation structure of the embedded package of high power chip as claimed in claim 5,
the S1 includes:
s1.1: processing a through hole of the substrate by a laser grooving or mechanical grooving process;
s1.2: temporarily bonding the substrate to a carrier plate by using a heat release adhesive tape, wherein the carrier plate is made of stainless steel, glass and other composite materials; the substrate comprises a substrate through hole region and an edge region located outside the substrate through hole region, wherein the edge region comprises at least one bonding pad.
9. The method for preparing the heat dissipation structure of embedded package of high power chip as claimed in claim 1, wherein the high power chip is a light emitting diode chip, and the step S2 includes:
s2.1: each row/column of high-power chip subunits are connected in series or in parallel or in series and parallel in a wire bonding mode;
s2.2: bonding the bonded wire to a pad on the substrate; the pad is located at the outer edge of the through hole.
10. The method for preparing the heat dissipation structure of the embedded package of high power chip as claimed in claim 1, wherein the step S3 includes:
s3.1: packaging the high-power chip by plastic package of materials such as silica gel, epoxy resin and the like;
s3.2: and heating the carrier plate to the temperature required by the heat release of the adhesive tape so as to separate the substrate from the carrier plate.
11. The method for preparing the heat dissipation structure of the embedded package of high power chip as claimed in claim 1, wherein the step S4 includes: performing plate-level physical vapor deposition on the substrate, and sputtering at least one first metallization layer on the substrate, wherein the first metallization layer comprises Ti/Cu, Ni/Au and Ag; and sputtering one or more second metallization layers on the bottom surface of the heat radiator, wherein the metallization layers comprise Ni/Au, Ag, Ti/Cu and Cu/Sn.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116127903A (en) * | 2023-02-14 | 2023-05-16 | 电子科技大学 | High-power PA chip layout and wind tunnel type self-heat-dissipation packaging design method |
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