CN113485671B - Click controller and asynchronous micro-pipeline data flow controller - Google Patents
Click controller and asynchronous micro-pipeline data flow controller Download PDFInfo
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Abstract
The invention relates to a click controller and an asynchronous micro-pipeline data flow controller. The click controller includes: the inverter, the exclusive-or gate and the trigger with the first output end connected back to the first input end; the input end of the exclusive OR gate inputs a Fill signal of the previous stage click controller and a drain signal of the next stage click controller; the exclusive-or gate is used for generating four local clock signals from the Fill signal and the drain signal; the output end of the exclusive-OR gate is connected with the second input end of the trigger; the second output end of the trigger is connected with the input end of the reverser; the trigger is also used for outputting a full signal of the click controller at the next stage; the reverser is used for reversing the full signal and outputting an empty signal of the previous-stage click controller; the empty signal is a response signal of the previous click controller. The invention has the characteristics of simple circuit structure and high compatibility.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a click controller and an asynchronous micro-pipeline data flow controller.
Background
Currently, a click controller is a two-term signal controller, the pipeline circuit structure of the branch and merge structure and the FIFO structure is complex, and the handshake signals of the pipeline cannot be compatible with other asynchronous pipeline controllers such as Mousetrap or MullerC units.
Therefore, there is a need for a click controller with a simple circuit structure and with improved compatibility.
Disclosure of Invention
The invention aims to provide a click controller and an asynchronous micro-pipeline data flow controller, which have the characteristics of simple circuit structure and high compatibility.
In order to achieve the above object, the present invention provides the following solutions:
a click controller comprising: the inverter, the exclusive-or gate and the trigger with the first output end connected back to the first input end;
the input end of the exclusive OR gate inputs a Fill signal of the previous stage click controller and a drain signal of the next stage click controller; the exclusive-or gate is used for generating four local clock signals from the Fill signal and the drain signal;
the output end of the exclusive-OR gate is connected with the second input end of the trigger;
the second output end of the trigger is connected with the input end of the reverser; the trigger is also used for outputting a full signal of the click controller at the next stage; the full signal is a request signal of the click controller;
the reverser is used for reversing the full signal and outputting an empty signal of the previous-stage click controller; the empty signal is a response signal of the previous click controller.
Optionally, the moment when the Fill signal reaches the inverter is earlier than the moment when the drain signal reaches the inverter.
An asynchronous micro-pipeline data flow controller, said asynchronous micro-pipeline data flow controller being coupled to said click controller; the asynchronous micro pipeline data flow controller comprises: and gate and buffer;
the input end of the buffer inputs a full signal of the previous stage click controller; the output end of the buffer is connected with the first input end of the AND gate, and the second input end of the AND gate inputs an empty signal of the next click controller; and the AND gate outputs a dry signal of the previous stage click controller and a fill signal of the next stage click controller.
An asynchronous micro-pipeline data flow controller, said asynchronous micro-pipeline data flow controller being coupled to said click controller; the asynchronous micro pipeline data flow controller comprises: the AND gate, the first buffer and the second buffer;
the input end of the first buffer inputs a full signal of a click controller at the upper stage in the first branch; the output end of the first buffer is connected with the first input end of the AND gate; the input end of the second buffer inputs a full signal of the click controller at the upper stage of the second branch; the output end of the second buffer is connected with the second input end of the AND gate; the third input end of the AND gate inputs an empty signal of the next click controller; the output end of the AND gate outputs a dry signal of the previous stage click controller in the first branch, a dry signal of the previous stage click controller in the second branch and a fill signal of the next stage click controller.
An asynchronous micro-pipeline data flow controller, said asynchronous micro-pipeline data flow controller being coupled to said click controller; the asynchronous micro pipeline data flow controller comprises: and gate and buffer;
the input end of the buffer inputs a full signal of the previous stage click controller; the output end of the buffer is connected with the first input end of the AND gate; the second input end of the AND gate inputs an empty signal of a click controller of the next stage in the first branch; the third input end of the AND gate inputs an empty signal of a click controller of the next stage in the second branch; the AND gate outputs a dry signal of the previous stage click controller, a fill signal of the next stage click controller in the first branch, and a fill signal of the next stage click controller in the second branch.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides a click controller and an asynchronous micro-pipeline data flow controller, which are used as controllers of each stage of a pipeline, and comprise two input signals Fill, dry and two output signals full and empty. The request and response signals Fill and drain from the previous and next stage pipelines generate four local clock signals through exclusive or gates, the trigger signals realized by a set of rising edges and reset signals control the output Q of the trigger to turn over, the output Q of the trigger is used as the request signal full of the next stage, and the inverted empty is used as the response signal of the previous stage pipeline. The delay control device has the advantages of simple structure and higher speed, and each stage of delay of the controlled pipeline is adjustable.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a click controller according to the present invention;
FIG. 2 is a schematic diagram of a FIFO structure of an asynchronous micro-pipeline data flow controller;
FIG. 3 is a schematic diagram of a merging architecture of an asynchronous micro-pipelined data-flow controller;
FIG. 4 is a schematic diagram of a branch structure of an asynchronous micro-pipelined data-flow controller.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide a click controller and an asynchronous micro-pipeline data flow controller, which have the characteristics of simple circuit structure and high compatibility.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
FIG. 1 is a schematic diagram of a click controller according to the present invention, as shown in FIG. 1, the click controller according to the present invention includes: the inverter INV, the exclusive or gate XOR and the flip-flop FF with the first output terminal connected back to the first input terminal.
The input end of the exclusive OR gate inputs a Fill signal of the previous stage click controller and a drain signal of the next stage click controller; the exclusive or gate is used for generating four local clock signals from the Fill signal and the drain signal.
The output end of the exclusive-OR gate is connected with the second input end of the trigger; the output Q of the flip-flop is controlled to flip by a set of rising and falling edge implemented trigger signals and reset signals.
The second output end of the trigger is connected with the input end of the reverser; the trigger is also used for outputting a full signal of the click controller at the next stage; the full signal is a request signal of the click controller;
the reverser is used for reversing the full signal and outputting an empty signal of the previous-stage click controller; the empty signal is a response signal of the previous click controller.
To meet the timing constraints of an asynchronous micro-pipeline control circuit, the moment when the Fill signal reaches the inverter is earlier than the moment when the drain signal reaches the inverter.
The click controller provided by the invention is improved on the basis of the original click controller structure, and has a simple circuit structure and higher compatibility. The simple logic processing and delay of handshake signals among all stages of the asynchronous micro-pipeline are realized to meet the time sequence constraint of an asynchronous micro-pipeline control circuit, and the FIFO, the branch and the confluence of the pipeline can be realized.
FIG. 2 is a schematic diagram of a FIFO structure of an asynchronous micro-pipelined data-flow controller, as shown in FIG. 2. The invention provides an asynchronous micro-pipeline data flow controller, which is connected with a click controller; the asynchronous micro pipeline data flow controller comprises: and gate and buffer;
the input end of the buffer inputs a full signal of the previous stage click controller; the output end of the buffer is connected with the first input end of the AND gate, and the second input end of the AND gate inputs an empty signal of the next click controller; and the AND gate outputs a dry signal of the previous stage click controller and a fill signal of the next stage click controller.
FIG. 3 is a schematic diagram of a merging architecture of an asynchronous micro-pipeline data flow controller, as shown in FIG. 3, connected to the click controller; the asynchronous micro pipeline data flow controller comprises: and gate, first buffer and second buffer,
the input end of the first buffer inputs a full1 signal of a click controller at the upper stage in the first branch; the output end of the first buffer is connected with the first input end (shown as 1 in fig. 3) of the and gate; the input end of the second buffer inputs a full2 signal of the click controller at the upper stage in the second branch; the output of the second buffer is connected to a second input of the and gate (shown as 2 in fig. 3); a third input end (shown as 0 in fig. 3) of the and gate inputs an empty signal of the click controller of the next stage; the output end of the AND gate outputs a dry 1 signal of the previous stage click controller in the first branch, a dry 2 signal of the previous stage click controller in the second branch and a fill signal of the next stage click controller.
FIG. 4 is a schematic diagram of a branching structure of an asynchronous micro-pipeline data flow controller, as shown in FIG. 4, connected to the click controller; the asynchronous micro pipeline data flow controller comprises: and gate and buffer;
the input end of the buffer inputs a full signal of the previous stage click controller; the output of the buffer is connected to a first input of the and gate (shown as 0 in fig. 4); the second input end of the AND gate (shown as 1 in FIG. 4) inputs the empty1 signal of the click controller of the next stage in the first branch; the third input end of the AND gate (shown as 2 in FIG. 4) inputs the empty2 signal of the click controller of the next stage in the second branch; the AND gate outputs a dry signal of the previous stage click controller, a fill1 signal of the next stage click controller in the first branch, and a fill2 signal of the next stage click controller in the second branch.
For each stage of click controller (pipeline controller), there are two states of "empty (empty)" and "full (full)" according to the data path controlled, which are respectively represented by the high level of the signal outputs empty and full of the front and rear stages of pipeline controllers.
When implementing the FIFO structure of an asynchronous pipeline, the fill signal of each stage of the asynchronous pipeline Data Flow Controller (DFC) represents the sum of the data fill request full from the previous stage and the reply empty of the present stage, and the dry represents the sum of the reply empty of the data from the next stage and the present stage full signal. Asynchronous pipeline Data Flow Controllers (DFCs) handle the inter-transmission of pipeline signals of each stage through buffers connected to the and gate inputs, requiring for each stage of pipeline control signals that the time of the request signal be earlier than the time of the reply signal arrival, so that the and gate between the pipeline controllers is required to pass through a buffer from the reply signal of the previous stage to meet this timing constraint.
When the branch pipeline structure is realized, when the request output full1, full2 of the previous stage and the response output empty of the next stage are at high level at the same time, after passing through an AND gate of an asynchronous pipeline Data Flow Controller (DFC), the response input drain1 of the previous stage pipeline and the request input fill of the next stage pipeline are pulled high at the same time.
When the confluence pipeline structure is realized, when the request output full of the previous stage and the response outputs empty1 and empty2 of the next stage are at high level at the same time, after passing through an AND gate of an asynchronous pipeline Data Flow Controller (DFC), the response input drain of the previous stage pipeline and the request input fill1 of the next stage pipeline are pulled high at the same time.
That is, when a branching or joining pipeline structure is implemented, an asynchronous pipeline Data Flow Controller (DFC) pulls up a "drain" input signal drain of a preceding stage and a "fill" input signal fill of a subsequent stage when all controllers of the preceding stage are "full", i.e., full is high, and all controllers of the subsequent stage are "empty", i.e., empty is high.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.
Claims (3)
1. An asynchronous micro-pipeline data flow controller, wherein the asynchronous micro-pipeline data flow controller is connected with a click controller; the asynchronous micro pipeline data flow controller comprises: and gate and buffer;
the click controller includes: the inverter, the exclusive-or gate and the trigger with the first output end connected back to the first input end; the input end of the exclusive OR gate inputs a Fill signal of the previous stage click controller and a drain signal of the next stage click controller; the exclusive-or gate is used for generating four local clock signals from the Fill signal and the drain signal; the output end of the exclusive-OR gate is connected with the second input end of the trigger; the second output end of the trigger is connected with the input end of the reverser; the trigger is also used for outputting a full signal of the click controller at the next stage; the full signal is a request signal of the click controller; the reverser is used for reversing the full signal and outputting an empty signal of the previous-stage click controller; the empty signal is a response signal of the previous click controller;
the input end of the buffer inputs a full signal of the previous stage click controller; the output end of the buffer is connected with the first input end of the AND gate, and the second input end of the AND gate inputs an empty signal of the next click controller; and the AND gate outputs a dry signal of the previous stage click controller and a fill signal of the next stage click controller.
2. An asynchronous micro-pipeline data flow controller, wherein the asynchronous micro-pipeline data flow controller is connected with a click controller; the asynchronous micro pipeline data flow controller comprises: the AND gate, the first buffer and the second buffer;
the click controller includes: the inverter, the exclusive-or gate and the trigger with the first output end connected back to the first input end; the input end of the exclusive OR gate inputs a Fill signal of the previous stage click controller and a drain signal of the next stage click controller; the exclusive-or gate is used for generating four local clock signals from the Fill signal and the drain signal; the output end of the exclusive-OR gate is connected with the second input end of the trigger; the second output end of the trigger is connected with the input end of the reverser; the trigger is also used for outputting a full signal of the click controller at the next stage; the full signal is a request signal of the click controller; the reverser is used for reversing the full signal and outputting an empty signal of the previous-stage click controller; the empty signal is a response signal of the previous click controller;
the input end of the first buffer inputs a full signal of a click controller at the upper stage in the first branch; the output end of the first buffer is connected with the first input end of the AND gate; the input end of the second buffer inputs a full signal of the click controller at the upper stage of the second branch; the output end of the second buffer is connected with the second input end of the AND gate; the third input end of the AND gate inputs an empty signal of the next click controller; the output end of the AND gate outputs a dry signal of the previous stage click controller in the first branch, a dry signal of the previous stage click controller in the second branch and a fill signal of the next stage click controller.
3. An asynchronous micro-pipeline data flow controller, wherein the asynchronous micro-pipeline data flow controller is connected with a click controller; the asynchronous micro pipeline data flow controller comprises: and gate and buffer;
the click controller includes: the inverter, the exclusive-or gate and the trigger with the first output end connected back to the first input end; the input end of the exclusive OR gate inputs a Fill signal of the previous stage click controller and a drain signal of the next stage click controller; the exclusive-or gate is used for generating four local clock signals from the Fill signal and the drain signal; the output end of the exclusive-OR gate is connected with the second input end of the trigger; the second output end of the trigger is connected with the input end of the reverser; the trigger is also used for outputting a full signal of the click controller at the next stage; the full signal is a request signal of the click controller; the reverser is used for reversing the full signal and outputting an empty signal of the previous-stage click controller; the empty signal is a response signal of the previous click controller;
the input end of the buffer inputs a full signal of the previous stage click controller; the output end of the buffer is connected with the first input end of the AND gate; the second input end of the AND gate inputs an empty signal of a click controller of the next stage in the first branch; the third input end of the AND gate inputs an empty signal of a click controller of the next stage in the second branch; the AND gate outputs a dry signal of the previous stage click controller, a fill signal of the next stage click controller in the first branch, and a fill signal of the next stage click controller in the second branch.
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