CN112600559A - Pipeline analog-to-digital converter and transceiving chip - Google Patents

Pipeline analog-to-digital converter and transceiving chip Download PDF

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CN112600559A
CN112600559A CN202011394280.0A CN202011394280A CN112600559A CN 112600559 A CN112600559 A CN 112600559A CN 202011394280 A CN202011394280 A CN 202011394280A CN 112600559 A CN112600559 A CN 112600559A
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reference level
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CN112600559B (en
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宋阳
吴建东
刘建新
赵鹏
李林旭
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Shenzhen State Micro Electronics Co Ltd
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    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
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Abstract

An initial quantization circuit amplifies an input signal by 1 time to output an initial output signal, and quantizes the input signal according to an initial reference level to output an initial quantized signal; the 1 st intermediate quantization circuit and the (i + 1) th intermediate quantization circuit quantize the output signal of the previous stage according to the quantized signal of the previous stage to output a 1 st intermediate quantized signal or an (i + 1) th intermediate quantized signal, and operate the output signal of the previous stage according to the quantized signal of the previous stage to output a 1 st output signal or an (i + 1) th output signal; i is a natural number less than n; an end quantization circuit generates an end reference level from the nth intermediate quantized signal, quantizes the nth output signal according to the end reference level to output an end quantized signal; the delay alignment circuit performs delay alignment and staggered addition on the initial quantized signal, the n middle quantized signals and the tail end quantized signal and outputs a total quantized signal; the comparison accuracy is improved.

Description

Pipeline analog-to-digital converter and transceiving chip
Technical Field
The application belongs to the field of integrated circuits, and particularly relates to a pipeline analog-to-digital converter and a transceiver chip.
Background
The transceiver performance in a SERializer/DESerializer (Serdes) system depends largely on the performance of the analog-to-digital converter, mainly related to the conversion rate, resolution and power consumption of the analog-to-digital converter. In the application of a receiving and transmitting system of intermediate frequency sampling, the performance requirements of high speed and high precision are limited, a pipeline structure is a circuit structure which is most suitable for transmitting data in all the existing analog-to-digital converter structures, and how to design an analog-to-digital converter with low power consumption under the requirements of high speed and high precision is also a current research hotspot.
In the conventional pipeline analog-to-digital converter structure, as shown in fig. 1, an input is sampled by a sample and hold circuit S/H and then transferred to a sub-quantization circuit MDACi of a subsequent stage, wherein in the sub-quantization circuit MDACi of each stage, the reference voltages of the comparators in the sub-analog-to-digital converter are +1/4VREF and-1/4 VREF. The wider reference voltage brings offset error of the comparator, thereby causing poor precision of the pipeline analog-to-digital converter.
Disclosure of Invention
The application aims to provide a pipeline analog-to-digital converter and a transceiver chip, and aims to solve the problem that the traditional pipeline analog-to-digital converter is poor in precision.
The embodiment of the application provides a pipeline analog-to-digital converter, which comprises an initial quantization circuit, n middle quantization circuits, a tail end quantization circuit and a delay alignment circuit;
the initial quantization circuit, the n intermediate quantization circuits and the tail end quantization circuit are connected in a step-by-step mode; wherein n is a natural number;
the initial quantization circuit is configured to amplify an input signal by a 1-fold ratio to output an initial output signal and quantize the input signal according to an initial reference level to output an initial quantized signal when the input signal is received;
the 1 st one of the intermediate quantization circuits is configured to quantize the initial output signal according to the initial quantization signal to output a 1 st intermediate quantization signal, and operate on the initial output signal according to the initial quantization signal to output a 1 st output signal;
the i +1 th intermediate quantization circuit is configured to quantize an i-th output signal according to an i-th intermediate quantization signal to output an i + 1-th intermediate quantization signal, and operate on the i-th output signal according to the i-th quantization signal to output an i + 1-th output signal; wherein i is a natural number less than n; the maximum value of i +1 is n;
the end quantization circuit is configured to generate an end reference level from the nth intermediate quantized signal and quantize the nth output signal according to the end reference level to output an end quantized signal;
the delay alignment circuit is connected with the initial quantization circuit, the n intermediate quantization circuits and the tail end quantization circuit; is configured to delay align and stagger add the initial quantized signal, the n intermediate quantized signals and the end quantized signal and output a summed quantized signal.
The embodiment of the invention also provides a transceiver chip, which comprises the pipeline analog-to-digital converter.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: because the intermediate quantization circuit and the tail end quantization circuit set reference levels according to the quantization circuit of the previous stage, the range of reference voltage is reduced, the offset error is reduced, and the comparison precision is improved.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts.
FIG. 1 is a schematic diagram of a conventional pipelined analog-to-digital converter;
fig. 2 is a schematic structural diagram of a pipeline analog-to-digital converter according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of an initial quantization circuit in a pipeline analog-to-digital converter according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a 1 st intermediate quantization circuit in a pipeline analog-to-digital converter according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an i +1 th intermediate quantization circuit in a pipeline analog-to-digital converter according to an embodiment of the present application;
fig. 6 is a schematic diagram of an end quantization circuit in a pipeline adc according to an embodiment of the present application;
FIG. 7 is a schematic diagram of an exemplary circuit for a comparison module in a pipelined analog-to-digital converter according to an embodiment of the present application;
FIG. 8 is an exemplary circuit schematic of an initial comparison circuit in a pipelined analog-to-digital converter provided by an embodiment of the present application;
FIG. 9 is an exemplary circuit schematic of an end compare circuit in a pipelined analog-to-digital converter provided by an embodiment of the present application;
FIG. 10 is a schematic diagram illustrating an operation of an intermediate quantization circuit in a pipelined analog-to-digital converter according to an embodiment of the present application;
fig. 11 is a schematic diagram illustrating an operation of an end quantization circuit in a pipeline adc according to an embodiment of the present application;
FIG. 12 is a schematic diagram of an exemplary circuit for an amplifying circuit in a pipeline ADC according to an embodiment of the present application;
FIG. 13 is a schematic diagram of an exemplary circuit for an arithmetic block in a pipelined analog-to-digital converter according to an embodiment of the present application;
FIG. 14 is a schematic diagram of an exemplary circuit for an initial comparison circuit and a comparison module in a pipelined analog-to-digital converter according to an embodiment of the present application;
FIG. 15 is an exemplary circuit schematic of an end compare circuit in a pipelined analog-to-digital converter provided by an embodiment of the present application;
FIG. 16 is a schematic diagram illustrating a calculation process of 536mV input signals provided by an embodiment of the present application;
fig. 17 is a schematic diagram of a calculation process of the delay alignment module when an input signal is 536mV according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Fig. 2 shows a schematic structural diagram of a pipeline analog-to-digital converter provided in the preferred embodiment of the present application, and for convenience of description, only the parts related to the present embodiment are shown, which are detailed as follows:
the pipeline analog-to-digital converter comprises an initial quantization circuit 11, n middle quantization circuits 12, an end quantization circuit 13 and a delay alignment circuit 14; the initial quantization circuit 11, the n intermediate quantization circuits 12 and the end quantization circuit 13 are connected in a stepwise manner; wherein n is a natural number.
The initial quantization circuit 11 is configured to, when receiving an input signal, amplify the input signal by a 1-fold ratio to output an initial output signal, and quantize the input signal according to an initial reference level to output an initial quantized signal.
The 1 st intermediate quantization circuit 121 is configured to quantize the initial output signal according to the initial quantization signal to output a 1 st intermediate quantized signal, and operate the initial output signal according to the initial quantization signal to output a 1 st output signal.
The i +1 th intermediate quantization circuit 12i +1 is configured to quantize the i-th output signal according to the i-th intermediate quantization signal to output an i +1 th intermediate quantization signal, and operate on the i-th output signal according to the i-th quantization signal to output an i +1 th output signal; wherein i is a natural number less than n; the maximum value of i +1 is n; .
The end quantization circuit 13 is configured to generate an end reference level from the nth intermediate quantized signal and quantize the nth output signal according to the end reference level to output an end quantized signal.
And a delay alignment circuit 14 connected to the initial quantization circuit 11, the n intermediate quantization circuits 12, and the end quantization circuit 13, and configured to perform delay alignment and offset addition on the initial quantization signal, the n intermediate quantization signals, and the end quantization signal and output a total quantization signal.
As shown in fig. 3, the initial quantization circuit 11 includes an amplification circuit 111 and an initial comparison circuit 112.
An amplification circuit 111 configured to amplify an input signal by a 1-fold ratio to output an initial output signal when receiving the input signal;
an initial comparison circuit 112 configured to quantize the input signal according to an initial reference level to output an initial quantized signal.
Wherein the initial reference level comprises an upper initial reference level anda lower initial reference level and an upper initial reference level of
Figure BDA0002814074800000041
The lower initial reference level is
Figure BDA0002814074800000042
The initial comparing circuit 112 quantizes the input signal according to the initial reference level to output an initial quantized signal specifically:
acquiring an initial quantized signal according to the following formula and outputting the signal:
Figure BDA0002814074800000043
wherein d is0For initially quantizing the signal, VinFor input signal, VRIs the reference voltage.
The functions of 1-fold proportional amplification and quantization of the most significant bit of the input signal are realized by the amplification circuit 111 and the initial comparison circuit 112, respectively.
As shown in fig. 4, the 1 st intermediate quantization circuit 121 includes a 1 st reference level selection circuit 1211, a 1 st comparison circuit 1212, a 1 st mode control circuit 1213, and a 1 st operation circuit 1214.
The 1 st reference level selection circuit 1211, connected to the initial quantization circuit 11, is configured to generate a 1 st intermediate reference level according to the initial quantization signal.
A 1 st comparing circuit 1212, connected to the 1 st reference level selecting circuit 1211 and the initial quantizing circuit 11, is configured to quantize the initial output signal according to the 1 st intermediate reference level to output a 1 st intermediate quantized signal.
There are three cases of the initial quantized signal, and in one-to-one correspondence with the three cases, the 1 st comparing circuit 1212 also has three cases, which are as follows:
in the first case, when the initially quantized signal is 00, the 1 st upper limit intermediate reference level is-3/8VRThe 1 st lower limit intermediate reference level is-5/8VROf 1 atThe 1 st comparing circuit 1212 quantizes the initial output signal according to the 1 st intermediate reference level to output a 1 st intermediate quantized signal specifically includes:
acquiring and outputting a 1 st intermediate quantized signal according to the following formula:
Figure BDA0002814074800000051
in the second case, when the initially quantized signal is 01, the 1 st upper limit intermediate reference level is 1/8VRThe 1 st lower limit intermediate reference level is-1/8VRThe 1 st comparing circuit 1212 quantizes the initial output signal according to the 1 st intermediate reference level to output the 1 st intermediate quantized signal specifically includes:
acquiring and outputting a 1 st intermediate quantized signal according to the following formula:
Figure BDA0002814074800000052
in the third case, when the initial quantized signal is 10, the 1 st upper limit middle reference level is 3/8VRThe 1 st lower limit intermediate reference level is 5/8VRThe 1 st comparing circuit 1212 quantizes the initial output signal according to the 1 st intermediate reference level to output the 1 st intermediate quantized signal specifically includes:
acquiring and outputting a 1 st intermediate quantized signal according to the following formula:
Figure BDA0002814074800000053
wherein, Vr，0Is an initial output signal; d1For the 1 st intermediate quantized signal, VRIs the reference voltage.
The 1 st mode control circuit 1213 is connected to the initial quantization circuit 11 and configured to generate a 1 st control signal according to the initial quantization signal.
The 1 st operation circuit 1214, connected to the initial quantization circuit 11 and the 1 st mode control circuit 1213, is configured to operate on the initial output signal according to the 1 st control signal to output a 1 st output signal.
The 1 st operation circuit 1214 performs an operation to output a 1 st output signal according to the 1 st control signal, specifically:
acquiring and outputting a 1 st output signal according to the following formula:
Vr,1＝2Vin-(d0-1)VR
wherein, Vr,1To output signal No. 1, VinTo the initial output signal, d0For initially quantizing the signal, VRIs the reference voltage.
Through the structure of the 1 st intermediate quantization circuit 121, the 1 st intermediate reference level is generated according to the initial quantization signal, and quantization is performed according to the 1 st intermediate reference level, so that the range of the reference voltage is reduced, the offset error is reduced, and the comparison precision is improved.
As shown in fig. 5, the i +1 th intermediate quantization circuit 12i +1 includes an i +1 th reference level selection circuit 12x1, an i +1 th comparison circuit 12x2, an i +1 th mode control circuit 12x3, and an i +1 th arithmetic circuit 12x 4.
An i +1 th reference level selection circuit 12x1 connected to the i-th comparison circuit and configured to generate an i +1 th intermediate reference level from the i-th intermediate quantized signal;
an i +1 th comparing circuit 12x2 connected to the i +1 th reference level selecting circuit 12x1 and the i-th arithmetic circuit, configured to quantize the i-th output signal according to the i +1 th intermediate reference level to output an i +1 th intermediate quantized signal;
there are three cases of the ith quantized signal, and in one-to-one correspondence with the three cases, there are also three cases of the i +1 th comparing circuit 12x2, which are as follows:
in the first case, when the ith quantized signal is 00, the i +1 th upper limit middle reference level is-3/8VRThe i +1 th lower limit intermediate reference level is-5/8VRThe i +1 th comparing circuit 12x2 quantizes the i-th output signal according to the i +1 th intermediate reference level to output the i +1 th intermediate quantized signal specifically includes:
acquiring and outputting an i +1 intermediate quantized signal according to the following formula:
Figure BDA0002814074800000061
in the second case, when the ith quantized signal is 01, the i +1 th upper limit middle reference level is 1/8VRThe i +1 th lower limit intermediate reference level is-1/8VRThe i +1 th comparing circuit 12x2 quantizes the i-th output signal according to the i +1 th intermediate reference level to output the i +1 th intermediate quantized signal specifically includes:
acquiring and outputting an i +1 intermediate quantized signal according to the following formula:
Figure BDA0002814074800000062
in the third case, when the ith quantized signal is 10, the i +1 th upper limit middle reference level is 3/8VRThe i +1 th lower limit intermediate reference level is 5/8VRThe i +1 th comparing circuit 12x2 quantizes the i-th output signal according to the i +1 th intermediate reference level to output the i +1 th intermediate quantized signal specifically includes:
acquiring and outputting an i +1 intermediate quantized signal according to the following formula:
Figure BDA0002814074800000071
wherein d isi+1For the i +1 th intermediate quantized signal, Vr,iFor the ith output signal, VRIs the reference voltage.
An i +1 th mode control circuit 12x3 connected to the i-th comparison circuit and configured to generate an i +1 th control signal according to the i-th quantized signal;
the i +1 th arithmetic circuit 12x4 is connected to the i +1 th mode control circuit 12x3 and the i-th arithmetic circuit, and configured to perform an arithmetic operation on the i-th output signal according to the i +1 th control signal to output an i +1 th output signal.
Wherein the intermediate reference level comprises an upper intermediate reference level and a lower intermediate reference level,
the i +1 th operation circuit 12x4 operates the i-th output signal according to the i +1 th control signal to output an i +1 th output signal specifically includes:
acquiring and outputting an i +1 th output signal according to the following formula:
Vr,i+1＝2Vr,i-(di-1)VR
Vr,i+1output signal for i +1 th, Vr,iIs the ith output signal, diQuantizing the signal for the ith;
through the structure of the (i + 1) th intermediate quantization circuit 12i +1, the (i + 1) th intermediate reference level is generated according to the ith quantization signal, and quantization is performed according to the (i + 1) th intermediate reference level, so that the range of the reference voltage is reduced, the offset error is reduced, and the comparison precision is improved.
As shown in fig. 6, the end quantization circuit 13 includes an end reference level selection circuit 131 and an end comparison circuit 132.
An end reference level selection circuit 131 connected to the nth intermediate quantization circuit 12 and configured to generate an end reference level from the nth intermediate quantized signal;
an end comparison circuit 132, connected to the nth intermediate quantization circuit 12 and the end reference level selection circuit 131, is configured to quantize the nth output signal according to the end reference level to output an end quantized signal.
There are three cases for the nth intermediate quantized signal, corresponding to the three cases one by one, and the end comparison circuit 132 also has three cases, which are as follows:
in the first case, when the nth intermediate quantized signal is 00, the end comparing circuit 132 quantizes the nth output signal according to the end reference level to output the end quantized signal specifically:
acquiring and outputting an end quantized signal according to the following formula:
Figure BDA0002814074800000081
in the second case, when the nth intermediate quantized signal is 01, the end comparing circuit 132 quantizes the nth output signal according to the end reference level to output the end quantized signal specifically:
acquiring and outputting an end quantized signal according to the following formula:
Figure BDA0002814074800000082
in the third case, when the nth intermediate quantized signal is 10, the end comparing circuit 132 quantizes the nth output signal according to the end reference level to output the end quantized signal specifically:
acquiring and outputting an end quantized signal according to the following formula:
Figure BDA0002814074800000083
wherein d iszFor end-quantizing the signal, Vr,nFor the nth output signal, VRIs the reference voltage.
By the structure of the terminal quantization circuit 13, the terminal reference level is generated according to the nth quantization signal, and quantization is performed according to the terminal reference level, so that the range of the reference voltage is reduced, the offset error is reduced, and the comparison precision is improved.
Fig. 7 shows a partial example circuit structure of a comparison module in a pipeline analog-to-digital converter according to an embodiment of the present invention, fig. 8 shows a partial example circuit structure of an initial comparison circuit 112 in a pipeline analog-to-digital converter according to an embodiment of the present invention, fig. 9 shows a partial example circuit structure of an end comparison circuit 132 in a pipeline analog-to-digital converter according to an embodiment of the present invention, and for convenience of explanation, only the parts related to the embodiment of the present invention are shown, and details are as follows:
the 1 st comparison circuit 1212 and the i +1 st comparison circuit 12x2 each include a comparison module including a first comparator U1, a second comparator U2, a first preamplifier U3, a second preamplifier U4, a first amplifier U5, a second amplifier U6, a first switch assembly K1, a second switch assembly K2, a first latch U7, a second latch U8, a first nand gate U9, and a first inverter U10;
the reference signal input end of the first comparator U1 is the upper limit middle reference level input end of the comparison module, the input signal input end of the first comparator U1 is the ith output signal input end of the comparison module or the initial output signal input end of the comparison module, the output end of the first comparator U1 is connected with the input end of the first preamplifier U3, the output end of the first preamplifier U3 is connected with the input end of the first switch component K1, the output end of the first switch component K1 is connected with the input end of the first amplifier U5, the output end of the first amplifier U5 is connected with the input end of the first latch U7, the positive phase data output end of the first latch U7 is the low-order middle quantized signal output end of the comparison module,
the reference signal input end of the second comparator U2 is the lower limit middle reference level input end of the comparison module, the input signal input end of the second comparator U2 is the ith output signal input end of the comparison module or the initial output signal input end of the comparison module, the output end of the second comparator U2 is connected with the input end of the second preamplifier U4, the output end of the second preamplifier U2 is connected with the input end of the second switch component K2, the output end of the second switch component K22 is connected with the input end of the second amplifier U6, the output end of the second amplifier U6 is connected with the input end of the second latch U8, the non-inverting data output end of the second latch U8 is connected with the first input end of the first NAND gate U9, the inverting data output end of the first latch U7 is connected with the second input end of the first NAND gate U9, the output end of the first NAND gate U9 is connected with the input end of the first inverter U10, the output terminal of the first inverter U10 is the high-order intermediate quantized signal output terminal of the comparison module.
The initial reference level includes an upper limit initial reference level and a lower limit initial reference level, the initial comparison circuit 112 includes a third comparator U11, a fourth comparator U12, a third pre-amplifier U13, a fourth pre-amplifier U14, a third amplifier U15, a fourth amplifier U16, a third switching component K3, a fourth switching component K4, a third latch U17, a fourth latch U18, a second nand gate U19, and a second inverter U20;
the reference signal input end of the third comparator U11 is the upper limit initial reference level input end of the initial comparison circuit 112, the input signal input end of the third comparator U11 is the input signal input end of the initial comparison circuit 112, the output end of the third comparator U11 is connected with the input end of the third pre-amplifier U13, the output end of the third pre-amplifier U13 is connected with the input end of the third switch component K3, the output end of the third switch component K3 is connected with the input end of the third amplifier U15, the output end of the third amplifier U15 is connected with the input end of the third latch U17, the positive phase data output end of the third latch U17 is the lower level initial quantization signal output end of the initial comparison circuit 112,
the reference signal input end of the fourth comparator U12 is the lower-limit initial reference level input end of the initial comparison circuit 112, the input signal input end of the fourth comparator U12 is the input signal input end of the initial comparison circuit 112, the output end of the fourth comparator U12 is connected with the input end of the fourth pre-amplifier U14, the output end of the fourth pre-amplifier U12 is connected with the input end of the fourth switching element K4, the output end of the fourth switching element K4 is connected with the input end of the fourth amplifier U16, the output end of the fourth amplifier U16 is connected with the input end of the fourth latch U18, the non-inverting data output end of the fourth latch U18 is connected with the first input end of the second nand gate U19, the inverting data output end of the second latch U17 is connected with the second input end of the second nand gate U19, the output end of the second nand gate U19 is connected with the input end of the second inverter U20, and the output end of the second inverter U20 is the high-level initial quantization signal output end of the.
The end reference levels include an upper end reference level, a middle end reference level, and a lower end reference level, the end comparison circuit 132 includes a fifth comparator U21, a sixth comparator U22, a seventh comparator U23, a fifth pre-amplifier U24, a sixth pre-amplifier U25, a seventh pre-amplifier U26, a fifth amplifier U27, a sixth amplifier U28, a seventh amplifier U29, a fifth latch U30, a sixth latch U31, a seventh latch U32, a third nand gate U33, a fourth nand gate U34, a fifth nand gate U35, a fifth switch element K5, a sixth switch element K6, and a seventh switch element K7;
a reference signal input end of the fifth comparator U21 is an upper limit terminal reference level input end of the terminal comparison circuit 132, an input signal input end of the fifth comparator U21 is an nth output signal input end of the terminal comparison circuit 132, an output end of the fifth comparator U21 is connected with an input end of a fifth preamplifier U24, an output end of the fifth preamplifier U24 is connected with an input end of a fifth switching element K5, an output end of the fifth switching element K5 is connected with an input end of a fifth amplifier U27, and an output end of the fifth amplifier U27 is connected with an input end of a fifth latch U30;
a reference signal input end of the sixth comparator U22 is a middle-end reference level input end of the end comparison circuit 132, an input signal input end of the sixth comparator U22 is an nth output signal input end of the end comparison circuit 132, an output end of the sixth comparator U22 is connected with an input end of a sixth pre-amplifier U25, an output end of the sixth pre-amplifier U25 is connected with an input end of a sixth switch component K6, an output end of the sixth switch component K6 is connected with an input end of a sixth amplifier U28, and an output end of the sixth amplifier U28 is connected with an input end of a sixth latch U31;
a reference signal input end of the seventh comparator U23 is a lower limit end reference level input end of the end comparison circuit 132, an input signal input end of the seventh comparator U23 is an nth output signal input end of the end comparison circuit 132, an output end of the seventh comparator U23 is connected with an input end of a seventh pre-amplifier U26, an output end of the seventh pre-amplifier U26 is connected with an input end of a seventh switch component K7, an output end of the seventh switch component K7 is connected with an input end of a seventh amplifier U29, and an output end of the seventh amplifier U29 is connected with an input end of a seventh latch U32;
the positive phase data output terminal of the fifth latch U30 is connected to the positive phase data output terminal of the sixth latch U31 and the first input terminal of the third nand gate U33, the inverted data output terminal of the sixth latch U31 and the first input terminal of the fourth nand gate U34 together form the low-order end quantized signal output terminal of the end comparator 132, the second input terminal of the fourth nand gate U34 is connected to the inverted data output terminal of the sixth latch U32, the output terminal of the third nand gate U33 is connected to the first input terminal of the fifth nand gate U35, the output terminal of the fourth nand gate U34 and the second input terminal of the fifth nand gate U35 are connected, and the output terminal of the fifth nand gate U35 is the high-order end quantized signal output terminal of the end comparator 132.
The following further description of fig. 7 to 9 is made in conjunction with the working principle:
the initial comparison circuit 112 inputs the following signals: a positive upper limit initial reference level VREF1, a negative upper limit initial reference level VREF2, a positive lower limit initial reference level VREF3, a negative lower limit initial reference level VREF4, a first clock signal phi 1, a second clock signal phi 2, a positive Vin + of the input signal, and a negative Vin of the input signal. The first clock signal phi 1 and the second clock signal phi 2 have the same frequency and opposite phases.
In a specific implementation, the positive upper limit initial reference level VREF1, the negative upper limit initial reference level VREF2, the positive lower limit initial reference level VREF3, and the negative lower limit initial reference level VREF4 may be 1.375V, 1.125V, 1.375V, and 1.125V, respectively. If 1.25V is considered to be 0VR1.75V is regarded as 1VR0.75V is regarded as-1VRIf the voltage drop is +1/8V, the upper-limit initial reference level VREF1, the upper-limit initial reference level VREF2, the lower-limit initial reference level VREF3 and the lower-limit initial reference level VREF4 are respectively set to +1/8VR、-1/8VR、+1/8VRand-1/8VR. The upper initial reference level is VREF1-VREF2 +1/4VRThe lower initial reference level is VREF4-VREF 3-1/4VR。
If the value of the input signal Vin + -Vin-is less than-1/4VRThen, the higher initial quantized signal output terminal d0,1 outputs 0, and the lower initial quantized signal output terminal d0,0 outputs 0. If the input signal Vin + -Vin-is greater than-1/4VRAnd less than +1/4VRIf so, the higher initial quantized signal output terminal d0,1 outputs 0, and the lower initial quantized signal output terminal d0,0 outputs 1; if the input signal Vin + -Vin-is greater than+1/4VRThen, the higher initial quantized signal output terminal d0,1 outputs 1, and the lower initial quantized signal output terminal d0,0 outputs 0.
The operation of the intermediate quantization circuit is schematically illustrated in fig. 10, which is described in detail below in connection with the comparison block.
The comparison module inputs the following signals: an upper positive limit intermediate reference level VREF1, an upper negative limit intermediate reference level VREF2, a lower positive limit intermediate reference level VREF3, a lower negative limit intermediate reference level VREF4, a first clock signal phi 1, a second clock signal phi 2, a positive pole of the ith output signal (or a positive pole of the initial output signal) Vin + and a negative pole of the ith output signal (or a negative pole of the initial output signal) Vin-. The first clock signal phi 1 and the second clock signal phi 2 have the same frequency and opposite phases.
When the initial quantized signal d0 or the i-th intermediate quantized signal di is 00, the positive upper limit intermediate reference level VREF1, the negative upper limit intermediate reference level VREF2, the positive lower limit intermediate reference level VREF3, and the negative lower limit intermediate reference level VREF4 may be 1.0625V, 1.4375V, 1.5625V, and 0.9375V, respectively. Consider 1.25V to be 0VR1.75V is regarded as 1VR0.75V is regarded as-1VRIf the positive middle reference level VREF1, the negative middle reference level VREF2, the positive middle reference level VREF3 and the negative middle reference level VREF4 are-3/16VR、+3/16VR、+5/16VRand-5/16VR. The upper intermediate reference level is VREF1-VREF 2-3/8VRThe lower limit intermediate reference level VREF4-VREF3 is-5/8VRIf the value of the ith output signal (or initial output signal) is greater than-3/8VRThen, the higher intermediate quantized signal output terminal di +1,1 (or d1,1) outputs 1, and the lower intermediate quantized signal output terminal di +1,0 (or d1,0) outputs 0. If the value of the ith output signal (or the initial output signal) is less than-5/8VRIf so, the higher intermediate quantized signal output terminal di +1,1 (or d1,1) outputs 0, and the lower intermediate quantized signal output terminal di +1,0 (or d1,0) outputs 0; if the value of the ith output signal (or the initial output signal) is less than-3/8VRAnd is greater than-5/8VRHigh order intermediate quantized signal outputThe terminal di +1,1 (or d1,1) outputs 0, and the lower intermediate quantized signal output terminal di +1,0 (or d1,0) outputs 1.
When the initial quantized signal d0 or the ith intermediate quantized signal di is 01, the positive upper limit intermediate reference level VREF1, the negative intermediate reference level VREF2, the positive lower limit intermediate reference level VREF3, and the negative lower limit intermediate reference level VREF4 may be 1.3125V, 1.1875V, 1.3125V, and 1.1875V, respectively. The positive upper limit intermediate reference level VREF1, the negative intermediate reference level VREF2, the positive lower limit intermediate reference level VREF3, and the negative lower limit intermediate reference level VREF4 are +1/16V, respectivelyR、-1/16VR、+1/16VRand-1/16VR. The upper-limit intermediate reference level is VREF1-VREF2 +1/8VRThe lower limit intermediate reference level VREF4-VREF3 is-1/8VRIf the value of the ith output signal (or the initial output signal) is greater than +1/8VRThen, the higher intermediate quantized signal output terminal di +1,1 (or d1,1) outputs 1, and the lower intermediate quantized signal output terminal di +1,0 (or d1,0) outputs 0. (ii) a (ii) a If the value of the ith output signal (or the initial output signal) is less than-1/8VRIf so, the higher intermediate quantized signal output terminal di +1,1 (or d1,1) outputs 0, and the lower intermediate quantized signal output terminal di +1,0 (or d1,0) outputs 0; if the value of the ith output signal (or the initial output signal) is less than +1/8VRAnd is greater than-1/8VRThe higher intermediate quantized signal output terminal di +1,1 (or d1,1) outputs 0, and the lower intermediate quantized signal output terminal di +1,0 (or d1,0) outputs 1.
When the initial quantized signal d0 or the i-th intermediate quantized signal di is 10, the positive upper limit intermediate reference level VREF1, the negative intermediate reference level VREF2, the positive lower limit intermediate reference level VREF3, and the negative lower limit intermediate reference level VREF4 may be 1.5625V, 0.9375V, 1.0625V, and 1.4375V, respectively. The positive upper limit intermediate reference level VREF1, the negative intermediate reference level VREF2, the positive lower limit intermediate reference level VREF3, and the negative lower limit intermediate reference level VREF4 are +5/16V, respectivelyR、-3/16VR、-3/16VRAnd +3/16VR. The upper-limit intermediate reference level is VREF1-VREF2 +5/8VRThe lower limit intermediate reference level VREF4-VREF3 is +3/8VRIf the value of the ith output signal (or the initial output signal) is greater than +5/8VRThen, the higher intermediate quantized signal output terminal di +1,1 (or d1,1) outputs 1, and the lower intermediate quantized signal output terminal di +1,0 (or d1,0) outputs 0. (ii) a (ii) a If the value of the ith output signal (or the initial output signal) is less than +3/8VRIf so, the higher intermediate quantized signal output terminal di +1,1 (or d1,1) outputs 0, and the lower intermediate quantized signal output terminal di +1,0 (or d1,0) outputs 0; if the value of the ith output signal (or the initial output signal) is less than +5/8VRAnd greater than +3/8VRThe higher intermediate quantized signal output terminal di +1,1 (or d1,1) outputs 0, and the lower intermediate quantized signal output terminal di +1,0 (or d1,0) outputs 1.
The operation of the end quantization circuit 13 is schematically illustrated in fig. 11, and will be described in detail with reference to the end comparison module.
The end reference levels include an upper end reference level, a middle end reference level, and a lower end reference level, and the end comparison circuit 132 inputs the following signals: a positive upper limit end reference level VREF1, a negative upper limit end reference level VREF2, a positive middle end reference level VREF3, a negative middle end reference level VREF4, a positive lower limit end reference level VREF5, a negative lower limit end reference level VREF6, a first clock signal phi 1, a second clock signal phi 2, a positive Vin + of the nth output signal, and a negative Vin of the nth output signal. The first clock signal phi 1 and the second clock signal phi 2 have the same frequency and opposite phases.
When the nth intermediate quantization signal dn is 00, the positive upper limit end reference level VREF1, the negative upper limit end reference level VREF2, the positive intermediate end reference level VREF3, the negative intermediate end reference level VREF4, the positive lower limit intermediate reference level VREF5, and the negative lower limit intermediate reference level VREF6 may be 1.375V, 1.125V, 1.5V, 1V, 1.625V, and 0.875V, respectively. If 1.25V is considered to be 0VR1.75V is regarded as 1VR0.75V is regarded as-1VRPositive upper limit end reference level VREF1, negative upper limit end reference level VREF2, positive middle end reference level VREF3, negative middle end reference level VREF4, positive lower limitThe intermediate reference level VREF5 and the cathode lower limit intermediate reference level VREF6 may be +1/8V respectivelyR、-1/8VR、+1/4VR、-1/4VR、+3/8VRand-3/8VR. The upper end reference level is VREF1-VREF 2-1/4VRThe middle terminal reference level is VREF3-VREF 4-1/2VRLower limit end reference level VREF5-VREF 6-3/4VR(ii) a If the value of the nth output signal is greater than-1/4VRThen, the higher end quantized signal output terminal dn +1,1 outputs 1, and the lower end quantized signal output terminal dn +1,0 outputs 1. If the value of the nth output signal is less than-3/4VRIf so, the high-order terminal quantized signal output end dn +1,1 outputs 0, and the low-order terminal quantized signal output end dn +1,0 outputs 0; if the value of the nth output signal is less than-1/4VRAnd is greater than-1/2VRThe high-order terminal quantized signal output end dn +1,1 outputs 1, and the low-order terminal quantized signal output end dn +1,0 outputs 0; if the value of the nth output signal is less than-1/2VRAnd is greater than-3/4VRThe higher-order terminal quantized signal output terminal dn +1,1 outputs 0, and the lower-order terminal quantized signal output terminal dn +1,0 outputs 1.
When the nth intermediate quantization signal dn is 01, the positive upper limit end reference level VREF1, the negative upper limit end reference level VREF2, the positive intermediate end reference level VREF3, the negative intermediate end reference level VREF4, the positive lower limit intermediate reference level VREF5, and the negative lower limit intermediate reference level VREF6 may be 1.125V, 1.375V, 1.25V, 1.375V, and 1.125V, respectively. If 1.25V is considered to be 0VR1.75V is regarded as 1VR0.75V is regarded as-1VRThen the positive upper limit end reference level VREF1, the negative upper limit end reference level VREF2, the positive middle end reference level VREF3, the negative middle end reference level VREF4, the positive lower limit middle reference level VREF5, and the negative lower limit middle reference level VREF6 may be-1/8V, respectivelyR、+1/8VR、0VR、0VR、+1/8VRand-1/8VR. The upper end reference level is VREF1-VREF2 +1/4VRThe middle end reference level is VREF3-VREF4 equal to 0VRLower limit end reference level VREF5-VREF 6-1/4VR(ii) a If it isThe value of the nth output signal is greater than +1/4VRThen, the higher end quantized signal output terminal dn +1,1 outputs 1, and the lower end quantized signal output terminal dn +1,0 outputs 1. If the value of the nth output signal is less than-1/4VRIf so, the high-order terminal quantized signal output end dn +1,1 outputs 0, and the low-order terminal quantized signal output end dn +1,0 outputs 0; if the value of the nth output signal is less than +1/4VRAnd is greater than 0VRThe high-order terminal quantized signal output end dn +1,1 outputs 1, and the low-order terminal quantized signal output end dn +1,0 outputs 0; if the value of the nth output signal is less than 0VRAnd is greater than-1/4VRThe higher-order terminal quantized signal output terminal dn +1,1 outputs 0, and the lower-order terminal quantized signal output terminal dn +1,0 outputs 1.
When the nth intermediate quantization signal dn is 10, the positive upper limit end reference level VREF1, the negative upper limit end reference level VREF2, the positive intermediate end reference level VREF3, the negative intermediate end reference level VREF4, the positive lower limit intermediate reference level VREF5, and the negative lower limit intermediate reference level VREF6 may be 0.875V, 1.625V, 1V, 1.5V, 1.125V, and 1.375V, respectively. If 1.25V is considered to be 0VR1.75V is regarded as 1VR0.75V is regarded as-1VRThen the positive upper limit end reference level VREF1, the negative upper limit end reference level VREF2, the positive middle end reference level VREF3, the negative middle end reference level VREF4, the positive lower limit middle reference level VREF5, and the negative lower limit middle reference level VREF6 may be-3/8V, respectivelyR、+3/8VR、-1/4VR、+1/4VR、-1/8VRAnd +1/8VR. The upper end reference level is VREF1-VREF2 +3/4VRThe middle terminal reference level is VREF3-VREF 4-1/2VRLower limit end reference level VREF5-VREF6 ═ 1/4VR(ii) a If the value of the nth output signal is greater than +3/4VRThen, the higher end quantized signal output terminal dn +1,1 outputs 1, and the lower end quantized signal output terminal dn +1,0 outputs 1. If the value of the nth output signal is less than +1/4VRIf so, the high-order terminal quantized signal output end dn +1,1 outputs 0, and the low-order terminal quantized signal output end dn +1,0 outputs 0; if the value of the nth output signal is less than +34VRAnd greater than +1/2VRThe high-order terminal quantized signal output end dn +1,1 outputs 1, and the low-order terminal quantized signal output end dn +1,0 outputs 0; if the value of the nth output signal is less than +1/2VRAnd greater than +1/4VRThe higher-order terminal quantized signal output terminal dn +1,1 outputs 0, and the lower-order terminal quantized signal output terminal dn +1,0 outputs 1.
An exemplary circuit schematic of the amplifying circuit 111 is shown in fig. 12. The amplifying circuit 111 is composed of two symmetrical modules. Taking the first amplifying module 305 in the upper half as an example, the common mode voltage VM1 is the input common mode voltage of the first operational amplifier 306 working normally. Wherein the capacitance of the first capacitor 503 is equal to the capacitance of the second capacitor 504. First, when in the sampling operation state, the twenty-first switch 441, the twentieth switch 443, and the nineteenth switch 439 are closed, and the twenty-second switch 442 and the twentieth switch 440 are open; in the hold state operation, the twenty-first switch 441, the twenty-third switch 443, and the nineteenth switch 439 are opened, and the twenty-second switch 442 and the twentieth switch 440 are closed. The OUTP-OUTN voltage calculated according to the charge conservation principle is Vin + -Vin-. The mirror sampling unit mirror-symmetrical to the sampling unit 305 is similar to the sampling operation of the first amplification module 305. Keeping the voltage pressed 1: the 1 st intermediate quantization circuit 121 samples the input signal and outputs the sampled signal to the 1 st intermediate quantization circuit.
The 1 st operational circuit 1214 and the i +1 st operational circuit 12x4 each include an operational block, and an exemplary circuit schematic of the operational block is shown in fig. 13. The operation module is composed of an upper part and a lower part of symmetrical circuits to form a differential structure. Specifically, the operation module 301 calculates the input signal according to the output of the previous stage of comparison circuit. The capacitance of the third capacitor 501 is equal to the capacitance of the fourth capacitor 502.
If the output of the comparator circuit at the previous stage is 00, first, in the sampling phase, the fourteenth switch 434, the fifteenth switch 435, the seventeenth switch 437, the eleventh switch 431, and the second switch 432 are turned off, and the sixteenth switch 436, the eighteenth switch 438, and the thirteenth switch 433 are turned on. Then, in the holding stage, the fourteenth switch 434, the sixteenth switch 436, the seventeenth switch 437, the eighteenth switch 438, the twelfth switch 432, and the tenth switchThe switch 433 is open and the fifteenth switch 435 and the eleventh switch 431 are closed. The module of lower part sets up with the module mirror image of upper portion, and the switching mode is unanimous, constitutes difference structure. The OUTP-OUTN voltage is calculated according to the charge conservation principle to be 2(INN-INP) + VREF, namely Vr,i+1＝2Vr,i+VROr Vr,1＝2Vin+VR。
If the output of the comparator circuit at the previous stage is 01, first, in the sampling phase, the fourteenth switch 434, the fifteenth switch 435, the seventeenth switch 437, the eleventh switch 431, and the twelfth switch 432 are turned off, and the sixteenth switch 436, the eighteenth switch 438, and the thirteenth switch 433 are turned on. Then, in the holding phase, the fourteenth switch 434, the fifteenth switch 435, the sixteenth switch 436, the eleventh switch 431, the eighteenth switch 438, and the thirteenth switch 433 are opened, and the seventeenth switch 437 and the twelfth switch 432 are closed. The modules of the upper part and the modules of the lower part are mirrored, and the switching modes are consistent, so that a differential structure is formed. The OUTP-OUTN voltage calculated according to the charge conservation principle is 2(VINN-VINP), i.e. Vr,i+1＝2Vr,iOr Vr,1＝2Vin。
If the output of the comparator circuit at the previous stage is 10, first, in the sampling phase, the fourteenth switch 434, the fifteenth switch 435, the seventeenth switch 437, the eleventh switch 431, and the twelfth switch 432 are turned off, and the sixteenth switch 436, the eighteenth switch 438, and the thirteenth switch 433 are turned on. Then, in the holding stage, the twelfth switch 432, the fifteenth switch 435, the sixteenth switch 436, the seventeenth switch 437, the eighteenth switch 438, and the thirteenth switch 433 are opened, and the fourteenth switch 434 and the eleventh switch 431 are closed. The modules of the upper part and the modules of the lower part are mirrored, and the switching modes are consistent, so that a differential structure is formed. The OUTP-OUTN voltage calculated according to the charge conservation principle is 2(INN-INP) -VREF, namely Vr,i+1＝2Vr,i-VROr Vr,1＝2Vin-VR。
By way of example and not limitation, an exemplary circuit schematic of the initial comparison circuit 112 and the comparison module are shown in FIG. 14. The gate voltage Vbias of the current source tube provides bias current for the comparison module, in the sampling phase, the ith output signal (or initial output signal) is simultaneously closed by the first switch 701, the second switch 702, the third switch 703, the sixth switch 706, the seventh switch 707 and the eighth switch 708, the fourth switch 704 and the ninth switch 709 are opened, the ith output signal (or initial output signal) is compared with the upper limit middle reference level by the comparison module in the upper half part, and the ith output signal (or initial output signal) is compared with the lower limit middle reference level by the comparison module in the lower half part; then the fourth switch 704 and the ninth switch 709 are closed, and the enable signal EN opens the inverter, further amplifies the amplified comparison result to a high level and a low level, and finally latches the comparison result through the third latch 705 and the fourth latch 710.
An exemplary circuit schematic of the end comparator circuit 132 is shown in fig. 15.
The calculation process will be described below by taking the input signal 536mV as an example, and is shown in fig. 16.
1) The input signal 536mV is input to the initial quantization circuit 11,
after being amplified by the amplification module according to the ratio of 1:1, 536mV outputs Vr, and 0 is 536 mV;
536mV higher than 1/4VRTherefore, the initial quantized signal d0 is 10;
2)536mV is provided as input to the 1 st intermediate quantization circuit 121.
The 1 st output signal of the 1 st intermediate quantization circuit 121 is Vr,1＝2Vin-(d0-1)VR＝2*536mV-1000mV＝72mV
Since d0 is 10, the upper limit intermediate reference level and the lower limit intermediate reference level of the 1 st comparing circuit 1212 in the 1 st intermediate quantizing circuit 121 are 5/8V, respectivelyRAnd 3/8VRSince 536mV is less than 5/8VRAnd is greater than 3/8VRTherefore, the 1 st quantized signal d1 is 01;
3)72mV as input to the 2 nd intermediate quantization circuit;
the 2 nd output signal of the 2 nd intermediate quantization circuit is Vr,i+1＝2Vr,i-(di-1)VR＝2*72mV＝144mV；
Since d1 is 01, the upper limit intermediate reference level and the lower limit intermediate reference level of the 2 nd comparing circuit in the 2 nd intermediate quantizing circuit are-1/8V, respectivelyRAnd 1/8VR72mV less than 1/8VRAnd is greater than-1/8VRTherefore, the 2 nd quantized signal d2 is 01;
4)144mV as input to the end quantization circuit 13;
since the 2 nd quantized signal d2 is 01, the upper limit end reference level, the middle end reference level and the lower limit end reference level of the end comparing circuit 132 in the end quantizing circuit 13 are-1/4V, respectivelyR0 and 1/4VR144mV less than 1/4VRAnd is greater than 0, so the end quantized signal dn +1(d3) is 10;
5) all d0 and d3 would be summed in the delay alignment block as shown in fig. 17, resulting in final outputs b4, b3, b2, b1, and b0 of 11000.
The embodiment of the present invention further provides a transceiver chip, which is characterized by including the pipeline analog-to-digital converter.
The embodiment of the invention is connected step by step through an initial quantization circuit, n intermediate quantization circuits and a tail end quantization circuit; wherein n is a natural number; the initial quantization circuit is configured to amplify an input signal by a 1-fold ratio to output an initial output signal, and quantize the input signal according to an initial reference level to output an initial quantized signal; the 1 st intermediate quantization circuit quantizes the initial output signal according to the initial quantization signal to output a 1 st intermediate quantization signal, and operates the initial output signal according to the initial quantization signal to output a 1 st output signal; the (i + 1) th intermediate quantization circuit quantizes the (i) th output signal according to the (i) th intermediate quantization signal to output an (i + 1) th intermediate quantization signal, and operates the (i) th output signal according to the (i) th quantization signal to output an (i + 1) th output signal; wherein i is a natural number less than n; an end quantization circuit generates an end reference level from the nth intermediate quantized signal and quantizes the nth output signal according to the end reference level to output an end quantized signal; the delay alignment circuit performs delay alignment and staggered addition on the initial quantized signal, the n middle quantized signals and the tail end quantized signal and outputs a total quantized signal; because the intermediate quantization circuit and the tail end quantization circuit set reference levels according to the quantization circuit of the previous stage, the range of reference voltage is reduced, the offset error is reduced, and the comparison precision is improved.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (10)

1. A pipelined analog-to-digital converter is characterized by comprising an initial quantization circuit, n intermediate quantization circuits, an end quantization circuit and a delay alignment circuit;
the initial quantization circuit, the n intermediate quantization circuits and the tail end quantization circuit are connected in a step-by-step mode; wherein n is a natural number;
the initial quantization circuit is configured to amplify an input signal by a 1-fold ratio to output an initial output signal and quantize the input signal according to an initial reference level to output an initial quantized signal when the input signal is received;
the 1 st one of the intermediate quantization circuits is configured to quantize the initial output signal according to the initial quantization signal to output a 1 st intermediate quantization signal, and operate on the initial output signal according to the initial quantization signal to output a 1 st output signal;
the i +1 th intermediate quantization circuit is configured to quantize an i-th output signal according to an i-th intermediate quantization signal to output an i + 1-th intermediate quantization signal, and operate on the i-th output signal according to the i-th quantization signal to output an i + 1-th output signal; wherein i is a natural number less than n; the maximum value of i +1 is n;
the end quantization circuit is configured to generate an end reference level from the nth intermediate quantized signal and quantize the nth output signal according to the end reference level to output an end quantized signal;
the delay alignment circuit is connected with the initial quantization circuit, the n intermediate quantization circuits and the tail end quantization circuit; is configured to delay align and stagger add the initial quantized signal, the n intermediate quantized signals and the end quantized signal and output a summed quantized signal.
2. The pipelined analog-to-digital converter of claim 1, wherein said 1 st of said intermediate quantization circuits comprises:
a 1 st reference level selection circuit, connected to the initial quantization circuit, configured to generate a 1 st intermediate reference level from the initial quantized signal;
a 1 st comparison circuit, connected to the 1 st reference level selection circuit and the initial quantization circuit, configured to quantize the initial output signal according to the 1 st intermediate reference level to output a 1 st intermediate quantized signal;
the 1 st mode control circuit is connected with the initial quantization circuit and is configured to generate a 1 st control signal according to the initial quantization signal;
a 1 st operation circuit connected to the initial quantization circuit and the 1 st mode control circuit, and configured to operate the initial output signal according to the 1 st control signal to output a 1 st output signal;
the i +1 th intermediate quantization circuit includes:
an i +1 th reference level selection circuit connected to the i-th comparison circuit and configured to generate an i +1 th intermediate reference level from the i-th intermediate quantized signal;
an i +1 th comparison circuit, connected to the i +1 th reference level selection circuit and the i-th arithmetic circuit, configured to quantize an i-th output signal according to the i + 1-th intermediate reference level to output an i + 1-th intermediate quantized signal;
the (i + 1) th mode control circuit is connected with the (i) th comparison circuit and is configured to generate an (i + 1) th control signal according to the (i) th quantized signal;
and the (i + 1) th operation circuit is connected with the (i + 1) th mode control circuit and the (i) th operation circuit and is configured to operate the (i) th output signal according to the (i + 1) th control signal so as to output an (i + 1) th output signal.
3. The pipeline analog-to-digital converter of claim 2, wherein the intermediate reference levels comprise an upper intermediate reference level and a lower intermediate reference level.
4. The pipeline adc of claim 3, wherein said 1 st operation circuit operating on said 1 st control signal to output a 1 st output signal is specifically:
acquiring the 1 st output signal according to the following formula and outputting the signal:
Vr,1＝2Vin-(d0-1)VR
wherein, Vr,1For the 1 st output signal, VinFor said initial output signal, d0For the initial quantized signal, VRIs a reference voltage;
when the initial quantized signal is 00, the 1 st upper limit middle reference level is-3/8VRThe 1 st lower limit intermediate reference level is-5/8VRThe step 1 of quantizing the initial output signal according to the 1 st intermediate reference level by the 1 st comparison circuit to output a 1 st intermediate quantized signal may specifically be:
acquiring the 1 st intermediate quantized signal according to the following formula and outputting the signal:
Figure FDA0002814074790000021
when the initial quantized signal is 01, the 1 st upper limit middle reference level is 1/8VRThe 1 st lower limit intermediate reference level is-1/8VRThe step 1 of quantizing the initial output signal according to the 1 st intermediate reference level by the 1 st comparison circuit to output a 1 st intermediate quantized signal may specifically be:
acquiring the 1 st intermediate quantized signal according to the following formula and outputting the signal:
Figure FDA0002814074790000022
when the initial quantized signal is 10, the 1 st upper limit middle reference level is 3/8VRThe 1 st lower limit intermediate reference level is 5/8VRThe step 1 of quantizing the initial output signal according to the 1 st intermediate reference level by the 1 st comparison circuit to output a 1 st intermediate quantized signal may specifically be:
acquiring the 1 st intermediate quantized signal according to the following formula and outputting the signal:
Figure FDA0002814074790000031
wherein, Vr，0Is the initial output signal; d1For said 1 st intermediate quantized signal, VRIs the reference voltage.
5. The pipeline adc of claim 3, wherein the i +1 th operation circuit operating the i-th output signal according to the i + 1-th control signal to output the i + 1-th output signal is specifically:
acquiring and outputting the (i + 1) th output signal according to the following formula:
Vr,i+1＝2Vr,i-(di-1)VR
Vr,i+1for the (i + 1) th inputOut of a signal, Vr,iFor the i-th output signal, diQuantizing the signal for the ith;
when the ith quantized signal is 00, the i +1 th upper limit middle reference level is-3/8VRThe i +1 th lower limit intermediate reference level is-5/8VRThe step of quantizing the ith output signal by the i +1 th comparison circuit according to the i +1 th intermediate reference level to output an i +1 th intermediate quantized signal may specifically be:
acquiring the i +1 th intermediate quantized signal according to the following formula and outputting the signal:
Figure FDA0002814074790000032
when the ith quantized signal is 01, the i +1 th upper limit middle reference level is 1/8VRThe i +1 th lower limit intermediate reference level is-1/8VRThe step of quantizing the ith output signal by the i +1 th comparison circuit according to the i +1 th intermediate reference level to output an i +1 th intermediate quantized signal may specifically be:
acquiring the i +1 th intermediate quantized signal according to the following formula and outputting the signal:
Figure FDA0002814074790000033
when the ith quantized signal is 10, the i +1 th upper limit middle reference level is 3/8VRThe i +1 th lower limit intermediate reference level is 5/8VRThe step of quantizing the ith output signal by the i +1 th comparison circuit according to the i +1 th intermediate reference level to output an i +1 th intermediate quantized signal may specifically be:
acquiring the i +1 th intermediate quantized signal according to the following formula and outputting the signal:
Figure FDA0002814074790000041
wherein d isi+1Intermediate quantization for the i +1 thSignal, Vr,iFor the ith output signal, VRIs the reference voltage.
6. The pipelined analog-to-digital converter of claim 1, wherein the initial quantization circuit comprises:
an amplification circuit configured to amplify the input signal by a 1-fold ratio to output the initial output signal when receiving the input signal;
an initial comparison circuit configured to quantize the input signal according to the initial reference level to output an initial quantized signal.
7. The pipeline analog-to-digital converter of claim 7, wherein the initial reference levels comprise an upper initial reference level and a lower initial reference level, the upper initial reference level being 1/4VRThe lower initial reference level is-1/4VRThe quantizing the input signal according to the initial reference level by the initial comparison circuit to output an initial quantized signal specifically includes:
acquiring an initial quantized signal according to the following formula and outputting the signal:
Figure FDA0002814074790000042
wherein d is0For the initial quantized signal, VinFor said input signal, VRIs the reference voltage.
8. The pipelined analog-to-digital converter of claim 1, wherein the end quantization circuit comprises:
an end reference level selection circuit coupled to the nth intermediate quantization circuit and configured to generate the end reference level from the nth intermediate quantized signal;
an end comparison circuit, coupled to the nth intermediate quantization circuit and the end reference level selection circuit, configured to quantize the nth output signal according to the end reference level to output the end quantized signal.
9. The pipelined analog-to-digital converter of claim 8, wherein when the nth intermediate quantized signal is 00, the end comparison circuit quantizes the nth output signal according to the end reference level to output the end quantized signal is specifically:
acquiring the terminal quantized signal according to the following formula and outputting the terminal quantized signal:
Figure FDA0002814074790000051
when the nth intermediate quantized signal is 01, the terminal comparing circuit quantizes the nth output signal according to the terminal reference level to output the terminal quantized signal specifically includes:
acquiring the terminal quantized signal according to the following formula and outputting the terminal quantized signal:
Figure FDA0002814074790000052
when the nth intermediate quantized signal is 10, the terminal comparing circuit quantizes the nth output signal according to the terminal reference level to output the terminal quantized signal specifically includes:
acquiring the terminal quantized signal according to the following formula and outputting the terminal quantized signal:
Figure FDA0002814074790000053
wherein d iszQuantizing the signal for said end, Vr,nFor the n-th output signal, VRIs the reference voltage.
10. A transceiver chip comprising a pipeline analog-to-digital converter as claimed in any one of claims 1 to 9.
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