CN216414284U - Analog-to-digital conversion circuit and transceiving system - Google Patents

Abstract

The application provides an analog-to-digital conversion circuit and a transceiving system, wherein a phase signal is generated through a clock module; obtaining a first quantized signal through a first quantization module; obtaining a second quantized signal through a second quantization module; obtaining a third quantized signal through a third quantization module; obtaining a fourth quantized signal through a fourth quantization module; and carrying out delay alignment and addition on the first quantized signal, the second quantized signal, the third quantized signal and the fourth quantized signal through a delay alignment module to obtain a final analog-to-digital conversion value. According to the method and the device, the sampling and holding circuit and the first-stage sub-quantization circuit in the traditional pipeline analog-to-digital conversion circuit are replaced by the first quantization module, so that not only can an input signal be sampled, but also a first quantization signal can be output, the quantization process is simplified, and the power consumption is reduced.

Description

Analog-to-digital conversion circuit and transceiving system

Technical Field

The application belongs to the technical field of integrated circuits, and particularly relates to an analog-to-digital conversion circuit and a transceiving system.

Background

The transceiving performance of the serializer/deserializer system is largely dependent on the performance of the Analog-to-Digital Converter (ADC), mainly related to the conversion rate, resolution and power consumption of the ADC. In a receiving and transmitting system of intermediate frequency sampling, limited by the performance requirements of high speed and high precision, a pipeline analog-to-digital converter is most suitable for transmitting data in all the current analog-to-digital converters.

However, the traditional pipeline analog-to-digital conversion circuit is generally internally provided with a sub-quantization circuit corresponding to quantization bits, so that the quantization process is complicated and the power consumption is high.

SUMMERY OF THE UTILITY MODEL

The application aims to provide an analog-to-digital conversion circuit and a transceiving system, and aims to solve the problem that a traditional analog-to-digital conversion circuit is high in power consumption.

In order to achieve the above object, in a first aspect, an embodiment of the present application provides an analog-to-digital conversion circuit, including:

a clock module configured to generate a phase signal;

the first quantization module is electrically connected with the clock module and is configured to be triggered to be switched on or switched off by the phase signal, amplify an input signal to obtain a first amplified signal and compare the input signal with a fixed level to obtain a first quantized signal;

the second quantization module is electrically connected with the clock module and the first quantization module, and is configured to be triggered by the phase signal to be switched on or switched off, amplify the first amplified signal to obtain a second amplified signal, determine a first reference level according to the first quantized signal, and compare the first amplified signal with the first reference level to obtain a second quantized signal;

the third quantization module is electrically connected with the clock module and the second quantization module, and is configured to be triggered by the phase signal to be switched on or switched off, amplify the second amplified signal to obtain a third amplified signal, determine a second reference level according to the second quantized signal, and compare the second amplified signal with the second reference level to obtain a third quantized signal;

the fourth quantization module is electrically connected with the clock module and the third quantization module, is configured to be triggered to be switched on or switched off by the phase signal, determines a third reference level according to the third quantization signal, and compares the third amplified signal with the third reference level to obtain a fourth quantization signal;

a delay alignment module electrically connected to the first quantization module, the second quantization module, the third quantization module and the fourth quantization module, and configured to delay align and add the first quantized signal, the second quantized signal, the third quantized signal and the fourth quantized signal to obtain a final analog-to-digital conversion value.

In one possible implementation of the first aspect, the first quantization module includes:

the first analog-to-digital converter is electrically connected with the clock module and is configured to be triggered to be switched on or switched off by the phase signal, and the input signal is compared with the fixed level to obtain a first quantized signal;

the first amplifier is electrically connected with the first analog-to-digital converter and is configured to amplify the input signal to obtain a first amplified signal.

In another possible implementation of the first aspect, the first analog-to-digital converter comprises:

a fixed level generating unit configured to generate a first reference voltage, a second reference voltage, a third reference voltage, and a fourth reference voltage;

the first analog-to-digital conversion unit is electrically connected with the fixed level generation unit and the clock module and is configured to be triggered by the phase signal to be switched on or switched off, and the input signal is compared with the difference value between the first reference voltage and the second reference voltage to obtain the high value of the first quantized signal;

and the second analog-to-digital conversion unit is electrically connected with the fixed level generation unit and the clock module, is configured to be triggered by the phase signal to be switched on or switched off, compares the input signal with the difference value of the third reference voltage and the fourth reference voltage, and obtains the low value of the first quantized signal by combining the high value of the first quantized signal.

In another possible implementation manner of the first aspect, the second quantization module includes:

the second analog-to-digital converter is electrically connected with the clock module and the first quantization module, is configured to be triggered by the phase signal to be switched on or switched off, determines a first reference level according to the first quantization signal, and compares the first amplified signal with the first reference level to obtain a second quantization signal;

the first digital-to-analog converter is electrically connected with the second analog-to-digital converter and the first quantization module and is configured to amplify the first amplified signal to obtain a second amplified signal.

In another possible implementation of the first aspect, the second analog-to-digital converter comprises:

a first level selection unit electrically connected to the first quantization module and configured to determine a fifth reference voltage, a sixth reference voltage, a seventh reference voltage and an eighth reference voltage according to a first quantization signal;

a third analog-to-digital conversion unit electrically connected to the first level selection unit and the clock module, and configured to be triggered by the phase signal to turn on or off, and compare the first amplified signal with a difference between the fifth reference voltage and the sixth reference voltage to obtain a high value of the second quantized signal;

and the fourth analog-to-digital conversion unit is electrically connected with the first level selection unit and the clock module, is configured to be triggered by the phase signal to be switched on or switched off, compares the first amplified signal with a difference value between the seventh reference voltage and the eighth reference voltage, and obtains a low value of the second quantized signal by combining a high value of the second quantized signal.

In another possible implementation manner of the first aspect, the first digital-to-analog converter includes:

a first logic control unit electrically connected with the second analog-to-digital converter and the first quantization module and configured to determine a first control signal according to the first quantization signal;

the second amplifier is electrically connected with the first logic control unit and is configured to amplify the first amplified signal according to the first control signal to obtain a second amplified signal.

In another possible implementation manner of the first aspect, the third quantization module includes:

the third analog-to-digital converter is electrically connected with the clock module and the second quantization module, is configured to be triggered by the phase signal to be switched on or switched off, determines a second reference level according to the second quantization signal, and compares the second amplified signal with the second reference level to obtain a third quantization signal;

and the second digital-to-analog converter is electrically connected with the third analog-to-digital converter and the second quantization module and is configured to amplify the second amplified signal to obtain a third amplified signal.

In another possible implementation manner of the first aspect, the fourth quantization module includes a fourth analog-to-digital converter, which is electrically connected to the clock module and the third quantization module, and is configured to be triggered by the phase signal to turn on or off, determine a third reference level according to the third quantization signal, and compare the third amplified signal with the third reference level to obtain a fourth quantization signal.

In another possible implementation of the first aspect, the fourth analog-to-digital converter includes:

a second level selection unit electrically connected to the third quantization module and configured to determine a ninth reference voltage, a tenth reference voltage, an eleventh reference voltage, a twelfth reference voltage, a thirteenth reference voltage and a fourteenth reference voltage according to a third quantization signal;

a fifth analog-to-digital conversion unit electrically connected to the second level selection unit and the clock module, and configured to be triggered by the phase signal to turn on or off, and compare the third amplified signal with a difference between the ninth reference voltage and the tenth reference voltage to obtain a high value of the fourth quantized signal;

a sixth analog-to-digital conversion unit electrically connected to the second level selection unit and the clock module, and configured to be triggered by the phase signal to turn on or off, compare the third amplified signal with a difference between the eleventh reference voltage and the twelfth reference voltage, and obtain a first bit value of the fourth quantized signal by combining a high bit value of the fourth quantized signal;

a seventh analog-to-digital conversion unit electrically connected to the second level selection unit and the clock module, and configured to be triggered by the phase signal to turn on or off, compare the third amplified signal with a difference between the thirteenth reference voltage and the fourteenth reference voltage, and then combine a high value of the fourth quantized signal and a second value of the fourth quantized signal to obtain a low value of the fourth quantized signal.

In a second aspect, an embodiment of the present application provides a transceiver system, which includes the analog-to-digital conversion circuit.

Compared with the prior art, the embodiment of the utility model has the following beneficial effects: according to the analog-digital conversion circuit, the sampling and holding circuit and the first-stage sub-quantization circuit in the traditional assembly line analog-digital conversion circuit are replaced by the first quantization module, so that not only can an input signal be sampled, but also the first quantization signal can be output, the quantization process is simplified, and the power consumption is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present disclosure;

fig. 2 is a circuit diagram of an analog-to-digital conversion circuit according to an embodiment of the present application;

fig. 3 is a circuit diagram of a first analog-to-digital converter of the analog-to-digital conversion circuit provided in the embodiment of the present application;

fig. 4 is a circuit diagram of a second analog-to-digital converter of the analog-to-digital conversion circuit provided in the embodiment of the present application;

fig. 5 is a circuit diagram of a first digital-to-analog converter of the analog-to-digital conversion circuit provided in the embodiment of the present application;

fig. 6 is a circuit diagram of a fourth analog-to-digital converter of the analog-to-digital conversion circuit provided in the embodiment of the present application;

fig. 7 is a quantization diagram of quantization modules 2 to N-1 of an analog-to-digital conversion circuit according to an embodiment of the present disclosure;

fig. 8 is a quantization diagram of an nth quantization module of an analog-to-digital conversion circuit according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram of five-bit analog-to-digital conversion and quantization of an analog-to-digital conversion circuit according to an embodiment of the present application.

Wherein, in the figures, the respective reference numerals:

1-clock module, 2-first quantization module, 21-first analog-to-digital converter, 211-fixed level generating unit, 212-first analog-to-digital converting unit, 213-second analog-to-digital converting unit, 22-first amplifier, 3-second quantization module, 31-second analog-to-digital converter, 311-first level selecting unit, 312-third analog-to-digital converting unit, 313-fourth analog-to-digital converting unit, 32-first analog-to-digital converter, 321-first logic control unit, 322-second amplifier, 4-third quantization module, 41-third analog-to-digital converter, 42-second analog-to-digital converter, 5-fourth quantization module, 51-fourth analog-to-digital converter, 511-second level selecting unit, 512-fifth analog-to-digital converting unit, 513-a sixth analog-to-digital conversion unit, 514-a seventh analog-to-digital conversion unit, 6-delay alignment module.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "electrically connected" to another element, it can be directly electrically connected to the other element or be indirectly electrically connected to the other element.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings that is solely for the purpose of facilitating the description and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the present application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

At present, in a traditional pipeline analog-to-digital conversion circuit, an input signal is sampled through a sampling and holding circuit, and a corresponding quantization signal is output through each level of sub quantization modules, so that the quantization process is complicated, and the consumed power consumption is high.

In view of the above problems, the present application provides an analog-to-digital conversion circuit, which replaces a sample-and-hold circuit and a first-stage sub-quantization circuit in a conventional pipeline analog-to-digital conversion circuit with a first quantization module, and can not only sample an input signal, but also output a first quantization signal, thereby simplifying a quantization process and reducing power consumption.

Fig. 1 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present application, and as shown in fig. 1, for convenience of description, only parts related to the embodiment are shown, and detailed descriptions are as follows: the analog-to-digital conversion circuit may include:

a clock module 1 configured to generate a phase signal;

the first quantization module 2 is electrically connected with the clock module 1 and is configured to be triggered by the phase signal to be switched on or switched off, amplify the input signal to obtain a first amplified signal and compare the input signal with a fixed level to obtain a first quantized signal;

the second quantization module 3 is electrically connected with the clock module 1 and the first quantization module 2, and is configured to be triggered by the phase signal to be switched on or switched off, amplify the first amplified signal to obtain a second amplified signal, determine a first reference level according to the first quantized signal, and compare the first amplified signal with the first reference level to obtain a second quantized signal;

the third quantization module 4 is electrically connected with the clock module 1 and the second quantization module 3, and is configured to be triggered by the phase signal to be switched on or switched off, amplify the second amplified signal to obtain a third amplified signal, determine a second reference level according to the second quantized signal, and compare the second amplified signal with the second reference level to obtain a third quantized signal;

the fourth quantization module 5 is electrically connected with the clock module 1 and the third quantization module 4, is configured to be triggered by the phase signal to turn on or turn off itself, determines a third reference level according to the third quantization signal, and compares the third amplified signal with the third reference level to obtain a fourth quantization signal;

and the delay alignment module 6 is electrically connected with the first quantization module 2, the second quantization module 3, the third quantization module 4 and the fourth quantization module 5, and is configured to delay align the first quantized signal, the second quantized signal, the third quantized signal and the fourth quantized signal and add the signals to obtain a final analog-to-digital conversion value.

In the embodiment of the application, the phase signal is generated by the clock module

Amplifying the input signal according to the proportion of 1:1 by a first quantization module to obtain a first amplified signal Vr,1, comparing and quantizing the input signal and a fixed level to obtain a first quantization result d1, and outputting the first quantization result d 1; amplifying the first amplified signal Vr,1 according to the ratio of 1:2 through a second quantization module, outputting a second amplified signal Vr,2, determining a first reference level according to the first quantized signal d1, comparing and quantizing the first amplified signal Vr,1 and the first reference level, obtaining and outputting a second quantized signal d 2; amplifying the second amplified signal Vr,2 according to the ratio of 1:2 by a third quantization module to obtain a third amplified signal Vr,3, determining a second reference level according to the second quantized signal d2, comparing and quantizing the second amplified signal Vr,2 and the second reference level to obtain a third quantized signal d3, and outputting the third quantized signal d 3; determining a third reference level according to the third quantized signal d3 through a fourth quantization module, and comparing and quantizing the third amplified signal Vr,3 with the third reference level to obtain and output a fourth quantized signal d 4; and performing delay alignment on the first quantized signal d1, the second quantized signal d2, the third quantized signal d3 and the fourth quantized signal d4 through a delay alignment module, and adding to obtain a final analog-to-digital conversion value.

The first quantized signal d1 of the first quantization module is:

residue expression of the first quantization module: v_r,1＝V_in。

When the first quantized signal d1 is 00, the second quantized signal d2 of the second quantization module is:

when the first quantized signal d1 is 01, the second quantized signal d2 of the second quantization module is:

when the first quantized signal d1 is 10, the second quantized signal d2 of the second quantization module is:

a second quantization module residue expression: v_r,2＝2V_in-(d₁-1)V_R。

The third quantization module can be expanded into a plurality of quantization modules, and is suitable for analog-to-digital conversion of more bits;

when the second quantized signal d2 is 00, the third quantized signal d3 of the third (or ith) quantized module is:

when the second quantized signal d2 is 01, the third quantized signal d3 of the third (or ith) quantized module is:

when the second quantized signal d2 is 10, the third quantized signal d3 of the third (or ith) quantized module is:

a third quantization module residue expression: v_r,2＝2V_in-(d_i-1)V_R。

When the third quantized signal d3 is 00, the fourth quantized signal d4 of the fourth (or last stage, N stages in total) quantization module is:

when the third quantized signal d3 is 01, the fourth quantized signal d4 of the fourth (or last stage, N stages in total) quantization module is:

when the third quantized signal d3 is 10, the fourth quantized signal d4 of the fourth (or last stage, N stages in total) quantization module is:

as shown in table 1, the final analog-to-digital conversion value is: (taking 5-bit pipeline ADC structure as an example)

TABLE 1 delay-aligned additive Table of d1, d2, d3, d4

Fig. 2 is a circuit diagram of an analog-to-digital conversion circuit provided in an embodiment of the present application, and as shown in fig. 2, for example, the first quantization module 2 may include:

the first analog-to-digital converter 21 is electrically connected with the clock module 1, and is configured to be triggered by the phase signal to be switched on or switched off, and compare the input signal with a fixed level to obtain a first quantized signal;

the first amplifier 22 is electrically connected to the first analog-to-digital converter 21 and configured to amplify the input signal to obtain a first amplified signal.

In the embodiment of the application, the input signal is compared and quantized with a fixed level through a first analog-to-digital converter to obtain a first quantized signal, and the input signal is amplified through a first amplifier to obtain a first amplified signal for use by a subsequent analog-to-digital converter.

Fig. 3 is a circuit diagram of a first analog-to-digital converter of the analog-to-digital conversion circuit provided in the embodiment of the present application, and as shown in fig. 3, for example, the first analog-to-digital converter 21 includes:

a fixed level generating unit 211 configured to generate a first reference voltage VREF1, a second reference voltage VREF2, a third reference voltage VREF3, and a fourth reference voltage VREF 4;

a first analog-to-digital conversion unit 212 electrically connected to the fixed level generation unit 211 and the clock module 1, and configured to be triggered by the phase signal to turn on or off itself, and compare the input signal with a difference between the first reference voltage and the second reference voltage to obtain a high value of the first quantized signal;

and a second analog-to-digital conversion unit 213 electrically connected to the fixed level generation unit 211 and the clock module 1, and configured to be triggered by the phase signal to turn on or off itself, compare the input signal with a difference between a third reference voltage and a fourth reference voltage, and obtain a low value of the first quantized signal by combining a high value of the first quantized signal.

In an embodiment of the application, the input of the first analog-to-digital converter comprises a clock signal generated by a clock module

Phase sum

The phase and input signal Vin, Vin + minus Vin-is Vin. The output ports are 2 in total: d1,0, d1, 1. Wherein VREF1, VREF2, VREF3 and VREF4 are respectively 1.375V, 1.125V, 1.375V and 1.125V. (if 1.25V is considered 0Vref, 2.25V is considered as1Vref, considering 0.25V as-1 Vref, these four voltages can be written as: +1/8Vref, -1/8Vref, +1/8Vref and-1/8 Vref)

The four levels are generated by a fixed level generation unit, and two differential voltages are VREF1-VREF2 ═ 1/4VREF, VREF4-VREF3 ═ -1/4 VREF;

if the value of the input signal Vin + -Vin-is less than-1/4 VREF, the output di,1 equals 0 and di,0 equals 0.

If the input signal Vin + -Vin-is greater than-1/4 VREF and less than +1/4VREF, then the output di,1 is 0, di,0 is 1;

if the input signal Vin + -Vin-is greater than +1/4VREF, the output di,1 equals 1, di,0 equals 0;

the first analog-to-digital conversion unit comprises a first-stage preamplifier A1, a second-stage preamplifier A2, a third-stage amplifier A3 and a first latch G1 which are electrically connected in sequence, and the first-stage preamplifier A1 and the second-stage preamplifier A2 are both electrically connected

Phase, third stage amplifier A3 electrical connection

Phase.

The second analog-to-digital conversion unit comprises a fourth-stage preamplifier A4, a fifth-stage preamplifier A5, a sixth-stage amplifier A6, a second latch G2, a first NAND gate and a first NOT gate which are electrically connected in sequence, the other input end of the first NAND gate is connected with the output end of the first latch G1, and the fourth-stage preamplifier A4 and the fifth-stage preamplifier A5 are electrically connected

The phase, sixth stage amplifier A6 is electrically connected

Phase.

The first stage preamplifier A1 and the second stage preamplifier A2 are used for comparing input signals to obtain a preliminary result, the voltage difference value is small, and the preliminary result is controlled by the clock circuit module

Is in phase conduction at

The phase is off. The third stage amplifier A3 is a digital amplifier for directly converting the pre-amplified result of the previous stage into 1 and 0, and is controlled by the clock control module

Is in phase conduction at

The phase is off. Finally, the 1 and 0 signals amplified by three stages are input to the first latch G1 to be latched and output. Similarly, the fourth stage preamplifier A4 and the fifth stage preamplifier A5 are at

Is in phase conduction at

Phase off, make preliminary comparison, sixth stage amplifier A6 at

Is in phase conduction at

The phase is closed, the result of the pre-amplification of the previous stage is directly converted into 1 and 0, and finally the 1 and 0 signals after the three-stage amplification are latched and output through the second latch G2. Wherein d is_1,0Representing the high order bits of the first stage binary output (d1), d_1,1Representing the low order bits of the first stage binary output (d 1).

As shown in fig. 2, the second quantization module 3 illustratively includes:

the second analog-to-digital converter 31 is electrically connected with the clock module 1 and the first quantization module 2, is configured to be triggered by the phase signal to be switched on or switched off, determines a first reference level according to the first quantization signal, and compares the first amplified signal with the first reference level to obtain a second quantization signal;

and the first digital-to-analog converter 32 is electrically connected with the second analog-to-digital converter 31 and the first quantization module 2, and is configured to amplify the first amplified signal to obtain a second amplified signal.

In the embodiment of the application, a first reference level is determined according to a first quantized signal through a second analog-to-digital converter, and a first amplified signal generated by a first quantization module is compared with the first reference level to obtain a second quantized signal; and the first digital-to-analog converter is used for amplifying the first amplified signal generated by the first quantization module to obtain a second amplified signal for the subsequent analog-to-digital converter to use.

Fig. 4 is a circuit diagram of a second analog-to-digital converter of the analog-to-digital conversion circuit provided in the embodiment of the present application, and as shown in fig. 4, the second analog-to-digital converter 31 exemplarily includes:

a first level selection unit 311 electrically connected to the first quantization module 2, and configured to determine a fifth reference voltage, a sixth reference voltage, a seventh reference voltage, and an eighth reference voltage according to the first quantization signal;

a third analog-to-digital conversion unit 312, electrically connected to the first level selection unit 311 and the clock module 1, and configured to be triggered by the phase signal to turn on or off itself, and compare the first amplified signal with a difference between the fifth reference voltage and the sixth reference voltage to obtain a high value of the second quantized signal;

and a fourth analog-to-digital conversion unit 313, electrically connected to the first level selection unit 311 and the clock module 1, configured to be triggered by the phase signal to turn on or off itself, compare the first amplified signal with a difference between the seventh reference voltage and the eighth reference voltage, and obtain a low value of the second quantized signal by combining a high value of the second quantized signal.

In the embodiment of the present application, the third analog-to-digital conversion unit includes a seventh-stage preamplifier a7, an eighth-stage preamplifier A8, a ninth-stage amplifier a9, and a third latch G3, which are electrically connected in sequence, and the seventh-stage preamplifier a7 and the eighth-stage preamplifier A8 are electrically connected

The phase, ninth stage amplifier A9 is electrically connected

Phase.

The fourth analog-to-digital conversion unit comprises a tenth-stage preamplifier A10, an eleventh-stage preamplifier A11, a twelfth-stage amplifier A12, a fourth latch G4, a second NAND gate and a second NOT gate which are electrically connected in sequence, the other input end of the second NAND gate is connected with the output end of the fourth latch G4, and the tenth-stage preamplifier A10 and the eleventh-stage preamplifier A11 are electrically connected

The phase, twelfth stage amplifier A12 is electrically connected

Phase.

The seventh stage of preamplifier A7 and the eighth stage of preamplifier A8 are used for comparing input signals to obtain a preliminary result, the voltage difference value is small, and the voltage difference value is controlled by the clock circuit module

Is in phase conduction at

The phase is off. The ninth-stage amplifier A9 is a digital amplifier for directly converting the pre-amplified result of the previous stage into 1 and 0, and is controlled by the clock control module

Is in phase conduction at

The phase is off. Finally, the three-stage amplified 1 and 0 signals are input into a third latch G3 to be latched and output. Similarly, the tenth stage preamplifier a10 and the eleventh stage preamplifier a11 are at

Is in phase conduction at

Phase off, make preliminary comparison, twelfth stage amplifier A12 at

Is in phase conduction at

The phase is closed, the result of the pre-amplification of the previous stage is directly converted into 1 and 0, and finally the 1 and 0 signals after the three-stage amplification are latched and output through a fourth latch G4. d_i,0Representing the high order of the i-th binary output (di), d_,i,1Representing the low order bits of the i-th level binary output (di).

When the input quantized signal di-1 is 00, VREF1, VREF2, VREF3, and VREF4 are respectively: 1.0625V, 1.4375V, 1.5625V, 0.9375V (if 1.25V is considered 0Vref, 2.25V is considered 1 × Vref, and 0.25V is considered-1 Vref), then these four reference voltages may correspond to write: -3/16Vref, +3/16Vref, +5/16Vref and-5/16 Vref.

The reference voltage is VREF1-VREF 2-3/8 VREF, VREF4-VREF 3-5/8 VREF,

if the value of the input signal Vin + -Vin-is greater than-3/8 VREF, the output di,1 equals 1, di,0 equals 0; i.e., di 2;

if the value of the input signal Vin + -Vin-is less than-5/8 VREF, the output di,1 equals 0, di,0 equals 0, i.e., di equals 0;

otherwise, the output di,1 equals 0, di,0 equals 1, i.e., di equals 1.

When the input quantized signal di-1 is 01, VREF1, VREF2, VREF3, and VREF4 are respectively: 1.3125V, 1.1875V, 1.3125V, 1.1875V, these four reference voltages can be written as: +1/16VREF, -1/16VREF, +1/16VREF, -1/16VREF, with a differential voltage of VREF1-VREF2 ═ 1/8VREF, VREF4-VREF3 ═ -1/8 VREF;

if the value of the input signal Vin + -Vin-is greater than +1/8VREF, the output di,1 equals 1, di,0 equals 0, i.e., di equals 2;

if the value of the input signal Vin + -Vin-is less than-1/8 VREF, the output di,1 equals 0, di,0 equals 0, i.e., di equals 0;

otherwise, the output di,1 equals 0, di,0 equals 1, i.e., di equals 1.

When the input quantized signal di-1 is equal to 10, VREF1, VREF2, VREF3, and VREF4 are respectively: 1.5625V, 0.9375V, 1.0625V, 1.4375V, these four reference voltages can be written as: +5/16VREF, -3/16VREF, -3/16VREF and +3/16VREF, wherein the differential voltage is VREF1-VREF2 ═ 5/8VREF, and VREF4-VREF3 ═ 3/8 VREF;

if the value of the input signal Vin + -Vin-is greater than +5/8VREF, the output di,1 equals 1, di,0 equals 0, i.e., di equals 2;

if the value of the input signal Vin + -Vin-is less than +3/8VREF, the output di,1 equals 0, di,0 equals 0, i.e., di equals 0;

otherwise, the output di,1 equals 0, di,0 equals 1, i.e., di equals 1.

The comparator reference voltage of the middle stage is selected from three levels of +1/8VREF and-1/8 VREF, -5/8VREF and-3/VREF, 5/8VREF and 3/8VREF, and the difference between the two levels is 1/4VREF, so that compared with the situation that all the traditional comparator reference voltages are +1/4VREF and-1/4 VREF, the difference between the two levels is 1/2VREF, the reference voltage range of the comparator is reduced, the offset error of the comparator can be reduced, and the comparison precision is improved.

Fig. 5 is a circuit diagram of a first digital-to-analog converter of the analog-to-digital conversion circuit provided in the embodiment of the present application, as shown in fig. 5, for example, the first digital-to-analog converter 32 may include:

a first logic control unit 321, electrically connected to the second analog-to-digital converter 32 and the first quantization module 2, configured to determine a first control signal according to the first quantization signal;

the second amplifier 322 is electrically connected to the first logic control unit 321, and configured to amplify the first amplified signal according to the first control signal to obtain a second amplified signal.

In the embodiment of the application, the first logic control unit determines a corresponding first control signal according to a first quantization signal output by the first quantization module, and the second amplifier performs corresponding amplification processing on the first amplified signal according to the first control signal to obtain a second amplified signal. The circuit structure of the second digital-to-analog converter is the same as that of the first digital-to-analog converter.

When the first quantization signal of the previous stage comparison module (for example, the first analog-to-digital converter in the first quantization module) is 00, the operation formula of the stage circuit is VOUT-VIN ═ 2(VIN + -VIN-) + VREF, and first, in the sampling phase, the switch 434, the switch 435, the switch 437, the switch 431, and the switch 432 are opened, and the switch 436, the switch 438, and the switch 433 are closed. Then, in the holding phase, the switch 434, the switch 436, the switch 437, the switch 438, the switch 432, and the switch 433 are opened, and the switch 435 and the switch 431 are closed. The circuit structure connected with the anode of the second amplifier is the same as the circuit structure connected with the cathode of the second amplifier, and the switching modes are the same, so that a differential structure is formed. VOUT — VIN ═ 2(VIN + — VIN-) + VREF is calculated from the principle of conservation of charge, where VREF ═ VREF + — VREF-.

If the first quantization signal of the previous stage comparison module (e.g. the first adc in the first quantization module) is 01, the operation formula of the stage circuit is VOUT-VIN-2 (VIN + -VIN-). First, in the sampling phase, the switches 434, 435, 437, 431, and 432 are opened, and the switches 436, 438, and 433 are closed. Then, in the holding phase, the switch 434, the switch 435, the switch 436, the switch 431, the switch 438, and the switch 433 are opened, and the switch 437 and the switch 432 are closed. The circuit structure connected with the anode of the second amplifier is the same as the circuit structure connected with the cathode of the second amplifier, and the switching modes are the same, so that a differential structure is formed. VOUT-VIN-2 (VIN + -VIN-) is calculated according to the principle of conservation of charge.

If the first quantization signal of the previous stage comparison module (e.g. the first analog-to-digital converter in the first quantization module) is 10, the operational formula of the stage circuit is VOUT-VIN-2 (VIN + -VIN-) -VREF. First, in the sampling phase, the switches 434, 435, 437, 431, and 432 are opened, and the switches 436, 438, and 433 are closed. Then, in the holding phase, the switch 432, the switch 435, the switch 436, the switch 437, the switch 438, and the switch 433 are opened, and the switch 434 and the switch 431 are closed. The circuit structure connected with the anode of the second amplifier is the same as the circuit structure connected with the cathode of the second amplifier, and the switching modes are the same, so that a differential structure is formed. VOUT-VIN-2 (VIN + -VIN-) -VREF is calculated according to the principle of conservation of charge.

As shown in fig. 2, the third quantization module 4 illustratively includes:

the third analog-to-digital converter 41 is electrically connected with the clock module 1 and the second quantization module 3, and is configured to be triggered by the phase signal to be switched on or switched off, determine a second reference level according to the second quantization signal, and compare the second amplified signal with the second reference level to obtain a third quantization signal;

and the second digital-to-analog converter 42 is electrically connected with the third analog-to-digital converter 41 and the second quantization module 3, and is configured to amplify the second amplified signal to obtain a third amplified signal.

In the embodiment of the application, a second reference level is determined according to the second quantized signal through a third analog-to-digital converter, and a second amplified signal generated by the second quantization module is compared with the second reference level to obtain a third quantized signal; and amplifying the second amplified signal generated by the second quantization module through a second digital-to-analog converter to obtain a third amplified signal for use by a subsequent analog-to-digital converter.

As shown in fig. 2, the fourth quantization module 5 exemplarily includes a fourth analog-to-digital converter 51, electrically connected to the clock module 1 and the third quantization module 4, and configured to be triggered by the phase signal to turn on or off itself, determine a third reference level according to the third quantization signal, and compare the third amplified signal with the third reference level to obtain a fourth quantization signal.

In the embodiment of the present application, a fourth analog-to-digital converter determines a corresponding third reference level according to the third quantized signal, and compares the third amplified signal with the third reference level to obtain a fourth quantized signal.

Fig. 6 is a circuit diagram of a fourth analog-to-digital converter of the analog-to-digital conversion circuit provided in the embodiment of the present application, and as shown in fig. 6, the fourth analog-to-digital converter 51 includes:

a second level selection unit 511 electrically connected to the third quantization module 4, and configured to determine a ninth reference voltage, a tenth reference voltage, an eleventh reference voltage, a twelfth reference voltage, a thirteenth reference voltage, and a fourteenth reference voltage according to the third quantization signal;

a fifth analog-to-digital conversion unit 512 electrically connected to the second level selection unit 511 and the clock module 1, and configured to be triggered by the phase signal to turn on or off itself, and compare the third amplified signal with a difference between the ninth reference voltage and the tenth reference voltage to obtain a high value of a fourth quantized signal;

a sixth analog-to-digital conversion unit 513, electrically connected to the second level selection unit 511 and the clock module 1, configured to be triggered by the phase signal to turn on or off itself, compare the third amplified signal with a difference between an eleventh reference voltage and a twelfth reference voltage, and obtain a first bit value of the fourth quantized signal by combining a high bit value of the fourth quantized signal;

and a seventh analog-to-digital conversion unit 514 electrically connected to the second level selection unit 511 and the clock module 1, configured to be triggered by the phase signal to turn on or off itself, compare the third amplified signal with a difference between a thirteenth reference voltage and a fourteenth reference voltage, and obtain a low value of the fourth quantized signal by combining a high value of the fourth quantized signal and a second value of the fourth quantized signal.

In the embodiment of the present application, the fifth analog-to-digital conversion unit includes a thirteenth-stage preamplifier a13, a fourteenth-stage preamplifier a14, a fifteenth-stage amplifier a15, and a fifth latch G5 electrically connected in sequence, and each of the thirteenth-stage preamplifier a13 and the fourteenth-stage preamplifier a14 is electrically connected

The phase, fifteenth stage amplifier A15 is electrically connected

Phase.

The sixth analog-to-digital conversion unit comprises a sixteenth-stage preamplifier A16, a seventeenth-stage preamplifier A17, an eighteenth-stage amplifier A18 and a sixth lock which are electrically connected in sequenceThe other input end of the third NAND gate is connected with the output end of the sixth latch G6, and the sixteenth-stage preamplifier A16 and the seventeenth-stage preamplifier A17 are electrically connected

The phase, eighteenth stage amplifier A18 is electrically connected

Phase.

The seventh analog-to-digital conversion unit comprises a nineteenth-stage preamplifier A19, a twentieth-stage preamplifier A20, a twenty-first-stage amplifier A21, a seventh latch G7 and a fourth NAND gate which are electrically connected in sequence, the other input end of the fourth NAND gate is connected with the output end of the seventh latch G7, the fifth analog-to-digital conversion unit further comprises a fifth NAND gate, and the input end of the fifth NAND gate is connected with the output end of the third NAND gate and the output end of the fourth NAND gate. The nineteenth-stage preamplifier A19 and the twentieth-stage preamplifier A20 are both electrically connected

Phase, twentieth amplifier A21 is electrically connected

Phase.

The thirteenth pre-amplifier A13 and the fourteenth pre-amplifier A14 are used for comparing the input signals to obtain a preliminary result, the voltage difference value is small, and the control is performed by the clock circuit module

Is in phase conduction at

The phase is off. The fifteenth stage amplifier A15 is a digital amplifier for directly converting the pre-amplified result of the previous stage into 1 and 0, and is controlled by the clock control module

Is in phase conduction at

The phase is off. Finally, the three-stage amplified 1 and 0 signals are input to a fifth latch G5 for latching and output. Similarly, the sixteenth preamplifier A16 and the seventeenth preamplifier A17 are at

Is in phase conduction at

Phase off, make preliminary comparison, eighteenth stage amplifier A18 at

Is in phase conduction at

The phase is closed, the result of the pre-amplification of the previous stage is directly converted into 1 and 0, and finally the 1 and 0 signals after the three-stage amplification are latched and output through a sixth latch G6. Similarly, the nineteenth and twentieth stages of preamplifiers A19, A20 are at

Is in phase conduction at

Phase off, make preliminary comparison, twenty-first amplifier a21 at

Is in phase conduction at

The phase is closed, the result of the pre-amplification of the previous stage is directly converted into 1 and 0, and finally the 1 and 0 signals after the three-stage amplification are latched and output through a seventh latch G7. d_i,0Representing the high order of the i-th binary output (di), d_,i,1Represents the ith stage binary output (di) is lower.

When the input quantization signal di-1 is 00, the reference voltage circuit output voltages VREF1, VREF2, VREF3, VREF4, VREF5, VREF6 are 1.375V, 1.125V, 1.5V, 1V, 1.625V, 0.875V, respectively. (if 1.25V is considered 0Vref, 2.25V is considered 1 × Vref, 0.25V is considered-1 Vref), then these six (single-ended) reference voltages can be written as: -1/8VREF, -1/8VREF, +1/4VREF, -1/4VREF, +3/8VREF, -3/8VREF, and the three differential voltages are VREF2-VREF 1-1/4 VREF, VREF4-VREF 3-1/2 VREF, and VREF6-VREF 5-3/4 VREF;

if the value of the input signal Vin + -Vin-is less than-3/4 VREF, the output di,1 equals 0, di,0 equals 0, i.e., di equals 0;

if the value of the input signal Vin + -Vin-is between-3/4 VREF and-1/2 VREF, the output di,1 equals 0, di,0 equals 1, i.e., di equals 1;

if the value of the input signal Vin + -Vin-is between-1/2 VREF and-1/4 VREF, the output di,1 equals 1, di,0 equals 0, i.e., di equals 2;

otherwise, the output di,1 equals 1, di,0 equals 1, i.e., di equals 3.

When the input quantization signal di-1 is 01, the reference voltage circuit output voltages VREF1, VREF2, VREF3, VREF4, VREF5, and VREF6 are 1.125V, 1.375V, 1.25V, 1.375V, and 1.125V, respectively. (if 1.25V is considered 0Vref, 2.25V is considered 1 × Vref, and 0.25V is considered-1 Vref), then these six reference voltages can be written as: -1/8VREF, +1/8VREF, 0, +1/8VREF, -1/8 VREF. The three differential voltages are VREF2-VREF 1-1/4 VREF, VREF4-VREF 3-0, VREF6-VREF 5-1/4 VREF;

if the value of the input signal Vin + -Vin-is less than-1/4 VREF, the output di,1 equals 0, di,0 equals 0, i.e., di equals 0;

if the value of the input signal Vin + -Vin-is between-1/4 VREF and 0VREF, the output di,1 equals 0, di,0 equals 1, i.e., di equals 1;

if the value of the input signal Vin + -Vin-is between 0VREF and 1/4VREF, the output di,1 equals 1, di,0 equals 0, i.e., di equals 2;

otherwise, the output di,1 equals 1, di,0 equals 1, i.e., di equals 3.

When the input quantization signal di-1 is 10, the reference voltage circuit output voltages VREF1, VREF2, VREF3, VREF4, VREF5, and VREF6 are 0.875V, 1.625V, 1V, 1.5V, 1.125V, and 1.375V, respectively. (if 1.25V is considered 0, 2.25V is considered 1VREF, and 0.25V is considered-1 VREF), then these six reference voltages can be written as: -3/8VREF, 3/8VREF, -1/4VREF, +1/4VREF, -1/8VREF, +1/8 VREF. The three differential voltages are VREF2-VREF1 ═ +3/4VREF, VREF4-VREF3 ═ 1/2VREF, and VREF6-VREF5 ═ 1/4 VREF;

if the value of the input signal Vin + -Vin-is less than +1/4VREF, the output di,1 equals 0, di,0 equals 0, i.e., di equals 0;

if the value of the input signal Vin + -Vin-is between +1/4VREF and +1/2VREF, the output di,1 equals 0, di,0 equals 1, i.e., di equals 1;

if the value of the input signal Vin + -Vin-is between +1/2VREF and +3/4VREF, the output di,1 equals 1, di,0 equals 0, i.e., di equals 2;

otherwise, the output di,1 equals 1, di,0 equals 1, i.e., di equals 3.

In application, taking an N-bit ADC as an example, the first quantization module and the 2 nd to N-1 th quantization modules, the nth quantization module operates as follows:

a first quantization module: the differential levels are fixed at +1/4VREF and-1/4 VREF, consistent with conventional pipeline voltages.

Fig. 7 is a quantization diagram of the 2 nd to N-1 th quantization modules of the analog-to-digital conversion circuit according to the embodiment of the present application, and as shown in fig. 7, the 2 nd to N-1 th quantization modules: the reference level is adjusted according to the comparison result of the previous stage, if the previous stage outputs 01, the +1/8VREF and-1/8 VREF are used as the (differential) reference level of the current stage comparison module; if the previous stage outputs 00, using-3/8 VREF and-5/8 VREF as the (differential) reference level of the current stage comparison module; if the previous stage outputs 10, the +5/8VREF and +3/8VREF are used as the (differential) reference levels of the current stage comparison module.

Fig. 8 is a quantization diagram of an nth quantization module of an analog-to-digital conversion circuit according to an embodiment of the present application, where as shown in fig. 8, the nth quantization module: the reference level is adjusted according to the comparison result of the previous stage, and if the previous stage outputs 01, the reference level is determined to be the (differential) reference level of the sub-quantization module N by using ± 1/4VREF and 0; if the previous stage outputs 00, using-3/4 VREF and-1/2 VREF and-1/4 VREF as the (differential) reference levels of the sub-quantization module N; if the previous stage outputs 10, the +3/4VREF and the +1/2VREF and the +1/4VREF are used as (differential) reference levels of the sub-quantization module N.

Fig. 9 is a schematic diagram of five-bit analog-to-digital conversion and quantization of an analog-to-digital conversion circuit provided in the embodiment of the present application, as shown in fig. 9, taking an input signal of-439 mV as an example to illustrate a calculation process,

1) an input signal of-439 mV enters a first quantization module, and the-439 mV outputs Vr according to a ratio of 1:1 after passing through a first amplifier, wherein 1 is-439 mV; -439mV is less than 1/4VREF, so the output d1 is 00;

2) 439mV as input to a second quantization module, the residual output V of the second quantization module_r,2＝2V_in-(d₁-1)V_R2 (-439) mV +1000 mV-122 mV; since d1 is 00, the comparison levels of the sub-adc in the sub-quantization module 2 are-5/8 VR and-3/8 VR, and since-439 mV is greater than-5/8 VR and less than-3/8 VR, the output d2 is 01;

3)122mV as input to a third quantization module, the residual output V of which_r,2＝2V_in-(d₂-1)V_R122 mV-244 mV; since d2 is 01, the comparison levels are-1/8 Vr and 1/8Vr, 122mV is less than 1/8Vr and greater than-1/8 Vr, and the output d3 is 01;

4)244mV is used as the input of the fourth quantization module in the last stage, since d3 is 01, the comparison levels are-1/4 VR, 0 and 1/4VR, 244mV is smaller than 1/4VR and larger than 0, so d4 is 10;

5) as shown in table 2, d1, d2, d3 and d4 are added by the delay alignment module to obtain final outputs b4, b3, b2, b1, and b0 being 01000.

TABLE 2 delay-aligned-addition tables for d1, d2, d3, d4 with-439 mV as input signal

0	0
						0	1
		0	1
								1	0
+
					0	1	0	0	0

A transceiver system may illustratively include analog-to-digital conversion circuitry.

In the embodiment of the application, the analog-to-digital conversion circuit is arranged in the transceiving system, so that the transceiving system replaces a sample-and-hold circuit and a first-stage sub-quantization circuit in a traditional pipeline analog-to-digital conversion circuit through the first quantization module, not only can an input signal be sampled, but also a first quantization signal can be output, thereby simplifying the quantization process and reducing the power consumption.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing embodiments, and are not described herein again.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed analog-to-digital conversion circuit may be implemented in other ways. For example, the above-described embodiments of analog-to-digital conversion circuits are merely illustrative, and for example, the division of the modules or units is only one logical function division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication electric connection may be an indirect coupling or communication electric connection of some interfaces, devices or units, and may be in an electric, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (10)

1. An analog-to-digital conversion circuit, comprising:

a clock module configured to generate a phase signal;

the first quantization module is electrically connected with the clock module and is configured to be triggered to be switched on or switched off by the phase signal, amplify an input signal to obtain a first amplified signal and compare the input signal with a fixed level to obtain a first quantized signal;

the second quantization module is electrically connected with the clock module and the first quantization module, and is configured to be triggered by the phase signal to be switched on or switched off, amplify the first amplified signal to obtain a second amplified signal, determine a first reference level according to the first quantized signal, and compare the first amplified signal with the first reference level to obtain a second quantized signal;

the third quantization module is electrically connected with the clock module and the second quantization module, and is configured to be triggered by the phase signal to be switched on or switched off, amplify the second amplified signal to obtain a third amplified signal, determine a second reference level according to the second quantized signal, and compare the second amplified signal with the second reference level to obtain a third quantized signal;

the fourth quantization module is electrically connected with the clock module and the third quantization module, is configured to be triggered to be switched on or switched off by the phase signal, determines a third reference level according to the third quantization signal, and compares the third amplified signal with the third reference level to obtain a fourth quantization signal;

a delay alignment module electrically connected to the first quantization module, the second quantization module, the third quantization module and the fourth quantization module, and configured to delay align and add the first quantized signal, the second quantized signal, the third quantized signal and the fourth quantized signal to obtain a final analog-to-digital conversion value.

2. The analog-to-digital conversion circuit of claim 1, wherein the first quantization module comprises:

the first analog-to-digital converter is electrically connected with the clock module and is configured to be triggered to be switched on or switched off by the phase signal, and the input signal is compared with the fixed level to obtain a first quantized signal;

the first amplifier is electrically connected with the first analog-to-digital converter and is configured to amplify the input signal to obtain a first amplified signal.

3. The analog-to-digital conversion circuit of claim 2, wherein the first analog-to-digital converter comprises:

a fixed level generating unit configured to generate a first reference voltage, a second reference voltage, a third reference voltage, and a fourth reference voltage;

the first analog-to-digital conversion unit is electrically connected with the fixed level generation unit and the clock module and is configured to be triggered by the phase signal to be switched on or switched off, and the input signal is compared with the difference value between the first reference voltage and the second reference voltage to obtain the high value of the first quantized signal;

and the second analog-to-digital conversion unit is electrically connected with the fixed level generation unit and the clock module, is configured to be triggered by the phase signal to be switched on or switched off, compares the input signal with the difference value of the third reference voltage and the fourth reference voltage, and obtains the low value of the first quantized signal by combining the high value of the first quantized signal.

4. The analog-to-digital conversion circuit of claim 1, wherein the second quantization module comprises:

the second analog-to-digital converter is electrically connected with the clock module and the first quantization module, is configured to be triggered by the phase signal to be switched on or switched off, determines a first reference level according to the first quantization signal, and compares the first amplified signal with the first reference level to obtain a second quantization signal;

the first digital-to-analog converter is electrically connected with the second analog-to-digital converter and the first quantization module and is configured to amplify the first amplified signal to obtain a second amplified signal.

5. The analog-to-digital conversion circuit of claim 4, wherein the second analog-to-digital converter comprises:

a first level selection unit electrically connected to the first quantization module and configured to determine a fifth reference voltage, a sixth reference voltage, a seventh reference voltage and an eighth reference voltage according to a first quantization signal;

a third analog-to-digital conversion unit electrically connected to the first level selection unit and the clock module, and configured to be triggered by the phase signal to turn on or off, and compare the first amplified signal with a difference between the fifth reference voltage and the sixth reference voltage to obtain a high value of the second quantized signal;

and the fourth analog-to-digital conversion unit is electrically connected with the first level selection unit and the clock module, is configured to be triggered by the phase signal to be switched on or switched off, compares the first amplified signal with a difference value between the seventh reference voltage and the eighth reference voltage, and obtains a low value of the second quantized signal by combining a high value of the second quantized signal.

6. The analog-to-digital conversion circuit of claim 4, wherein the first digital-to-analog converter comprises:

a first logic control unit electrically connected with the second analog-to-digital converter and the first quantization module and configured to determine a first control signal according to the first quantization signal;

the second amplifier is electrically connected with the first logic control unit and is configured to amplify the first amplified signal according to the first control signal to obtain a second amplified signal.

7. The analog-to-digital conversion circuit of claim 1, wherein the third quantization module comprises:

the third analog-to-digital converter is electrically connected with the clock module and the second quantization module, is configured to be triggered by the phase signal to be switched on or switched off, determines a second reference level according to the second quantization signal, and compares the second amplified signal with the second reference level to obtain a third quantization signal;

and the second digital-to-analog converter is electrically connected with the third analog-to-digital converter and the second quantization module and is configured to amplify the second amplified signal to obtain a third amplified signal.

8. The analog-to-digital conversion circuit of claim 1, wherein the fourth quantization module comprises a fourth analog-to-digital converter electrically connected to the clock module and the third quantization module, and configured to be turned on or off by the phase signal, determine a third reference level according to the third quantization signal, and compare the third amplified signal with the third reference level to obtain a fourth quantization signal.

9. The analog-to-digital conversion circuit of claim 8, wherein the fourth analog-to-digital converter comprises:

a second level selection unit electrically connected to the third quantization module and configured to determine a ninth reference voltage, a tenth reference voltage, an eleventh reference voltage, a twelfth reference voltage, a thirteenth reference voltage and a fourteenth reference voltage according to a third quantization signal;

a fifth analog-to-digital conversion unit electrically connected to the second level selection unit and the clock module, and configured to be triggered by the phase signal to turn on or off, and compare the third amplified signal with a difference between the ninth reference voltage and the tenth reference voltage to obtain a high value of the fourth quantized signal;

a sixth analog-to-digital conversion unit electrically connected to the second level selection unit and the clock module, and configured to be triggered by the phase signal to turn on or off, compare the third amplified signal with a difference between the eleventh reference voltage and the twelfth reference voltage, and obtain a first bit value of the fourth quantized signal by combining a high bit value of the fourth quantized signal;

a seventh analog-to-digital conversion unit electrically connected to the second level selection unit and the clock module, and configured to be triggered by the phase signal to turn on or off, compare the third amplified signal with a difference between the thirteenth reference voltage and the fourteenth reference voltage, and then combine a high value of the fourth quantized signal and a second value of the fourth quantized signal to obtain a low value of the fourth quantized signal.

10. A transceiver system comprising an analog-to-digital conversion circuit according to any one of claims 1 to 9.

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