CN112489712A - EEPROM programming period control circuit - Google Patents
EEPROM programming period control circuit Download PDFInfo
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- CN112489712A CN112489712A CN202011515635.7A CN202011515635A CN112489712A CN 112489712 A CN112489712 A CN 112489712A CN 202011515635 A CN202011515635 A CN 202011515635A CN 112489712 A CN112489712 A CN 112489712A
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- nmos tube
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- nmos
- gate
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention belongs to the field of EEPROM control systems, and particularly relates to a timing circuit system provided by a micro-current source. The device comprises a reference voltage source, a micro-current source and a timing circuit; the reference voltage source provides voltage bias for the micro-current source, which is irrelevant to temperature and power supply; the micro-current source provides pA level current for the timing circuit; the timing circuit realizes ms-level timing by pF-level capacitor. The invention realizes EEPROM erasing and programming time control by using a very simple circuit structure. The time produced by the invention has little change with temperature. The invention relates to less resources.
Description
Technical Field
The invention belongs to the field of EEPROM control systems, and particularly relates to a timing circuit system provided by a micro-current source.
Background
Currently, digital storage technologies are mainly divided into three types: magnetic, photoelectric, and semiconductor types. The semiconductor memory technology is basically divided into two types, namely Volatile (voltate) and Non-Volatile (Non-voltate), and the Volatile memory technology is mature and is also the mainstream of the current semiconductor memory technology, including DRAM, SRAM and the like; non-volatile memory technologies include mask ROM, EPROM, EEPROM, Flash, and the emerging FRAM (ferroelectric memory), MRAM (magnetic memory), and OUM (phase change memory), among others. The characteristics of non-volatility, high access speed, low cost, simple manufacturing process, high data storage density, low power consumption, unlimited erasing and the like are essential points of future memory technology.
The EEPROM unit needs a time period of ms magnitude for programming and erasing, the prior art is composed of a time base circuit and a frequency dividing circuit (a timing circuit), the time base circuit generates a clock signal, the frequency dividing circuit divides the frequency of the clock signal to complete timing, and when the timing period is longer, larger capacitors, larger resistors and more frequency dividers are needed. If the ms-level timing is realized, about 500 transistors are needed for the whole function, the on-chip capacitance is about 6pF, and the resistance is 50K omega. Although the prior art can realize accurate control on erasing and programming time, the needed resources are very much, and the more time is needed for programming, the more resources are needed.
Disclosure of Invention
The invention provides a timing circuit with a simple structure, which only needs less than 100 transistors, an on-chip capacitor 12p and an on-chip large resistor on the premise of providing ms-level timing. The invention aims to provide a control circuit for EEPROM erasing and programming time, which has stable performance, small volume and low cost.
The technical scheme adopted by the invention for realizing the purpose is as follows:
an EEPROM programming cycle control circuit comprising: a reference voltage source, a micro-current source and a timing circuit,
wherein:
the reference voltage source is used for providing reference voltage for the micro current source;
the micro-current source is used for providing reference current for the timing circuit according to the reference voltage;
and the timing circuit is used for realizing timing according to the reference current and the capacitor.
The reference current is pA level.
The capacitance is of the pF class.
The timing circuit completes ms-level timing.
The circuit of the micro-current source is as follows:
the reference voltage VREF is respectively input to a gate of the NMOS tube MN01, a gate of the NMOS tube MN02, a gate of the NMOS tube MN03, a gate of the NMOS tube MN04, a gate of the NMOS tube MN05, and a gate of the NMOS tube MN06, a source of the NMOS tube MN01 is connected to a drain of the NMOS tube MN02, a source of the NMOS tube MN02 is connected to a drain of the NMOS tube MN03, a source of the NMOS tube MN03 is grounded, a drain of the NMOS tube MN03 is connected to a drain of the PMOS tube MP03, a gate of the PMOS tube MP03 is connected to a control signal CON, a source of the PMOS tube MP03 is respectively connected to a source of the PMOS tube MP03 and a gate of the PMOS tube MP03, a drain of the PMOS tube MP03 is connected to a drain of the NMOS tube MN03, a drain of the PMOS tube MN03, and a drain of the NMOS tube MN03 are respectively connected to a drain of the NMOS tube MN03, and a drain of the PMOS, the gate of the NMOS transistor MN07 outputs the reference current IREF, and the source of the NMOS transistor MN07 is grounded.
The timing circuit is as follows:
the reference current IREF is input to a gate of the NMOS tube MN13, a source of the NMOS tube MN13 is grounded, a drain of the NMOS tube MN13 is connected to a source of the NMOS tube MN12, a drain of the NMOS tube MN12 is connected to a source of the NMOS tube MN11 and a drain and a gate of the NMOS tube MN15 through a capacitor CAP1, a gate of the NMOS tube MN11 is connected to the feedback signal CON2, a drain of the NMOS tube MN11 is connected to the power supply VPP, a source of the NMOS tube MN15 is connected to a drain and a gate of the NMOS tube MN16, a source of the NMOS tube MN16 is connected to a drain and a gate of the NMOS tube MN17, a source of the NMOS tube MN17 is connected to a drain of the NMOS tube MN18, a gate of the NMOS tube MN18 is connected to the feedback signal CON2, a source of the NMOS tube MN18 is grounded, a drain of the NMOS tube MN14 is connected to a drain of the NMOS tube MN12, a gate of the NMOS tube MN12 is connected to the power supply VDD, and is used as an output of the NMOS.
The invention has the following beneficial effects and advantages:
1. the invention realizes EEPROM erasing and programming time control by using a very simple circuit structure.
2. The time produced by the invention has little change with temperature.
3. The invention relates to less resources.
Drawings
FIG. 1 is a system framework of the present invention;
wherein, 1 is a reference voltage source, 2 is a micro-current source, and 3 is a timing circuit;
FIG. 2 is a schematic diagram of the micro-current source circuit of the present invention;
FIG. 3 is a circuit diagram of the timing circuit of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
As shown in figure 1, the invention is a timing circuit provided by a micro-current source (2) and used for controlling the programming time of an EEPROM, comprising a reference voltage source (1), the micro-current source (2) and a timing circuit (3); the reference voltage source (1) provides voltage bias irrelevant to temperature and power supply for the micro-current source (2); the reference voltage source adopts a traditional band gap reference and provides reference voltage irrelevant to power supply voltage and temperature, and the value of the reference voltage is about 1.2V; the micro-current source (2) provides pA level current for the timing circuit (3); the timing circuit realizes ms-level timing by pF-level capacitor.
The reference voltage source (1) adopts a classical band-gap reference structure and provides a reference voltage which is irrelevant to the power voltage and the temperature for the micro-current source (2).
As shown in fig. 2, the micro-current source (2) circuit is specifically described: the grid of the first PMOS device (MP01) is connected with the grid of the first PMOS device (MP01) and the grid of the second PMOS device (MP02) are connected with the source of the third PMOS device (MP03) and the substrate of the third PMOS device (MP03), the source of the first PMOS device (MP01) is connected with the power supply, the substrate of the first PMOS device (MP01) is connected with the power supply, the source of the second PMOS device (MP02) is connected with the power supply, the drain of the second PMOS device (MP02) is connected with the drain of the eighth NMOS device (MN08), the substrate of the second PMOS device (MP02) is connected with the power supply, the source of the third PMOS device (MP03) is connected with the drain of the first NMOS device (MN01), and the grid of the third PMOS device (MP03) is connected with a control signal (CON); the gates of the first and second NMOS devices (MN01, MN02, MN04, MN05, MN06) are connected to and coupled to the reference voltage VREF, the substrate of the first NMOS device (MN01), the substrate of the second NMOS device (MN02), the substrate of the third NMOS device (MN03), the substrate of the fourth NMOS device (MN04), the substrate of the fifth NMOS device (MN05), the substrate of the sixth NMOS device (MN06), the source of the first NMOS device (MN01), the drain of the second NMOS device (MN02), the source of the second NMOS device (MN02), the drain of the third NMOS device (MN03), the source of the third NMOS device (MN03), the drain of the fourth NMOS device (MN 584648), the drain of the fourth NMOS device (MN 465), the drain of the fourth NMOS device (MN04, MN 4623), the drain of the fifth NMOS device (MN 465), the drain of the fourth NMOS device (MN 4623), the drain of the NMOS device (MN 465), the drain of the first NMOS device (MN 468), the drain of the fourth NMOS device (MN 465), the drain of the fourth NMOS device (MN04), the drain of the NMOS device (MN 465), the drain of the NMOS device (MN 465), the NMOS device (MN 468), the drain of the NMOS device, The source of the sixth NMOS device (MN06) is grounded, the gate of the eighth NMOS device (MN08) is connected with the power supply VDD, the source of the eighth NMOS device (MN08), the drain of the seventh NMOS device (MN07) and the gate of the seventh NMOS device (MN07) are connected to form an output IREF, and the source of the seventh NMOS device (MN07) is grounded. The other devices in the micro-current source circuit except the eighth NMOS device (MN08) which is a NATIVE device are depletion type MOSFETs.
The control signal CON controls whether the micro-current source is started or not through the third PMOS device MP03, and when CON is connected to a high level, i.e., a power voltage, the third PMOS device MP03 is turned off, and the micro-current source is not started; when CON is connected to a low level, i.e., ground, the third PMOS device MP03 is turned on and the trickle current source is enabled. The first NMOS device MN01, the second NMOS device MN02, the third NMOS device MN03, the fourth NMOS device MN04, the fifth NMOS device MN05 and the sixth NMOS device MN06 are connected in series, the area is reduced compared with the large resistance due to the fact that the area is equivalent to the large resistance, the grids of the first NMOS device MN01, the second NMOS device MN02, the third NMOS device MN03, the fourth NMOS device MN04, the fifth NMOS device MN05 and the sixth NMOS device MN06 are in short circuit with reference voltage VREF provided by a reference voltage source (1), and the generated micro current is guaranteed to have the minimum temperature coefficient and the maximum power supply rejection ratio.
The first PMOS device MP01 and the second PMOS device MP02 form a mirror structure, and mirror micro-currents generated by the first NMOS device MN01, the second NMOS device MN02, the third NMOS device MN03, the fourth NMOS device MN04, the fifth NMOS device MN05, and the sixth NMOS device MN 06.
The seventh NMOS device MN07 and the eighth NMOS device MN08 mirror the micro current.
As shown in fig. 3, the detailed description of the timing circuit (3) circuit: the drain of the eleventh NMOS device (MN11) is connected with VPP, VPP is a high voltage output by the charge pump, the gate of the eleventh NMOS device (MN11) is connected with a control signal CON2, the source of the eleventh NMOS device (MN11) and one pole of the first CAP device (CAP1) are connected with the drain of the fifteenth NMOS device (MN15) and the gate of the fifteenth NMOS device (MN15), the substrate of the eleventh NMOS device (MN11) is grounded, the other stage of the first CAP device (CAP1) and the drain of the fourteenth NMOS device (MN14) are connected with the drain of the twelfth NMOS device (MN12), the gate of the twelfth NMOS device (MN12) is connected with a power voltage VDD, the source of the twelfth NMOS device (MN12) is connected with the drain of the thirteenth NMOS device (MN13), the micro-gate of the thirteenth NMOS device (MN13) is connected with a current source output F, the source of the thirteenth NMOS device (MN13) is grounded, the source of the thirteenth NMOS device (MN13) is connected with the drain of the fourteenth NMOS device (MN14), the source of the fourteenth NMOS device (MN14) is connected with the input of the inverter INV1, the substrate of the fourteenth NMOS device (MN14) is grounded, the output of the inverter INV1 is the timer output, the source of the fifteenth NMOS device (MN15) is connected with the drain of the sixteenth NMOS device (MN16) and the gate of the sixteenth NMOS device (MN16), the substrate of the fifteenth NMOS device (MN15) is grounded, the source of the sixteenth NMOS device (MN16) is connected to the drain of the seventeenth NMOS device (MN17) and the gate of the seventeenth NMOS device (MN17), the substrate of the sixteenth NMOS device (MN16) is grounded, the source of the seventeenth NMOS device (MN17) is connected to the drain of the eighteenth NMOS device (MN18), the substrate of the seventeenth NMOS device (MN17) is grounded, the gate of the eighteenth NMOS device (MN18) is connected to the control signal CON2, the source of the eighteenth NMOS device (MN18) is grounded, and the substrate of the eighteenth NMOS device (MN18) is grounded.
The twelfth NMOS device MN12 and the thirteenth NMOS device MN13 are the seventh NMOS device MN07 and the eighth NMOS device MN08 of the micro-current source (2);
CON2 is the overall feedback signal, and CON2 is typically high, i.e., the supply voltage. VPP is a high level used for programming and erasing EEPROM generated by a charge pump, about 14V, when VPP rises to 14V, CAP1 induces a voltage at a K1 end by using the alternating current short-circuit characteristic thereof, namely a certain charge is accumulated on CAP1, the charge of CAP1 is slowly released through a twelfth NMOS device MN12 and a thirteenth NMOS device MN13, the release time can be controlled at ms level because of micro current at a twelfth NMOS device MN12 and a thirteenth NMOS device MN13, the voltage at a K1 point is reduced to be low enough when the release time is long enough, CON2 can be triggered to turn to a low level, and the voltage at the K2 point is discharged through a fifteenth NMOS device MN15, a sixteenth NMOS device MN16, a seventeenth NMOS device MN17 and an eighteenth NMOS device MN 18. The control signal CON2 returns to high after a short low level to start timing the next period again.
Claims (6)
- An EEPROM program cycle control circuit, comprising: reference voltage source, little current source and timing circuit, wherein:the reference voltage source is used for providing reference voltage for the micro current source;the micro-current source is used for providing reference current for the timing circuit according to the reference voltage;and the timing circuit is used for realizing timing according to the reference current and the capacitor.
- 2. The EEPROM programming cycle control circuit of claim 1, wherein the reference current is pA level.
- 3. The EEPROM program cycle control circuit of claim 1, wherein the capacitor is of pF class.
- 4. The EEPROM programming cycle control circuit of claim 1, wherein the timing circuit completes ms level timing.
- 5. The EEPROM program cycle control circuit of claim 1, wherein the micro current source circuit is:the reference voltage VREF is respectively input to a gate of the NMOS tube MN01, a gate of the NMOS tube MN02, a gate of the NMOS tube MN03, a gate of the NMOS tube MN04, a gate of the NMOS tube MN05, and a gate of the NMOS tube MN06, a source of the NMOS tube MN01 is connected to a drain of the NMOS tube MN02, a source of the NMOS tube MN02 is connected to a drain of the NMOS tube MN03, a source of the NMOS tube MN03 is grounded, a drain of the NMOS tube MN03 is connected to a drain of the PMOS tube MP03, a gate of the PMOS tube MP03 is connected to a control signal CON, a source of the PMOS tube MP03 is respectively connected to a source of the PMOS tube MP03 and a gate of the PMOS tube MP03, a drain of the PMOS tube MP03 is connected to a drain of the NMOS tube MN03, a drain of the PMOS tube MN03, and a drain of the NMOS tube MN03 are respectively connected to a drain of the NMOS tube MN03, and a drain of the PMOS, the gate of the NMOS transistor MN07 outputs the reference current IREF, and the source of the NMOS transistor MN07 is grounded.
- 6. The EEPROM program cycle control circuit of claim 1, wherein the timing circuit is:the reference current IREF is input to a gate of the NMOS tube MN13, a source of the NMOS tube MN13 is grounded, a drain of the NMOS tube MN13 is connected to a source of the NMOS tube MN12, a drain of the NMOS tube MN12 is connected to a source of the NMOS tube MN11 and a drain and a gate of the NMOS tube MN15 through a capacitor CAP1, a gate of the NMOS tube MN11 is connected to the feedback signal CON2, a drain of the NMOS tube MN11 is connected to the power supply VPP, a source of the NMOS tube MN15 is connected to a drain and a gate of the NMOS tube MN16, a source of the NMOS tube MN16 is connected to a drain and a gate of the NMOS tube MN17, a source of the NMOS tube MN17 is connected to a drain of the NMOS tube MN18, a gate of the NMOS tube MN18 is connected to the feedback signal CON2, a source of the NMOS tube MN18 is grounded, a drain of the NMOS tube MN14 is connected to a drain of the NMOS tube MN12, a gate of the NMOS tube MN12 is connected to the power supply VDD, and is used as an output of the NMOS.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011515635.7A CN112489712B (en) | 2020-12-21 | 2020-12-21 | EEPROM programming cycle control circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011515635.7A CN112489712B (en) | 2020-12-21 | 2020-12-21 | EEPROM programming cycle control circuit |
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| CN112489712A true CN112489712A (en) | 2021-03-12 |
| CN112489712B CN112489712B (en) | 2023-07-18 |
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2020
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| CN104375553A (en) * | 2014-12-10 | 2015-02-25 | 中国电子科技集团公司第四十七研究所 | Bandgap reference circuit and base current compensation circuit |
| WO2017049840A1 (en) * | 2015-09-21 | 2017-03-30 | 东南大学 | Band-gap reference voltage source with high power supply rejection ratio |
| CN110136765A (en) * | 2019-05-17 | 2019-08-16 | 山东华翼微电子技术股份有限公司 | A kind of sensitive sense amplifier circuit of EEPROM and its working method of efficient low-power consumption |
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| CN111478581A (en) * | 2020-05-15 | 2020-07-31 | 电子科技大学 | Upper power tube conduction time timing circuit with wide input voltage range |
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