CN113154967A - Delay trigger ignition circuit and delay trigger ignition method thereof - Google Patents
Delay trigger ignition circuit and delay trigger ignition method thereof Download PDFInfo
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- CN113154967A CN113154967A CN202110407538.4A CN202110407538A CN113154967A CN 113154967 A CN113154967 A CN 113154967A CN 202110407538 A CN202110407538 A CN 202110407538A CN 113154967 A CN113154967 A CN 113154967A
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F42—AMMUNITION; BLASTING
- F42C—AMMUNITION FUZES; ARMING OR SAFETY MEANS THEREFOR
- F42C19/00—Details of fuzes
- F42C19/08—Primers; Detonators
- F42C19/12—Primers; Detonators electric
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F42—AMMUNITION; BLASTING
- F42C—AMMUNITION FUZES; ARMING OR SAFETY MEANS THEREFOR
- F42C11/00—Electric fuzes
- F42C11/06—Electric fuzes with time delay by electric circuitry
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Abstract
The invention is suitable for the technical field of circuit design, and provides a delay trigger ignition circuit and a delay trigger ignition method thereof, wherein the delay trigger ignition circuit comprises a low-voltage generating circuit, a high-precision current generating module, a feedback type clock generating module, a delay configuration module and an ignition circuit, and the low-voltage generating circuit is used for generating preset low voltage; the high-precision current generation module is used for generating precision current irrelevant to power supply voltage and temperature; the feedback clock generation module is used for generating an accurate clock signal irrelevant to the power supply voltage and the temperature; the delay configuration module is used for controlling the delay time of the ignition signal; the ignition circuit controls the charging and discharging of the energy storage capacitor to the electric initiating explosive device through the transistor. The invention can work under the condition of larger temperature fluctuation and has the characteristics of no need of external crystal oscillator, easy circuit integration and configurable delay time.
Description
Technical Field
The invention belongs to the technical field of circuit design, and particularly relates to a delay trigger ignition circuit and a delay trigger ignition method thereof.
Background
The electronic detonator is a latest product in the domestic detonating market in recent years. The detonator usually adopts a microelectronic device to replace a traditional lead wire, and a crystal oscillator and a counter are used for delaying time, so that the detonator is more accurate in precision than the traditional lead wire detonator. With the wide application of the electronic detonator, the requirement on the electronic detonator is higher and higher. Aiming at different scenes, the function of configuring the delay of different time is particularly important in the electronic detonator. Meanwhile, the trigger ignition device adopted in part of electronic detonators needs an additional crystal oscillator to generate a clock. The crystal oscillator cannot be integrated in a chip generally, so that the use condition of the chip is limited, and the cost of the chip is increased. Part of the electronic detonators are greatly influenced by temperature, so that the application range of the electronic detonators is limited.
In view of the following drawbacks of the conventional trigger firing circuit: 1) the stable operation can not be realized under the condition of large temperature fluctuation; 2) an additional crystal oscillator is required to generate the clock; 3) a configurable delay time; 4) integration is not easy. Therefore, it is necessary to design a new trigger ignition circuit with high precision and adjustable delay to solve the above technical problems.
Disclosure of Invention
The invention provides a delay trigger ignition circuit and a delay trigger ignition method thereof, aiming at solving various problems in the traditional trigger ignition circuit.
The invention is realized in this way, a delay trigger ignition circuit and a delay trigger ignition method thereof, comprising:
a low voltage generating circuit for generating a preset low voltage;
the high-precision current generation module is used for generating a precise current irrelevant to the power supply voltage and the temperature;
the feedback type clock generating module is used for generating an accurate clock signal irrelevant to power supply voltage and temperature;
a delay configuration module to control a delay time of the ignition signal;
and the ignition circuit controls the charging and discharging of the energy storage capacitor on the electric initiating explosive device through the transistor.
Preferably, the low voltage generating circuit includes: the first to the twelfth pole tubes, the first resistor and the first capacitor. The negative electrode of the first diode is grounded, and the positive electrode of the first diode is connected with one end of a first resistor; the other end of the first resistor is connected with the cathode of the second diode; one end of the first capacitor is connected with the anode of the first diode, and the other end of the first capacitor is grounded; the anode of the second diode is connected with the cathode of the third diode, and the cathode of the second diode is connected with one end of the first resistor; the third to the twelfth pole tubes are sequentially connected in series, the negative end of the twelfth pole tube is connected with the positive end of the ninth diode, and the positive end of the twelfth pole tube is connected with the power supply voltage.
Preferably, the high-precision current generation module includes: the band gap reference circuit comprises a first band gap reference source, a first operational amplifier, first to sixth PMOS (P-channel metal oxide semiconductor) tubes, a second resistor, a third resistor, a first NMOS (N-channel metal oxide semiconductor) tube, a second capacitor, a first comparator, a second comparator and a first NAND gate and a second NAND gate;
the source electrode of the first PMOS tube is connected with the cathode of the second diode, and the grid end of the first PMOS tube is connected with the grid electrode of the second PMOS tube and the drain electrode of the first PMOS tube; the source electrode of the second PMOS tube is connected with the cathode of the second diode, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain end of the second PMOS tube is connected with the source electrode of the fourth PMOS tube; the source electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube, and the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and the drain electrode of the third PMOS tube; the source electrode of the fourth PMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the sixth PMOS tube; the source electrode of the fifth PMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the fifth PMOS tube is connected with the output end of the first operational amplifier, and the drain electrode of the fifth PMOS tube is connected with the upper end of the second resistor; the source electrode of the sixth PMOS tube is connected with the drain end of the fourth PMOS tube, the grid end of the sixth PMOS tube is connected with the grid end of the first NMOS tube, and the drain end of the sixth PMOS tube is connected with the drain end of the first NMOS tube; the output end of the first bandgap reference source is connected with the negative output end of the first operational amplifier; the negative input end of the first operational amplifier is connected with the output end of the band-gap reference, and the positive input end of the first operational amplifier is connected with the drain end of a fifth PMOS tube; the upper end of the second resistor is connected with the drain end of the fifth PMOS, and the lower end of the second resistor is connected with the upper end of the third resistor; the upper end of the third resistor is connected with the lower end of the second resistor, and the lower end of the third resistor is grounded; the drain end of the first NMOS tube is connected with the sixth PMOS tube, the gate end of the first NMOS tube is connected with the output end of the first NAND gate, and the source end of the first NMOS tube is grounded.
Preferably, the feedback clock generating module includes: a second capacitor, first and second comparators, first and second nand gates;
the upper end of the second capacitor is connected with the drain end of the sixth PMOS tube, and the lower end of the second capacitor is grounded; the positive input end of the first comparator is connected with the positive input end of the first operational amplifier, the negative input end of the first comparator is connected with the drain end of the sixth PMOS tube, and the output end of the first comparator is connected with the upper input end of the first NAND gate; the positive input end of the second comparator is connected with the negative input end of the first comparator, the negative input end is connected with the lower end of the second resistor, and the output end is connected with the lower end of the second NAND gate; the upper input end of the first NAND gate is connected with the output end of the first comparator, the lower input end of the first NAND gate is connected with the output end of the second NAND gate, and the output end of the first NAND gate is connected with the upper input end of the second comparator; the upper input end of the second NAND gate is connected with the output end of the first comparator, the lower input end of the second NAND gate is connected with the output end of the second comparator, and the output end of the second NAND gate is connected with the lower input end of the first NAND gate.
Preferably, the delay configuration module includes: configuring an input circuit, a frequency divider circuit, a counter circuit, a digital comparator circuit and a level conversion circuit;
the input end of S1 and S2 bits user in the configuration input circuit is connected with the end of a frequency divider Q0 through an input A, the end of a frequency divider Q5 through an input B, the end of a frequency divider Q10 through an input C, and the end of a frequency divider Q15 through an input D;
the output O end of the configuration input circuit is connected with the input CLK end of the counter;
the input A end is connected with the A end of the digital comparator, the input B end is connected with the B end of the digital comparator, and the input C end is connected with the C end of the digital comparator;
the output end D of the digital comparator is connected with the input end Vin of the level shifter, and the output end of the level shifter is connected with the grid electrodes of the seventh PMOS tube and the second NMOS tube.
Preferably, the firing circuit includes: a fourth resistor, a third capacitor, a seventh PMOS tube, a second NMOS tube and a first ignition device T1;
the upper end of the fourth resistor is connected with power voltage, and the negative end of the fourth resistor is connected with the source electrode of the seventh PMOS tube; the source electrode of the seventh PMOS tube is connected with the lower end of the fourth resistor, the grid electrode of the seventh PMOS tube is connected with the output end of the digital comparator, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the second NMOS tube; the drain electrode of the second NMOS tube is connected with the first ignition device T1, the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with the grid electrode of the seventh PMOS tube; the upper end of the third capacitor is connected with power voltage, and the lower end of the third capacitor is grounded.
The invention also provides a delay triggering ignition method, which comprises the following steps:
s1, installing the delay trigger ignition circuit;
s2, the low voltage generating circuit generates stable 3V voltage for subsequent circuits;
s3, generating a precise current irrelevant to the temperature by a high-precision current generating module; the current enters a feedback clock generation module; generating a clock signal;
s4, user selects the delay mode at the input end of the multi-path selector in the input circuit, the feedback clock generating module generates the clock signal through the multi-path selector; the appropriate clock signal drives the counter to count, when the output value of the counter reaches the comparison threshold value of the digital comparator, the output of the digital comparator is overturned from high level to low level, an ignition enabling signal is generated, and the signal is converted into an ignition signal through the level conversion circuit.
Compared with the prior art, the invention has the beneficial effects that:
1) the high-precision delay-adjustable trigger ignition circuit can work under the condition of large temperature fluctuation;
2) the high-precision delay-adjustable trigger ignition circuit does not need an external crystal oscillator;
3) the high-precision delay-adjustable trigger ignition circuit is easy to integrate;
4) the high-precision delay-adjustable trigger ignition circuit can configure delay time.
Drawings
Fig. 1 is a diagram of a high-precision delay-adjustable trigger ignition circuit according to the present invention.
Fig. 2 is a circuit diagram of the configuration input circuit according to the present invention.
Fig. 3 is a circuit diagram of the frequency divider according to the present invention.
Fig. 4 is a circuit diagram of the digital comparator according to the present invention.
FIG. 5 is a circuit diagram of the counter according to the present invention.
Fig. 6 is a level shift circuit according to the present invention.
FIG. 7 is a graph of current versus temperature for a high precision current generation module according to the present invention.
Fig. 8 is a graph of the corresponding delay signal and trigger firing current versus temperature according to the present invention. .
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1-8, the present invention provides a technical solution: a delay trigger ignition circuit and a delay trigger ignition method thereof are provided, wherein the delay trigger ignition circuit comprises a low-voltage generating circuit, a high-precision current generating module, a feedback type clock generating module, a delay configuration module and an ignition circuit.
The low voltage generating circuit is used for generating preset low voltage; the low voltage generating circuit comprises first to twelfth pole tubes, a first resistor and a first capacitor. The negative electrode of the first diode is grounded, and the positive electrode of the first diode is connected with one end of the first resistor; the other end of the first resistor is connected with the cathode of the second diode; one end of the first capacitor is connected with the anode of the first diode, and the other end of the first capacitor is grounded; the anode of the second diode is connected with the cathode of the third diode, and the cathode of the second diode is connected with one end of the first resistor; the third to the twelfth pole tubes are sequentially connected in series, the negative end of the twelfth pole tube is connected with the positive end of the ninth diode, and the positive end of the twelfth pole tube is connected with the power supply voltage.
The high-precision current generation module is used for generating precision current irrelevant to power supply voltage and temperature. The high-precision current generation module comprises: the band-gap reference circuit comprises a first band-gap reference source, a first operational amplifier, first to sixth PMOS (P-channel metal oxide semiconductor) tubes, second and third resistors, a first NMOS (N-channel metal oxide semiconductor) tube, a second capacitor, first and second comparators and first and second NAND gates.
The source electrode of the first PMOS tube is connected with the cathode of the second diode, and the grid end of the first PMOS tube is connected with the grid electrode of the second PMOS tube and the drain electrode of the first PMOS tube; the source electrode of the second PMOS tube is connected with the cathode of the second diode, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain end of the second PMOS tube is connected with the source electrode of the fourth PMOS tube; the source electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube, and the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and the drain electrode of the third PMOS tube; the source electrode of the fourth PMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the sixth PMOS tube; the source electrode of the fifth PMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the fifth PMOS tube is connected with the output end of the first operational amplifier, and the drain electrode of the fifth PMOS tube is connected with the upper end of the second resistor; the source electrode of the sixth PMOS tube is connected with the drain end of the fourth PMOS tube, the grid end of the sixth PMOS tube is connected with the grid end of the first NMOS tube, and the drain end of the sixth PMOS tube is connected with the drain end of the first NMOS tube; the output end of the first bandgap reference source is connected with the negative output end of the first operational amplifier; the negative input end of the first operational amplifier is connected with the output end of the band-gap reference, and the positive input end of the first operational amplifier is connected with the drain end of a fifth PMOS tube; the upper end of the second resistor is connected with the drain end of the fifth PMOS, and the lower end of the second resistor is connected with the upper end of the third resistor; the upper end of the third resistor is connected with the lower end of the second resistor, and the lower end of the third resistor is grounded; the drain end of the first NMOS tube is connected with the sixth PMOS tube, the gate end of the first NMOS tube is connected with the output end of the first NAND gate, and the source end of the first NMOS tube is grounded.
The feedback clock generation module is used for generating an accurate clock signal which is irrelevant to the power supply voltage and the temperature. The feedback clock generation module comprises: a second capacitor, first and second comparators, and first and second NAND gates.
The upper end of the second capacitor is connected with the drain end of the sixth PMOS tube, and the lower end of the second capacitor is grounded; the positive input end of the first comparator is connected with the positive input end of the first operational amplifier, the negative input end of the first comparator is connected with the drain end of the sixth PMOS tube, and the output end of the first comparator is connected with the upper input end of the first NAND gate; the positive input end of the second comparator is connected with the negative input end of the first comparator, the negative input end is connected with the lower end of the second resistor, and the output end is connected with the lower end of the second NAND gate; the upper input end of the first NAND gate is connected with the output end of the first comparator, the lower input end of the first NAND gate is connected with the output end of the second NAND gate, and the output end of the first NAND gate is connected with the upper input end of the second comparator; the upper input end of the second NAND gate is connected with the output end of the first comparator, the lower input end of the second NAND gate is connected with the output end of the second comparator, and the output end of the second NAND gate is connected with the lower input end of the first NAND gate.
The delay configuration module is used for controlling the delay time of the ignition signal. The delay configuration module includes: the circuit comprises an input circuit, a frequency divider circuit, a counter circuit, a digital comparator circuit and a level conversion circuit.
The input circuit is configured with S1 and S2 bit user input ends, an input A end is connected with a Q0 end of a frequency divider, an input B end is connected with a Q5 end of the frequency divider, an input C end is connected with a Q10 end of the frequency divider, and an input D end is connected with a Q15 end of the frequency divider; the output O end of the configuration input circuit is connected with the input CLK end of the counter; the input A end is connected with the A end of the digital comparator, the input B end is connected with the B end of the digital comparator, and the input C end is connected with the C end of the digital comparator; the output end D of the digital comparator is connected with the input end Vin of the level shifter, and the output end of the level shifter is connected with the grid electrodes of the seventh PMOS tube and the second NMOS tube.
The ignition circuit controls the charging and discharging of the energy storage capacitor to the electric initiating explosive device through the transistor. The firing circuit includes: a fourth resistor, a third capacitor, a seventh PMOS tube, a second NMOS tube and a first ignition device T1.
The upper end of the fourth resistor is connected with power voltage, and the negative end of the fourth resistor is connected with the source electrode of the seventh PMOS tube; the source electrode of the seventh PMOS tube is connected with the lower end of the fourth resistor, the grid electrode of the seventh PMOS tube is connected with the output end of the digital comparator, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the second NMOS tube; the drain electrode of the second NMOS tube is connected with the first ignition device T1, the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with the grid electrode of the seventh PMOS tube; the upper end of the third capacitor is connected with power voltage, and the lower end of the third capacitor is grounded.
Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1: the embodiment provides a delay trigger ignition circuit and a delay trigger ignition method thereof. VDD is power voltage, and the voltage value is 10V. GND is ground potential, and T1 is an electric initiating explosive device to be ignited.
A method for realizing a high-precision delay-adjustable trigger ignition circuit comprises a first to a twelfth polar tubes, and a first resistor which forms a low-voltage generating circuit. The 10V power voltage of the first capacitor is divided by the diode chain D1-D10, the diode conduction voltage drop is 0.7V, wherein C1 is used for stabilizing the voltage, and R1 is used for limiting the current of the diode chain, and 100K-200K can be selected. The low voltage generating circuit generates a stable 3V voltage at the upper end of the R1 resistor, and the 3V voltage supplies power to the high-precision current generating module, the feedback clock generating module and the delay configuration module.
In the high-precision current generation module, a first band gap reference source, a first operational amplifier, first to sixth PMOS tubes, a second resistor, a third resistor and a first NMOS tube form the high-precision current generation module. The P1, the P2, the P3 and the P4 are used as cascode current mirrors to inhibit the influence of the supply voltage change on the precise current. The bandgap references OPM1, P5, R2, R3 form a linear regulator structure for generating a precise current independent of temperature, wherein the voltage at point a is equal to the bandgap reference voltage. The resistor R2 is a diffusion resistor with positive temperature coefficient, and R3 is a polysilicon resistor with negative temperature coefficient. R2 and R3 form a resistor with zero temperature coefficient, and the precision current generated by the high-precision current generation module is 1 microampere. The current enters a feedback clock generation module.
The feedback clock generation module comprises a second capacitor, a first comparator, a second comparator, a first NAND gate and a second NAND gate. The high precision current charges capacitor C2, producing a sawtooth signal at C2. The sawtooth wave signal is compared with two threshold levels and generates a clock signal after passing through an RS trigger.
The delay configuration circuit includes: the configuration input circuit, the frequency divider circuit, the counter circuit and the digital comparator circuit are used for selecting a desired delay mode through the input end of a multiplexer in the configuration input circuit, and a clock generated by the feedback clock generation module generates a proper clock signal through the multiplexer. The appropriate clock signal drives the counter to count, when the output value of the counter reaches the comparison threshold value of the digital comparator, the output of the digital comparator is overturned from high level to low level, an ignition enabling signal is generated, and the signal is converted into an ignition signal through the level conversion circuit to drive the ignition circuit.
The ignition circuit comprises a fourth resistor, a third capacitor, a seventh PMOS tube, a second NMOS tube and a first ignition device T1. The output of the digital comparator is opened P7 and closed N2, at this time, C3 starts to discharge electricity to the electric initiating explosive device T1, and the electric initiating explosive device RL is detonated to finish ignition. R4 can be taken as a charging current-limiting resistor of 100K-200K, so that the charging current of the power supply voltage to C3 is within a safe current range.
Fig. 8 is a waveform of a delay signal output by the high-precision delay-adjustable trigger ignition circuit of the present invention when the operating temperature is varied from-40 ℃ to 125 ℃. It can be seen that the delay signal generated by the high-precision delay-adjustable trigger ignition circuit has small change with temperature.
The invention discloses a delay triggering ignition method, which is based on the delay triggering ignition circuit and comprises the following steps:
s1, installing the delay trigger ignition circuit;
s2, in the low voltage generating circuit, a 10V power voltage is divided by the diode chain D1 to D10, C1 is used to stabilize the voltage, and R1 is used to limit the current of the diode chain. The low voltage generation circuit generates a stable 3V voltage on the upper end of the R1 resistor for subsequent circuits to use;
s3, in the high-precision current generation module, P1, P2, P3 and P4 are used as cascode current mirrors to restrain the influence of the supply voltage change on the precision current. Bandgap references, OPM1, P5, R2, R3, are used to generate accurate currents independent of temperature. The current enters a feedback clock generation module to charge a capacitor C2, and a sawtooth signal is generated on C2. Comparing the sawtooth wave signal with two threshold levels, and generating a clock signal after passing through an RS trigger;
s4, the user selects the desired delay mode at the input end of the multiplexer in the configuration input circuit, and the clock generated by the feedback clock generation module generates the appropriate clock signal through the multiplexer. The appropriate clock signal drives the counter to count, when the output value of the counter reaches the comparison threshold value of the digital comparator, the output of the digital comparator is overturned from high level to low level, an ignition enabling signal is generated, and the signal is converted into an ignition signal through the level conversion circuit. The ignition signal is turned on P7 and turned off N2, and at the moment, C3 starts to discharge electricity to the electric initiating explosive device T1, so that the electric initiating explosive device RL is detonated to finish ignition. R4 is used as a charging current-limiting resistor to make the charging current of the power supply voltage to C3 be in a safe current range.
In summary, the high-precision delay-adjustable trigger ignition circuit has the following beneficial effects:
1) the high-precision delay-adjustable trigger ignition circuit can work under the condition of large temperature fluctuation.
2) The high-precision delay-adjustable trigger ignition circuit does not need an external crystal oscillator.
3) The high-precision delay-adjustable trigger ignition circuit is easy to integrate.
4) The high-precision delay-adjustable trigger ignition circuit can configure delay time.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (7)
1. A time-delay triggered ignition circuit, characterized by: the method comprises the following steps:
a low voltage generating circuit for generating a preset low voltage;
the high-precision current generation module is used for generating a precise current irrelevant to the power supply voltage and the temperature;
the feedback type clock generating module is used for generating an accurate clock signal irrelevant to power supply voltage and temperature;
a delay configuration module to control a delay time of the ignition signal;
and the ignition circuit controls the charging and discharging of the energy storage capacitor on the electric initiating explosive device through the transistor.
2. A delay trigger ignition circuit as defined in claim 1, wherein: the low voltage generating circuit includes: the first to the twelfth pole tubes, the first resistor and the first capacitor. The negative electrode of the first diode is grounded, and the positive electrode of the first diode is connected with one end of a first resistor; the other end of the first resistor is connected with the cathode of the second diode; one end of the first capacitor is connected with the anode of the first diode, and the other end of the first capacitor is grounded; the anode of the second diode is connected with the cathode of the third diode, and the cathode of the second diode is connected with one end of the first resistor; the third to the twelfth pole tubes are sequentially connected in series, the negative end of the twelfth pole tube is connected with the positive end of the ninth diode, and the positive end of the twelfth pole tube is connected with the power supply voltage.
3. A delay trigger ignition circuit as defined in claim 1, wherein: the high-precision current generation module includes: the band gap reference circuit comprises a first band gap reference source, a first operational amplifier, first to sixth PMOS (P-channel metal oxide semiconductor) tubes, a second resistor, a third resistor, a first NMOS (N-channel metal oxide semiconductor) tube, a second capacitor, a first comparator, a second comparator and a first NAND gate and a second NAND gate;
the source electrode of the first PMOS tube is connected with the cathode of the second diode, and the grid end of the first PMOS tube is connected with the grid electrode of the second PMOS tube and the drain electrode of the first PMOS tube; the source electrode of the second PMOS tube is connected with the cathode of the second diode, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain end of the second PMOS tube is connected with the source electrode of the fourth PMOS tube; the source electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube, and the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and the drain electrode of the third PMOS tube; the source electrode of the fourth PMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the sixth PMOS tube; the source electrode of the fifth PMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the fifth PMOS tube is connected with the output end of the first operational amplifier, and the drain electrode of the fifth PMOS tube is connected with the upper end of the second resistor; the source electrode of the sixth PMOS tube is connected with the drain end of the fourth PMOS tube, the grid end of the sixth PMOS tube is connected with the grid end of the first NMOS tube, and the drain end of the sixth PMOS tube is connected with the drain end of the first NMOS tube; the output end of the first bandgap reference source is connected with the negative output end of the first operational amplifier; the negative input end of the first operational amplifier is connected with the output end of the band-gap reference, and the positive input end of the first operational amplifier is connected with the drain end of a fifth PMOS tube; the upper end of the second resistor is connected with the drain end of the fifth PMOS, and the lower end of the second resistor is connected with the upper end of the third resistor; the upper end of the third resistor is connected with the lower end of the second resistor, and the lower end of the third resistor is grounded; the drain end of the first NMOS tube is connected with the sixth PMOS tube, the gate end of the first NMOS tube is connected with the output end of the first NAND gate, and the source end of the first NMOS tube is grounded.
4. A delay trigger ignition circuit as defined in claim 1, wherein: the feedback clock generation module comprises: a second capacitor, first and second comparators, first and second nand gates;
the upper end of the second capacitor is connected with the drain end of the sixth PMOS tube, and the lower end of the second capacitor is grounded; the positive input end of the first comparator is connected with the positive input end of the first operational amplifier, the negative input end of the first comparator is connected with the drain end of the sixth PMOS tube, and the output end of the first comparator is connected with the upper input end of the first NAND gate; the positive input end of the second comparator is connected with the negative input end of the first comparator, the negative input end is connected with the lower end of the second resistor, and the output end is connected with the lower end of the second NAND gate; the upper input end of the first NAND gate is connected with the output end of the first comparator, the lower input end of the first NAND gate is connected with the output end of the second NAND gate, and the output end of the first NAND gate is connected with the upper input end of the second comparator; the upper input end of the second NAND gate is connected with the output end of the first comparator, the lower input end of the second NAND gate is connected with the output end of the second comparator, and the output end of the second NAND gate is connected with the lower input end of the first NAND gate.
5. A delay trigger ignition circuit as defined in claim 1, wherein: the delay configuration module includes: configuring an input circuit, a frequency divider circuit, a counter circuit, a digital comparator circuit and a level conversion circuit;
the input end of S1 and S2 bits user in the configuration input circuit is connected with the end of a frequency divider Q0 through an input A, the end of a frequency divider Q5 through an input B, the end of a frequency divider Q10 through an input C, and the end of a frequency divider Q15 through an input D;
the output O end of the configuration input circuit is connected with the input CLK end of the counter;
the input A end is connected with the A end of the digital comparator, the input B end is connected with the B end of the digital comparator, and the input C end is connected with the C end of the digital comparator;
the output end D of the digital comparator is connected with the input end Vin of the level shifter, and the output end of the level shifter is connected with the grid electrodes of the seventh PMOS tube and the second NMOS tube.
6. A delay trigger ignition circuit as defined in claim 1, wherein: the firing circuit includes: a fourth resistor, a third capacitor, a seventh PMOS tube, a second NMOS tube and a first ignition device T1;
the upper end of the fourth resistor is connected with power voltage, and the negative end of the fourth resistor is connected with the source electrode of the seventh PMOS tube; the source electrode of the seventh PMOS tube is connected with the lower end of the fourth resistor, the grid electrode of the seventh PMOS tube is connected with the output end of the digital comparator, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the second NMOS tube; the drain electrode of the second NMOS tube is connected with the first ignition device T1, the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with the grid electrode of the seventh PMOS tube; the upper end of the third capacitor is connected with power voltage, and the lower end of the third capacitor is grounded.
7. A method of delayed triggered ignition, comprising: the method comprises the following steps:
s1, installing a delay trigger ignition circuit according to any one of claims 1 to 6;
s2, the low voltage generating circuit generates stable 3V voltage for subsequent circuits;
s3, generating a precise current irrelevant to the temperature by a high-precision current generating module; the current enters a feedback clock generation module; generating a clock signal;
s4, user selects the delay mode at the input end of the multi-path selector in the input circuit, the feedback clock generating module generates the clock signal through the multi-path selector; the appropriate clock signal drives the counter to count, when the output value of the counter reaches the comparison threshold value of the digital comparator, the output of the digital comparator is overturned from high level to low level, an ignition enabling signal is generated, and the signal is converted into an ignition signal through the level conversion circuit.
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| CN202110407538.4A CN113154967A (en) | 2021-04-15 | 2021-04-15 | Delay trigger ignition circuit and delay trigger ignition method thereof |
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| CN202110407538.4A CN113154967A (en) | 2021-04-15 | 2021-04-15 | Delay trigger ignition circuit and delay trigger ignition method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114111475A (en) * | 2021-12-10 | 2022-03-01 | 苏州烽燧电子有限公司 | Electronic fuse for smoke screen |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114111475A (en) * | 2021-12-10 | 2022-03-01 | 苏州烽燧电子有限公司 | Electronic fuse for smoke screen |
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