CN108736875B - Trimming code value generating circuit - Google Patents
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
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- H—ELECTRICITY
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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Abstract
A modification code value generation circuit belongs to the technical field of electronic circuits. The device comprises a control signal generation module, a modification code value generation module and a modification code value storage output module, wherein the control signal generation module is used for generating a control signal PD _ N to control whether the modification code value generation module normally works, the modification code value generation module comprises a reference comparison unit and a generation unit, whether a current fuse is fused in the generation unit is controlled to generate a modification code value, and the input end of the modification code value storage output module is connected with the output end of the generation unit and used for storing and outputting the modification code value. The circuit provided by the invention works when the generated trimming code value is required to be generated, and enters a reset state after the generated trimming code value is stored, so that the current loss is reduced, and the power consumption of the circuit is greatly reduced.
Description
Technical Field
The invention relates to the electronic circuit technology, in particular to a trimming code value generating circuit.
Background
Trimming (Trimming) generally refers to the act of adjusting certain parameters of a chip by externally writing data into the chip after the chip is manufactured. The Trimming technology can reduce the process fluctuation and disorder and improve the parameter precision of the chip. Since the Trimming module also has power consumption, not only the significance of improving the precision of chip parameters to the whole chip system needs to be fully considered in the chip system design, but also how to further reduce the power consumption of the Trimming circuit is considered, especially in the low-power design application.
Therefore, the ultra-low power consumption trimming code value generating circuit optimizes the circuit and reduces the power consumption of the trimming code value generating circuit at the same time, so that the ultra-low power consumption trimming code value generating circuit is suitable for the development trend of low power consumption of the current integrated circuit.
Disclosure of Invention
In order to overcome the power consumption problem of the existing trimming circuit, the invention provides the trimming code value generating circuit which can effectively control the working time of the trimming code value generating module, improve the working efficiency of the trimming code value generating module and greatly reduce the power consumption of the circuit.
The technical scheme adopted by the invention is as follows:
a circuit for generating a modified code value comprises a control signal generating module, a modified code value generating module and a modified code value saving and outputting module,
the control signal generation module is used for generating a control signal PD _ N to control the modification value generation module,
the mask value generation module includes a reference comparison unit and a generation unit,
the reference comparison unit comprises a first NMOS transistor NM1, a second NMOS transistor NM2, a fourth NMOS transistor NM4, a first PMOS transistor PM1 and a first resistor R1,
the drain of the first NMOS transistor NM1 is connected to a reference current Iref, the gate thereof is connected to the gate of the second NMOS transistor NM2 and the drain of the fourth NMOS transistor NM4 and serves as the first output terminal of the reference comparison unit, and the source thereof is connected to the sources of the second NMOS transistor NM2 and the fourth NMOS transistor NM4 and is grounded to GND;
the gate of the fourth NMOS transistor NM4 is connected to the control signal PD _ N;
the drain of the second NMOS transistor NM2 is connected to the gate and the drain of the first PMOS transistor PM1 and serves as the second output terminal of the reference comparison unit;
one end of the first resistor R1 is connected with a power supply voltage VDD, and the other end of the first resistor R1 is connected with the source electrode of the first PMOS transistor PM 1;
the generation unit includes a second PMOS transistor PM2, a fuse, a third NMOS transistor NM3, and a fifth NMOS transistor NM5,
the grid electrode of the third NMOS tube NM3 is connected with the first output end of the reference comparison unit, the drain electrode thereof is connected with the drain electrodes of the fifth NMOS tube NM5 and the second PMOS tube PM2 and serves as the output end of the generation unit, and the source electrode thereof is connected with the source electrode of the fifth NMOS tube NM5 and is grounded GND;
the grid electrode of the fifth NMOS tube NM5 is connected with the control signal PD _ N;
the grid electrode of the second PMOS pipe PM2 is connected with the second output end of the reference comparison unit, and the source electrode of the second PMOS pipe PM2 is connected with one end of the fuse and serves as a fuse control end;
the other end of the fuse is connected with a power supply voltage VDD;
the input end of the modifying code value saving output module is connected with the output end of the generating unit, and the output end of the modifying code value saving output module outputs the modifying code value.
Specifically, the control signal generating module includes a D flip-flop, a first delayer Delay _1, a second delayer Delay _2, a first AND gate AND1, AND a first inverter INV1,
a first input end of the first AND gate AND1 is connected to the enable signal EN, a second input end thereof is connected to the output end of the second delayer Delay _2, AND an output end thereof is connected to the input ends of the first delayer Delay _1 AND the first inverter INV 1;
the output end of the first inverter INV1 outputs the control signal PD _ N;
the data input end of the D trigger is connected with a power supply voltage VDD, the clock input end of the D trigger is connected with the output end of the first delayer Delay _1, the reset end of the D trigger is connected with the enable signal EN, and the Q non-output end of the D trigger is connected with the input end of the second delayer Delay _ 2.
Specifically, a shaping unit is further disposed between an output end of the first delayer Delay _1 and a clock input end of the D flip-flop in the control signal generation module, and the shaping unit includes a second inverter INV2 and a third inverter INV3,
an input end of the second inverter INV2 is connected to the output end of the first delayer Delay _1, and an output end thereof is connected to an input end of the third inverter INV 3; an output end of the third inverter INV3 is connected to the clock input end of the D flip-flop.
Specifically, the control signal generating module further includes a second AND gate AND2 AND a fourth inverter INV4,
the input end of the fourth inverter INV4 is connected to the clock input end of the D flip-flop, AND the output end thereof is connected to the first input end of the second AND gate AND 2;
a second input terminal of the second AND gate AND2 is connected to the Q output terminal of the D flip-flop, AND an output terminal thereof outputs a ready signal Trimming _ ok.
Specifically, the modification value saving and outputting module comprises a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7 and an RS flip-flop,
an input end of the fifth inverter INV5 is used as an input end of the trimming value saving output module, and an output end of the fifth inverter INV5 is connected with an input end of the sixth inverter INV 6;
the S input end of the RS flip-flop is connected with the output end of the sixth inverter INV6, the R input end of the RS flip-flop is connected with the output end of the seventh inverter INV7, and the Q output end or the Q non-output end of the RS flip-flop outputs the trimming code value;
an input end of the seventh inverter INV7 is connected to the enable signal EN.
Specifically, when N modification value values need to be generated, the modification value generation circuit includes N generation units and N modification value storage output modules corresponding to the generation units, an output end of each generation unit is connected to an input end of the corresponding modification value storage output module, output signals of the N modification value storage output modules constitute the N modification value values needed, where N is a positive integer.
The invention has the beneficial effects that: when the trimming code value needs to be generated, the circuit works, and the circuit enters a reset state after the generated trimming code value is stored, so that the current loss is reduced, and the power consumption of the circuit is greatly reduced.
Drawings
Fig. 1 is a schematic diagram of a circuit structure implementation of a modified modulation value generation circuit according to the present invention.
FIG. 2 is a waveform diagram of key signals of the control signal generating module according to the present invention.
Fig. 3 is a waveform diagram of key signals of the modification value generation module and the modification value saving output module according to the present invention.
Fig. 4 is an implementation form of an RS flip-flop.
FIG. 5 is a diagram of the true values of the RS flip-flops in the example.
Detailed Description
The technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.
The invention provides a repair code value generation circuit which comprises a control signal generation module, a repair code value generation module and a repair code value storage output module, wherein the control signal generation module is used for generating a control signal PD _ N to control whether the repair code value generation module works normally, the repair code value generation module comprises a reference comparison unit and a generation unit, and the input end of the repair code value storage output module is connected with the output end of the generation unit and used for storing and outputting repair code values. The number of generating units and the number of modifying code value saving output modules in the modifying code value generating module can be set according to the number of modifying codes required to be generated in actual use, if N (N is a positive integer) modifying codes are required to be generated, the modifying code value generating module is required to be provided with N generating units, the N generating units can share one reference comparing unit, the corresponding N modifying code value saving output modules are required to store and output signals of the N generating units, and the output signals of the N modifying code value saving output modules form the required N-bit modifying code value.
As shown in fig. 1, in the trimming code value generating module, the reference comparing unit includes a first NMOS transistor NM1, a second NMOS transistor NM2, a fourth NMOS transistor NM4, a first PMOS transistor PM1 and a first resistor R1, a drain of the first NMOS transistor NM1 is connected to the reference current Iref, a gate thereof is connected to a gate of the second NMOS transistor NM2 and a drain of the fourth NMOS transistor NM4 and serves as a first output terminal of the reference comparing unit, and a source thereof is connected to sources of the second NMOS transistor NM2 and the fourth NMOS transistor NM4 and is grounded GND; the reference current Iref may be provided by a reference current source; the gate of the fourth NMOS transistor NM4 is connected to the control signal PD _ N; the drain of the second NMOS transistor NM2 is connected to the gate and the drain of the first PMOS transistor PM1 and serves as the second output terminal of the reference comparison unit; one end of the first resistor R1 is connected to the power supply voltage VDD, and the other end is connected to the source of the first PMOS transistor PM 1.
The generating unit comprises a second PMOS tube PM2, a fuse, a third NMOS tube NM3 and a fifth NMOS tube NM5, the grid electrode of the third NMOS tube NM3 is connected with the first output end of the reference comparison unit, the drain electrode of the third NMOS tube NM3 is connected with the drain electrodes of the fifth NMOS tube NM5 and the second PMOS tube PM2 and serves as the output end of the generating unit, and the source electrode of the third NMOS tube NM 35353525 is connected with the source electrode of the fifth NMOS tube NM5 and is grounded GND; the gate of the fifth NMOS transistor NM5 is connected to the control signal PD _ N; the grid electrode of the second PMOS pipe PM2 is connected with the second output end of the reference comparison unit, and the source electrode of the second PMOS pipe PM2 is connected with one end of the fuse and serves as a fuse control end; the other end of the fuse is connected to a supply voltage VDD. Preferably, a current fuse is generally used.
As shown in fig. 1, an implementation circuit structure of the repair code value saving output module is provided, which includes a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7 and an RS flip-flop, wherein an input end of the fifth inverter INV5 is used as an input end of the repair code value saving output module, and an output end of the fifth inverter INV5 is connected to an input end of the sixth inverter INV 6; the S input end of the RS flip-flop is connected with the output end of the sixth inverter INV6, the R input end of the RS flip-flop is connected with the output end of the seventh inverter INV7, and the input end of the seventh inverter INV7 is connected with the enable signal EN; the Q output terminal of the RS flip-flop outputs a Vout signal, the Q non-output terminal thereof outputs a Vout ' signal, and the Vout signal output by the Q output terminal of the RS flip-flop is generally selected as a trimming code value, and the Vout ' signal output by the Q non-output terminal of the RS flip-flop is used as a spare trimming code value, for example, when a current fuse is not fused, the Vout signal is 1, the Vout ' signal is 0, and the situation is exactly opposite to that after the current fuse is fused, if the trimming code value required by a subsequent circuit is 1, then two schemes are possible: 1. the current fuse is not fused, and the Vout signal is selected as a trimming code value to be output; 2. and blowing a current fuse, and selecting the Vout' signal as a trimming code value to be output, wherein the specific selection scheme can be determined according to the required condition and the use condition of the trimming code value.
The RS flip-flop is used to store and output the trimming code value generated by the generating unit, and may be in a nor gate form or a nand gate form, as shown in fig. 4, the RS flip-flop is in a nor gate form, and fig. 5 is a truth table of the RS flip-flop in a nor gate form.
As shown in fig. 1, the circuit implementation structure of the control signal generation module includes a D flip-flop, a first Delay _1, a second Delay _2, a first AND gate AND1, AND a first inverter INV1, where the D flip-flop is reset at a low level, a first input terminal of the first AND gate AND1 is connected to an enable signal EN, a second input terminal thereof is connected to an output terminal of the second Delay _2, AND an output terminal thereof is connected to input terminals of the first Delay _1 AND the first inverter INV 1; the output end of the first inverter INV1 outputs the control signal PD _ N; the data input end of the D trigger is connected with a power supply voltage VDD, the clock input end of the D trigger is connected with the output end of the first Delay _1, the reset end of the D trigger is connected with an enable signal EN, and the Q non-output end of the D trigger is connected with the input end of the second Delay _ 2.
In some embodiments, a shaping unit is further disposed between the output end of the first delayer Delay _1 and the clock input end of the D flip-flop in the control signal generation module, and includes a second inverter INV2 and a third inverter INV3, an input end of the second inverter INV2 is connected to the output end of the first delayer Delay _1, and an output end of the second inverter INV2 is connected to an input end of the third inverter INV 3; an output end of the third inverter INV3 is connected to the clock input end of the D flip-flop. The shaping unit is used for shaping the output signal of the first Delay _1 and inputting the shaped output signal to the clock input end of the D flip-flop, and the shaping unit can be replaced by a buffer or a Schmitt flip-flop or even removed.
In some embodiments, the control signal generating module further includes a second AND gate AND2 AND a fourth inverter INV4, an input terminal of the fourth inverter INV4 is connected to the clock input terminal of the D flip-flop, AND an output terminal thereof is connected to the first input terminal of the second AND gate AND 2; a second input terminal of the second AND gate AND2 is connected to the Q output terminal of the D flip-flop, AND an output terminal thereof outputs a ready signal Trimming _ ok. The preparation signal Trimming _ ok indicates that the Trimming code value generation circuit is prepared, generates a corresponding Trimming code value, can be connected to a subsequent circuit to serve as an enable signal, and informs the subsequent circuit that the generated Trimming code value can be used for working.
The working process of the present invention is described in detail by taking the generation of a one-bit trimming value as an example, the trimming value generation module includes a reference comparison unit and a generation unit, the current fuse in the generation unit is Pfuse _1, and the output signal V _1 of the generation unit generates Vout _1 and Vout _ 1' after passing through the trimming value saving output module.
For the control signal generation module, the enable signal EN at the initial time is low, at this time, the D flip-flop in the control signal generation module is in a reset state, the output signal of the Q output end of the D flip-flop is at a low level, and the output signal vin2 of the second delayer Delay _2 is at a high level; when the enable signal EN is pulled high, the enable signal EN and the output signal vin2 of the second Delay device Delay _2 are anded with each other, so that the PD signal rises, the PD signal is delayed by Δ t1 time by the first Delay device Delay _1 and then input to the clock input terminal of the D flip-flop after being shaped, the potential applied to the data input terminal of the D flip-flop, that is, the D terminal is at a high level, at this time, the enable signal EN is high, the D flip-flop is reset, the rising edge of the clock signal of the D flip-flop, that is, the CK signal, comes to make the output signal of the Q output terminal of the D flip-flop high, the output signal of the Q non-output terminal of the D flip-flop is delayed by Δ t2 time by the second Delay device Delay _2 to generate vin2, and finally the waveform shown in fig. 2 can be obtained. And simultaneously, after the clock signal CK of the D trigger is inverted, the clock signal CK and the output signal phase of the Q output end of the D trigger are in phase with an available preparation signal Trimming _ ok, namely that the preparation of the Trimming calibration generating circuit is finished.
For the trimming code value generating module, the control signal PD _ N at the initial time is high, the entire trimming code value generating module is turned off, that is, is in a reset state, when the enable signal EN is high, the control signal PD _ N pulls down to release the reset state of the trimming code value generating module, the control signal PD _ N is accessed to the gate of the fourth NMOS tube NM4 in the reference comparing unit of the trimming code value generating module and the gate of the fifth NMOS tube NM5 in the generating unit, and the fourth NMOS tube NM4 and the fifth NMOS tube NM5 are controlled to be turned on and off according to the level of the control signal PD _ N, so that the reset state of the trimming code value generating module is released, and the trimming code value generating module is controlled to normally operate.
In the trimming code value generating module, a first NMOS transistor NM1, a second NMOS transistor NM2 and a third NMOS transistor NM3 form a current mirror, a fourth NMOS transistor NM4 is used for controlling whether the current mirror is turned on, a fifth NMOS transistor NM5 is used for controlling an output signal of a generating unit in the trimming code value generating module to be in a certain state, whether a current fuse is blown or not is selected according to a trimming value required to be generated, the output signal of the generating unit is controlled to be in a high level or a low level by controlling whether the current fuse is blown or not, the blown current fuse can be generated by applying a certain external voltage to a current fuse control terminal, the resistance value of the current fuse before being unblown is similar to 0, the current fuse is equivalent to a wire, and the resistance value after being blown is close to infinity, namely, the circuit is opened. The output signal of the generating unit in the modification code value generating module is input to the modification code value storage output module for output, when the modification code value is generated and output, the control signal generating module inverts the control signal PD _ N again to enable the modification code value generating module to enter a reset state, the working time for generating the modification code value for one time is delta t1+ delta t2, and the whole modification code value generating circuit is closed after delta t1+ delta t2 time, so that the current loss is reduced, and the power consumption of the circuit is greatly reduced.
When the current fuse Pfuse _1 is not blown, the resistance value R of the current fusePfuse_1Resistance value R of first resistor R1 in reference comparison unit1From the formula:
R1IPM1+VGS1＝RPfuse1IPM2+VGS2
easily obtained VGS1＜VGS2From the formula
Is easy to obtainPM1＜IPM2In which IPMRepresenting the value of the current, V, flowing through the PMOS tubeGSRepresents the grid source voltage value of the MOS tube, mu represents the carrier mobility, Cox represents the unit area grid capacitance,
the width-to-length ratio of the MOS transistor is shown, and Vth represents the threshold voltage of the MOS transistor. And since the width-to-length ratio of the second NMOS transistor NM2 and the third NMOS transistor NM3 is the same as the gate-source voltage VGS, INM2And INM3Similarly, since the NMOS current mirror and the PMOS current mirror have a mismatch relationship, the output signal V _1 of the generating unit tends to reduce the current flowing through the second PMOS transistor PM2, so that V _1 is pulled high.
In the same way, when electricityFlow fuse Pfuse_1Fusing off so that VGSPM1>VGSPM2Then, IPM1＞IPM2V _1 tends to increase the current through the second PMOS transistor PM2, so V _1 is pulled low. The key signal waveforms are shown in fig. 2.
The modification code value saving output module uses an output signal V _1 and an enable signal EN of a generating unit in the modification code value generating module as input signals, utilizes an RS trigger built by a NOR gate, when the enable signal EN is pulled high, the whole modification code value generating circuit starts to work, firstly, the reset state of the modification code value generating module is released, and then, according to a current fuse Pfuse_1The corresponding V _1 value is saved and output. When current flows through the fuse Pfuse_1When not blown, the SR end of the RS trigger is changed through 01-10-00 state to finally obtain stable Vout _1 and Vout _ 1' values when the current fuse Pfuse_1When the fuse is blown, the SR end of the RS trigger is changed from 01 to 00 states, and finally stable Vout _1 and Vout _ 1' values can be obtained. The key signal waveforms are shown in fig. 3.
When N-bit modification values need to be generated, a control signal generation module can be used to generate a control signal PD _ N to control N generation units in the modification value generation module, output signals V _1, V _2, … …, and V _ N of the N generation units are respectively input to input ends of N modification value storage output modules, and output signals of the N modification value storage output modules form N-bit modification values.
It is to be understood that the invention is not limited to the precise arrangements and components shown above. Various modifications, changes and optimizations may be made to the order of the steps, details and operations of the methods and structures described above without departing from the scope of protection of the claims.
Claims (6)
1. A circuit for generating a modified code value comprises a control signal generating module, a modified code value generating module and a modified code value saving and outputting module,
the control signal generation module is used for generating a control signal (PD _ N) to control the modification value generation module,
the mask value generation module includes a reference comparison unit and a generation unit,
the reference comparison unit comprises a first NMOS transistor (NM1), a second NMOS transistor (NM2), a fourth NMOS transistor (NM4), a first PMOS transistor (PM1) and a first resistor (R1),
the drain electrode of the first NMOS tube (NM1) is connected with a reference current (Iref), the grid electrode of the first NMOS tube (NM1) is connected with the grid electrode of the second NMOS tube (NM2) and the drain electrode of the fourth NMOS tube (NM4) and serves as the first output end of the reference comparison unit, and the source electrode of the first NMOS tube (NM1) is connected with the source electrodes of the second NMOS tube (NM2) and the fourth NMOS tube (NM4) and is Grounded (GND);
the grid electrode of the fourth NMOS tube (NM4) is connected with the control signal (PD _ N);
the drain electrode of the second NMOS tube (NM2) is connected with the grid electrode and the drain electrode of the first PMOS tube (PM1) and serves as a second output end of the reference comparison unit;
one end of the first resistor (R1) is connected with a power supply Voltage (VDD), and the other end of the first resistor (R1) is connected with the source electrode of the first PMOS tube (PM 1);
the generating unit comprises a second PMOS tube (PM2), a fuse, a third NMOS tube (NM3) and a fifth NMOS tube (NM5),
the grid electrode of the third NMOS tube (NM3) is connected with the first output end of the reference comparison unit, the drain electrode of the third NMOS tube (NM3) is connected with the drain electrodes of the fifth NMOS tube (NM5) and the second PMOS tube (PM2) and serves as the output end of the generating unit, and the source electrode of the third NMOS tube (NM 3578) is connected with the source electrode of the fifth NMOS tube (NM5) and is Grounded (GND);
the grid electrode of the fifth NMOS tube (NM5) is connected with the control signal (PD _ N);
the grid electrode of the second PMOS pipe (PM2) is connected with the second output end of the reference comparison unit, and the source electrode of the second PMOS pipe is connected with one end of the fuse and serves as a fuse control end;
the other end of the fuse is connected with a power supply Voltage (VDD);
the input end of the modification code value storage output module is connected with the output end of the generation unit, and the output end of the modification code value storage output module outputs the modification code value;
when the control signal (PD _ N) is turned from high to low, the modification code value generation module starts to work to generate the modification code value, and when the modification code value is output, the control signal (PD _ N) is turned from low to high to enable the modification code value generation module to enter a reset state.
2. The mask value generating circuit according to claim 1, wherein the control signal generating block includes a D flip-flop, a first Delay _1, a second Delay _2, a first AND gate (AND1), AND a first inverter (INV1),
a first input end of the first AND gate (AND1) is connected with the enable signal (EN), a second input end thereof is connected with an output end of the second delayer (Delay _2), AND an output end thereof is connected with input ends of the first delayer (Delay _1) AND the first inverter (INV 1);
an output terminal of the first inverter (INV1) outputs the control signal (PD _ N);
the data input end of the D trigger is connected with a power supply Voltage (VDD), the clock input end of the D trigger is connected with the output end of the first delayer (Delay _1), the reset end of the D trigger is connected with the enable signal (EN), and the Q non-output end of the D trigger is connected with the input end of the second delayer (Delay _ 2).
3. The mask value generating circuit according to claim 2, wherein a shaping unit is further provided between an output terminal of the first delayer (Delay _1) and a clock input terminal of the D flip-flop in the control signal generating module, the shaping unit including a second inverter (INV2) and a third inverter (INV3),
the input end of the second inverter (INV2) is connected with the output end of the first delayer (Delay _1), and the output end of the second inverter (INV2) is connected with the input end of the third inverter (INV 3); the output end of the third inverter (INV3) is connected with the clock input end of the D flip-flop.
4. The trim value generation circuit according to claim 2 or 3, wherein the control signal generation block further comprises a second AND gate (AND2) AND a fourth inverter (INV4),
the input end of the fourth inverter (INV4) is connected with the clock input end of the D flip-flop, AND the output end of the fourth inverter is connected with the first input end of the second AND gate (AND 2);
a second input of the second AND-gate (AND2) is connected to the Q output of the D flip-flop, the output of which outputs the ready signal (Trimming _ ok).
5. The mask value generating circuit according to claim 1, wherein the mask value save output module includes a fifth inverter (INV5), a sixth inverter (INV6), a seventh inverter (INV7), and an RS flip-flop,
the input end of the fifth inverter (INV5) is used as the input end of the trimming value saving output module, and the output end of the fifth inverter (INV5) is connected with the input end of the sixth inverter (INV 6);
the S input end of the RS flip-flop is connected with the output end of the sixth inverter (INV6), the R input end of the RS flip-flop is connected with the output end of the seventh inverter (INV7), and the Q output end or the Q non-output end of the RS flip-flop outputs the trimming code value;
an input end of the seventh inverter (INV7) is connected to the enable signal (EN).
6. The mask value generating circuit according to claim 1, wherein when N mask values need to be generated, the mask value generating circuit comprises N generating units and N corresponding mask value saving output modules, an output terminal of each generating unit is connected to an input terminal of the corresponding mask value saving output module, output signals of the N mask value saving output modules constitute the N required mask values, where N is a positive integer.
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| CN113189477B (en) * | 2020-09-03 | 2022-10-28 | 深圳利普芯微电子有限公司 | Chip trimming circuit and trimming method |
| CN112367073B (en) * | 2020-11-18 | 2024-04-26 | 江苏润石科技有限公司 | High-reliability trimming circuit |
| CN112968696B (en) * | 2021-02-26 | 2023-06-06 | 西安微电子技术研究所 | Trimming circuit with virtual trimming function |
| CN113741618B (en) * | 2021-09-29 | 2022-05-17 | 电子科技大学 | Rear end trimming control circuit |
| CN114256812B (en) * | 2022-02-08 | 2022-11-01 | 深圳市创芯微微电子有限公司 | Battery protection circuit and trimming circuit |
| CN114637359A (en) * | 2022-03-25 | 2022-06-17 | 北京集创北方科技股份有限公司 | Trimming circuit, driving device, chip and electronic equipment |
| CN114822663B (en) * | 2022-05-17 | 2023-03-10 | 上海摩芯半导体技术有限公司 | Control circuit suitable for chip Fuse is write in |
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| CN107169219A (en) * | 2017-05-26 | 2017-09-15 | 北京伽略电子股份有限公司 | A kind of fuse of high flexibility ratio trims circuit and its application method |
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| JP2006319504A (en) * | 2005-05-11 | 2006-11-24 | Sharp Corp | Trimming circuit |
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