CN112447822A - 一种半导体功率器件 - Google Patents
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Abstract
本发明实施例提供的一种半导体功率器件,包括:n型漏区以及位于所述n型漏区之上的n型外延层,所述n型外延层中设有:至少两个第一p型体区,所述第一p型体区内设有n型源区;位于所述第一p型体区下方的p型柱状掺杂区;位于相邻两个所述第一p型体区之间的两个栅极沟槽,该两个栅极沟槽之间设有第二p型体区;所述栅极沟槽内设有栅介质层和栅极。
Description
技术领域
本发明属于半导体功率器件技术领域,特别是涉及一种超结结构的半导体功率器件。
背景技术
现有技术的一种超结结构的半导体功率器件的剖面结构如图1所示,包括:n型漏区31和位于n型漏区31之上的n型外延层30,n型漏区31通过漏极金属层70接漏极电压;在n型外延层30内形成有栅极沟槽,在栅极沟槽内形成有栅介质层35和栅极36,栅极36通过栅极电压来控制位于p型体区33内的电流沟道的开启和关断。p型体区33和n型源区34通过源极金属层47接源极电压。高掺杂浓度的p型体区接触区38用于降低欧姆接触。在p型体区33的下方形成有p型柱状外延掺杂区32。绝缘介质层50为层间绝缘层。
超结结构的半导体功率器件在开启和关断过程中,米勒电容(Crss)及其所对应的栅漏电容(Cgd)对半导体功率器件的开关过程起到重要的作用,现有技术的超结结构的半导体功率器件由于栅漏电容过小,在开启和关断时会导致栅漏电容发生突变,从而导致电磁干扰严重。
发明内容
有鉴于此,本发明的目的是提供一种半导体功率器件,以解决现有技术中的半导体功率器件由于栅漏电容过小导致的电磁干扰严重的问题。
本发明实施例提供的一种半导体功率器件,包括:
n型漏区以及位于所述n型漏区之上的n型外延层,所述n型外延层中设有:
至少两个第一p型体区,所述第一p型体区内设有n型源区;
位于所述第一p型体区下方的p型柱状掺杂区;
位于相邻两个所述第一p型体区之间的两个栅极沟槽,该两个栅极沟槽之间设有第二p型体区;
所述栅极沟槽内设有栅介质层和栅极。
可选的,本发明所述第二p型体区外接源极电压。
可选的,本发明所述第二p型体区的宽度小于所述第一p型体区的宽度。
可选的,本发明所述栅极沟槽包括上部和下部两部分,所述栅极和所述栅介质层位于所述栅极沟槽的上部内,所述栅极沟槽的下部内设有屏蔽栅和场氧化层。
可选的,本发明所述屏蔽栅和所述场氧化层向上延伸至所述栅极沟槽的上部内,所述屏蔽栅通过所述场氧化层与所述栅极隔离。
可选的,本发明所述屏蔽栅将所述栅极分割为靠近所述第一p型体区一侧的第一栅极和靠近所述第二p型体区一侧的第二栅极。
可选的,本发明所述第一栅极外接栅极电压,所述第二栅极外接源极电压。
本发明实施例提供的一种半导体功率器件具有较大的栅漏电容,可以降低半导体功率器件在开启和关断时由于栅漏电容突变导致的电磁干扰。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案,下面对描述实施例中所需要用到的附图做一简单介绍。显然,所介绍的附图只是本发明所要描述的一部分实施例的附图,而不是全部的附图,对于本领域普通技术人员,在不付出创造性劳动的前提下,还可以根据这些附图得到其他的附图。
图1是现有技术的一种半导体功率器件的剖面结构示意图;
图2是本发明提供的一种半导体功率器件的第一个实施例的剖面结构示意图;
图3是本发明提供的一种半导体功率器件的第二个实施例的剖面结构示意图;
图4是本发明提供的一种半导体功率器件的第三个实施例的剖面结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚,以下将结合本发明实施例中的附图,通过具体方式,完整地描述本发明的技术方案。显然,所描述的实施例是本发明的一部分实施例,而不是全部的实施例。
应当理解,本发明所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在或添加。同时,为清楚地说明本发明的具体实施方式,说明书附图中所列图形大小并不代表实际尺寸,说明书附图是示意性的,不应限定本发明的范围。说明书中所列实施例不应仅限于说明书附图中所示区域的特定形状,而是包括所得到的形状如制备引起的偏差等。
图2是本发明提供的一种半导体功率器件的第一个实施例的剖面结构示意图,如图2所示,本发明实施例提供的一种半导体功率器件,包括n型漏区20,n型漏区20可以通过漏极金属层外接漏极电压。位于n型漏区20之上的n型外延层21,以及位于n型外延层21中的:
至少两个第一p型体区24,图2中示例性的示出了3个第一p型体区24结构,同时为了方便展示和说明,图2中示例性的框出了本发明的一个最小单元结构101。
第一p型体区24内设有n型源区26,第一p型体区24的下方设有p型柱状掺杂区27,p型柱状掺杂区27可以与第一p型体区24相连接,也可以不连接,示例性的,图2中的p型柱状掺杂区27可以与第一p型体区24相连接。第一p型体区24和n型源区26可以通过源极金属层外接源极电压。
位于相邻的两个第一p型体区24之间的两个栅极沟槽,该两个栅极沟槽之间设有第二p型体区25,可选的,第二p型体区25的宽度小于第一p型体区24的宽度,这样可以减小半导体功率器件的芯片尺寸,降低半导体功率器件的制造成本。
栅极沟槽中设有栅介质层22和栅极23,栅极23可以通过栅极金属层外接栅极电压,由此栅极23通过栅极电压来控制位于第一p型体区24中的电流沟道的开启和关断。
本发明实施列的一种半导体功率器件,在相邻的第一p型体区之间设置两个栅极沟槽,从而形成两个栅极结构,这样能够增大半导体功率器件的栅漏电容,从而可以降低半导体功率器件在开启和关断时由于栅漏电容突变导致的电磁干扰。在两个栅极沟槽之间设置第二p型体区,可以降低栅极底部处的电场强度,使得半导体功率器件的制造工艺窗口变大,提高半导体功率器件的制造稳定性,同时,可选的,可以使第二p型体区外加源极电压,可以进一步降低栅极底部处的电场强度。
图3是本发明提供的一种半导体功率器件的第二个实施例的剖面结构示意图,如图3所示,本发明实施列的半导体功率器件栅极沟槽包括上部和下部两部分,栅极23和栅介质层22位于栅极沟槽的上部内,栅极沟槽的下部内设有屏蔽栅28和场氧化层27。屏蔽栅28可以外接源极电压,从而可以调节栅极沟槽的下部处的电场强度,提高半导体功率器件的耐压。
图4是本发明提供的一种半导体功率器件的第三个实施例的剖面结构示意图,如图4所示,本发明实施列的半导体功率器件是在图3所示的半导体功率器件的基础上,将屏蔽栅28和场氧化层27向上延伸至栅沟槽的上部内,屏蔽栅28通过场氧化层27与栅极隔离。屏蔽栅28和场氧化层27向上延伸至栅沟槽的上部内时,可以将栅极分割为靠近第一p型体区24一侧的第一栅极23a和靠近第二p型体区25一侧的第二栅极23b,此时第一栅极23a和第二栅极23b可以同时外接栅极电压,也可以是第一栅极23a外接栅极电压,第二栅极23b外接源极电压。
以上具体实施方式及实施例是对本发明提出的一种半导体功率器件技术思想的具体支持,不能以此限定本发明的保护范围,凡是按照本发明提出的技术思想,在本技术方案基础上所做的任何等同变化或等效的改动,均仍属于本发明技术方案保护的范围。
尽管本发明的实施方案已公开如上,但其并不仅仅限于说明书和实施方式中所列运用,它完全可以被适用于各种适合本发明的领域,对于熟悉本领域的人员而言,可容易地实现另外的修改,因此在不背离权利要求及等同范围所限定的一般概念下,本发明并不限于特定的细节和这里示出与描述的图例。
Claims (7)
1.一种半导体功率器件,其特征在于,包括:
n型漏区以及位于所述n型漏区之上的n型外延层,所述n型外延层中设有:
至少两个第一p型体区,所述第一p型体区内设有n型源区;
位于所述第一p型体区下方的p型柱状掺杂区;
位于相邻两个所述第一p型体区之间的两个栅极沟槽,该两个栅极沟槽之间设有第二p型体区;
所述栅极沟槽内设有栅介质层和栅极。
2.如权利要求1所述的一种半导体功率器件,其特征在于,所述第二p型体区外接源极电压。
3.如权利要求1所述的一种半导体功率器件,其特征在于,所述第二p型体区的宽度小于所述第一p型体区的宽度。
4.如权利要求1所述的一种半导体功率器件,其特征在于,所述栅极沟槽包括上部和下部两部分,所述栅极和所述栅介质层位于所述栅极沟槽的上部内,所述栅极沟槽的下部内设有屏蔽栅和场氧化层。
5.如权利要求4所述的一种半导体功率器件,其特征在于,所述屏蔽栅和所述场氧化层向上延伸至所述栅极沟槽的上部内,所述屏蔽栅通过所述场氧化层与所述栅极隔离。
6.如权利要求5所述的一种半导体功率器件,其特征在于,所述屏蔽栅将所述栅极分割为靠近所述第一p型体区一侧的第一栅极和靠近所述第二p型体区一侧的第二栅极。
7.如权利要求6所述的一种半导体功率器件,其特征在于,所述第一栅极外接栅极电压,所述第二栅极外接源极电压。
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WO2023087714A1 (zh) * | 2021-11-17 | 2023-05-25 | 苏州东微半导体股份有限公司 | 半导体超结功率器件 |
WO2023178865A1 (zh) * | 2022-03-21 | 2023-09-28 | 苏州东微半导体股份有限公司 | 半导体超结功率器件 |
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