CN112424912B - 等离子处理方法 - Google Patents
等离子处理方法 Download PDFInfo
- Publication number
- CN112424912B CN112424912B CN201980005146.6A CN201980005146A CN112424912B CN 112424912 B CN112424912 B CN 112424912B CN 201980005146 A CN201980005146 A CN 201980005146A CN 112424912 B CN112424912 B CN 112424912B
- Authority
- CN
- China
- Prior art keywords
- silicon substrate
- plasma
- processing method
- plasma processing
- gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 54
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 54
- 239000010703 silicon Substances 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 9
- 230000003647 oxidation Effects 0.000 claims abstract description 9
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 4
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 239000001301 oxygen Substances 0.000 claims abstract description 4
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 4
- 239000007789 gas Substances 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 37
- 238000005530 etching Methods 0.000 claims description 32
- 238000002955 isolation Methods 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 claims 2
- 229910052786 argon Inorganic materials 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 239000007795 chemical reaction product Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000009832 plasma treatment Methods 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32137—Radio frequency generated discharge controlling of the discharge by modulation of energy
- H01J37/32146—Amplitude modulation, includes pulsing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32174—Circuits specially adapted for controlling the RF discharge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Ceramic Engineering (AREA)
- Analytical Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Element Separation (AREA)
Abstract
等离子处理方法是在硅基板形成STI的等离子处理方法,其具有:沟道形成工序,使用通过被脉冲调制后的高频电力而生成的等离子,在所述硅基板形成沟道;以及氧化工序,在所述沟道形成工序之后,仅使用氧气来使所述硅基板氧化,将所述沟道形成工序和所述氧化工序重复多次。
Description
技术领域
本发明涉及一种等离子处理方法。
背景技术
近年来,半导体的微细化不断促进,也对器件的构造造成了影响。例如,在以上的晶体管构造中,因伴随着栅极长的缩小的源极漏极间的短通道效应而导致的阈值电压下降变得无法无视。因此,使用了将被称作Fin(以下,也称为fin)(鳍)的源极、漏极电极设置于栅极电极侧壁的Fin FET(Fin-Field Effect Transistor(鳍式场效应晶体管))构造。
在一般的Fin FET中,对与多晶硅栅极电极交叉的Fin进行离子注入而形成源极、漏极电极,控制晶体管的驱动电流。此时,若得不到所期望的Fin的高度,则Fin的面积减少,因此,成为晶体管的驱动电流下降的要因。此外,若对于Fin的侧壁形状产生粗糙度,则器件性能下降,因此,Fin的侧壁要求尽可能接近垂直的形状。
另一方面,在半导体的制造领域中,作为元件隔离技术,使用了浅沟道隔离(Shallow Trench Isolation:以下简称为STI)。在STI中,例如通过各向异性蚀刻,在硅基板形成沟道(也称为蚀刻沟道)。并且,能够将该沟道组合来形成Fin。
然而,在一般的硅基板中形成了:沟道的宽度比较窄小并且沟道设置得比较紧密的区域(以下,简称为密部图案),和沟道宽度宽并且沟道设置的稀疏的区域(以下,简称为疏部图案)。
此外,在通过蚀刻在硅基板形成沟道的工序中,进行蚀刻以使在密部图案以及疏部图案中沟道的深度以及形状相同,这在确保稳定的器件性能方面是必不可少的。然而,若对密部图案以及疏部图案混杂的硅基板进行蚀刻,则在密部图案的蚀刻速度慢,在疏部图案的蚀刻速度快,得不到均一的沟道深度。将该现象称作疏密微负载。
此外,如上述那样,在具有Fin FET构造的器件中,对Fin的硅侧壁要求尽可能接近垂直的形状。
专利文献1中公开了一种通过将第一工序、第二工序和第三工序重复复多次,在硅基板上形成给定深度的沟道的技术。更具体地公开了,在第一工序中使用Cl2气体进行蚀刻,在第二工序中通过Ar气体和CF4气体除去在沟道侧面沉积的沉积物,在第三工序中,通过O2气体和Ar气体的混合气体使沟道侧面以及底面氧化。此外还公开了,将以上三个工序重复多次,由此来减轻疏密微负载。
此外,专利文献2中公开了如下一种等离子蚀刻方法:作为脉冲调制电力的施加方法,等离子通过脉冲调制来控制,基板偏置控制成使脉冲状电力与连续电力重叠。
在先技术文献
专利文献
专利文献1:日本特开2015-50440号公报
专利文献2:日本特开2014-220360号公报
发明内容
-发明要解决的课题-
通过专利文献1所公开的技术对在上表面设置了硬掩模的硅基板进行蚀刻,由此,能够降低疏密微负载。然而,由于专利文献1中公开的处理包含第二工序,因而存在Fin的硅侧壁处产生粗糙度的问题。
图4中表示使用专利文献1的技术进行了蚀刻之后的形状。专利文献1中公开的第二工序是使用了Ar气体和CF4气体的过程,是在除去硅系的反应生成物的目的下进行的。然而,氟与Fin的硅侧壁201的蚀刻有关,成为如图4所示那样产生粗糙度(凹凸)的原因。
为了降低硅侧壁201的粗糙度,需要省略第二工序来重复进行蚀刻,然而,由此,通过第一工序而附着的沉积物的降低变得不充分。
另一方面,专利文献2中公开了通过使用了三氟化氮气体和氧气的混合气体的等离子来除去在沟道的内部沉积的沉积膜的工序。然而,若追加地执行这样的工序,则处理时间变长,因而是不优选的。
本发明的目的在于,提供一种在硅基板的蚀刻中,能够降低硅侧壁的粗糙度并且降低疏密微负载的等离子处理方法。
-用于解决课题的手段-
为了解决上述课题,代表性的本发明的等离子处理方法通过如下而实现,在硅基板形成STI的等离子处理方法中,具有如下步骤:沟道形成工序,使用通过被脉冲调制后的高频电力而生成的等离子,在所述硅基板形成沟道;以及氧化工序,在所述沟道形成工序之后,仅使用氧气来使所述硅基板氧化,将所述沟道形成工序和所述氧化工序重复多次。
-发明效果-
通过本发明,能够提供一种在硅基板的蚀刻中,兼顾硅侧壁的粗糙度的降低和疏密微负载的降低的等离子处理方法。
上述以外的课题、结构以及效果,通过以下的实施方式的说明而变得明确。
附图说明
图1是本实施方式中的等离子蚀刻装置的概略图。
图2是对本实施方式中的半导体的制造工序进行说明的半导体基板的要部剖视图。
图3是本实施方式中的半导体的制造工序中与图2相同的部位的要部剖视图。
图4是现有技术中的半导体的制造工序中与图2相同的部位的要部剖视图。
图5是本实施方式中的半导体的制造工序中与图2相同的部位的要部剖视图。
图6是本实施方式中的半导体的制造工序中与图2相同的部位的要部剖视图。
图7是本实施方式中的半导体的制造工序中与图2相同的部位的要部剖视图。
图8是本实施方式中的半导体的制造工序的流程图。
具体实施方式
以下,参照附图来说明本申请发明的实施方式。图1是表示为了实施本实施方式所涉及的等离子处理方法而使用的等离子处理装置的概略整体结构的剖视图。
等离子处理装置由如下构成:真空处理室101、在该真空处理室101内设置的下部电极(试样台)103、石英等的微波透过窗104、在其上方设置的波导管105、磁控管(等离子产生装置)106、磁控管驱动电源113、在真空处理室101的周围设置的电磁线圈107、与下部电极103连接的静电吸附电源108、基板偏置电源109、和用于控制磁控管驱动电源113以及基板偏置电源109的供给电力的电力控制部114。下部电极103具备对硅基板203进行保持的晶片载置面。
磁控管驱动电源113将等离子产生用电力供给到磁控管106,基板偏置电源109将基板偏置电力供给到下部电极103。
此外,为了将硅基板203送入真空处理室101或者从其送出,设置了晶片送入口110,并设置有用于向真空处理室101供给气体的气体供给口111。
接下来,说明如上述那样构成的等离子处理装置的动作。在将真空处理室101的内部减压之后,将蚀刻气体从气体供给口111供给到真空处理室101内,并调整成所期望的压力。
接着,通过静电吸附电源108施加几百V的直流电压,由此,使硅基板203静电吸附到下部电极103上的配置面。之后,当从磁控管驱动电源113供给等离子产生用电力时(导通时),从磁控管106振荡出频率2.45GHz的微波。该微波经过波导管105而被传播到真空处理室101内。此外,当未供给等离子产生用电力时(截止时),磁控管106停止微波的振荡。
在真空处理室101内,通过电磁线圈107而产生磁场,通过该磁场与振荡出的微波的相互作用,在真空处理室101内生成高密度的等离子112。
在生成等离子112之后,从基板偏置电源109向下部电极103供给高频电力,通过控制等离子中的离子向晶片的入射的能量,能够进行硅基板203的蚀刻处理。
此外,通过对向磁控管106供给的电力进行脉冲调制,能够使脉冲等离子产生。更具体地,若以超过0%且不足100%的占空比将等离子产生用电力导通/截止,则与稳定放电时相比,等离子产生时的电子密度或电子温度、自由基密度变高。此外,将此时产生的等离子称为脉冲等离子。
此外,能够对基板偏置电源109的输出也进行脉冲调制,将脉冲调制后的电力施加给下部电极103。等离子产生用电力或者基板偏置电力通过电力控制部114来控制。
这里,所谓占空比,是指导通时间相对于电力的导通/截止合计时间的比例。
此外,与规格条件相匹配地,等离子产生用电力的占空比能够在15~40%的范围内适当变更,此外,基板偏置电力的占空比能够在5~40%的范围内适当变更。但是,控制成,仅在等离子产生用电力导通时,基板偏置电力导通。
以下,参照图2~图8,来描述使用了该等离子处理装置的STI等离子处理方法的实施方式。如图2所示那样,作为初始构造,在硅基板203上形成硬掩模202。硬掩模202具有:以给定间隔图案化的密部图案DP、和以比密部图案DP宽的间隔图案化的疏部图案SP。密部图案DP中相邻的硬掩模202的间隔是20nm以下,例如10nm左右。
图3中表示通过等离子处理,形成了Fin的硅基板203的形状。形成Fin的工艺如以下那样。
(1)在向真空处理室101内供给Cl2气体来设为0.4Pa以下的压力,并且将用于形成脉冲等离子的等离子产生用电力的占空比设为40%以下的工艺条件下,对硅基板203进行蚀刻(第一工序,图8的步骤S11)。
(2)向真空处理室101内供给SF6和CHF3的混合气体,对硅基板203进行垂直加工处理(第二工序,图8的步骤S12)。这里,所谓垂直加工处理是指对硅基板203的表面加工成大致垂直的处理。
(3)向真空处理室101内供给O2气体,并在设基板偏置电源的功率为5W以下,处理时间为10秒以下的工艺条件下,使硅基板203的表面氧化(第三工序,图8的步骤S13)。
(4)将第一工序至第三工序重复多次,进行蚀刻处理,直至沟道深度成为40nm以上。将重复多次第一工序至第三工序的工序称为形成fin FET的fin的fin形成工序。
在本实施方式中,重复7次第一工序至第三工序来进行蚀刻处理,由此将沟道深度设为65nm。并排形成的沟道之间成为Fin。
此外,在本实施方式中,进行蚀刻处理直至沟道深度成为65nm,然而并不限于此,只要进行蚀刻处理直至能够形成Fin的给定深度即可。
此外,在Fin形成后,基于疏密微负载的沟道深度的差成为25nm,然而在硅侧壁201并未产生粗糙度。在接下来的形成STI的工序中,实施降低疏密微负载的等离子蚀刻处理。
作为本实施方式的等离子蚀刻处理方法,在fin形成工序之后,进一步重复进行:使用脉冲等离子以及Cl2气体的第四工序(沟道形成工序)、和使用基于连续放电的等离子以及仅O2气体的第五工序(氧化工序)。由此,能够不在构成Fin的硅侧壁201产生粗糙度地进行蚀刻处理。
更具体地,说明形成STI的工序。表1中汇总地表示本实施方式中的第四工序以及第五工序所涉及的处理条件的一例。
[表1]
首先,如图5所示那样,第四工序(图8的步骤S14)中,通过使用硬掩模202的蚀刻,在硅基板203形成沟道。作为处理条件,优选使用Cl2气体,并设Cl2气体的流量为200ml/min以下、压力为0.3Pa以下。代表性地,设Cl2气体流量为100ml/min、Ar气体流量为30ml/min、CH4气体为4ml/min以下、压力为0.1Pa。
优选地,一边将脉冲调制后的高频电力供给到载置硅基板203的下部电极103,一边进行第四工序。此外,优选地,用于生成等离子的脉冲调制后的高频电力的占空比大于供给到下部电极103的脉冲调制后的高频电力的占空比。
此外,在本实施方式中,使用了Ar气体,然而还可以置换成He气体或者与其混合,由此,得到与Ar气体单独使用的情况下相同的效果。
这里,设等离子产生用功率为800W、占空比为40%,设基板偏置功率为400W、占空比为25%,通过使等离子产生用电力和基板偏置电力脉冲调制的Dual TM(TimeModulation,时间调制),来使其同步。
此外,在第四工序中,通过Dual TM使其脉冲调制,由此能够抑制沉积物向硬掩模202的附着。此外,通过降低气体压力,蚀刻中的反应生成物减少,在硬掩模202附着的沉积物进一步减少。
因此,如现有技术的第二工序那样的、除去硅系的反应生成物的工序是不需要的,Fin的粗糙度能够降低。此外,若第四工序的处理时间过长,则疏部图案SP的蚀刻容易进行,导致疏密微负载的劣化,因此,第四工序的处理时间设为了8秒。
接下来,如图6所示那样,在第五工序(图8的步骤S15)中,在硬掩模202的侧面以及上表面、以及硅表面形成氧化部分204。通过设置该氧化部分204,当在之后重复执行第四工序时,当进一步在深度方向上蚀刻硅基板203时,能够防止硬掩模202的侧面以及硅侧壁201的蚀刻。
作为第五工序的处理条件,仅使用O2气体,一边利用等离子产生用功率900W的连续波生成等离子,并施加基板偏置功率5W的连续波,一边进行等离子处理。通过施加基板偏置电力,密部图案DP的硅侧壁201容易氧化,防止粗糙度的产生。然而,若施加10W以上,则深度方向的蚀刻被抑制,因此,疏密微负载劣化。因此,基板偏置功率设为了5W的连续波。
优选地,一边将未调制的高频电力供给到下部电极103一边进行第五工序。
在第五工序中,若O2气体的流量大且处理时间长,则在密部图案DP的区域露出的硅表面被过度地氧化,因此,当之后重复执行第四工序时,硅基板203的蚀刻被阻碍。此外,若压力过低,则在疏部图案SP露出的硅表面难以氧化,因此,无法抑制深度方向的蚀刻,成为疏密微负载劣化的原因。因此,O2的气体流量设为了100ml/min以下,设压力为0.8Pa以下,处理时间设为了7秒。
在本实施方式中,第四工序的处理时间设为了8秒,第五工序的处理时间设为了7秒,然而,若每一个处理时间均过长,则成为疏密微负载劣化的原因。因此,第四工序和第五工序优选处理时间为10秒以内,由此,得到同样的效果。
在表1所示的处理条件下,将使用图5(第四工序)、图6(第五工序)说明的两个工序重复进行蚀刻以便成为给定的深度。在本实施方式中,重复5次以使沟道深度成为110nm。
如图7所示那样,基于疏密微负载的沟道深度的差减少至10nm。在本实施方式中,进行蚀刻直至沟道深度成为110nm,然而,优选大多将第四工序和第五工序重复5次以上,由此,能够蚀刻成沟道深度成为110nm以上。
如以上描述的那样,根据本实施方式,通过第四工序在蚀刻中减少了反应生成物,在第五工序中避免对硅表面进行过度保护,由此,能够一边抑制沉积物的沉积,一边实现疏密微负载的降低、和Fin的硅侧壁中的粗糙度的降低的兼顾。
此外,本发明并不限于上述实施方式,包含各种变形例。例如,上述实施方式是为了以易于理解的方式来说明本发明而进行了详细说明,并不必限定为具备所说明的全部结构。此外,能够将某实施方式的结构的一部分替换成其他实施方式的结构,此外,还能够在某实施方式的结构中追加其他实施方式的结构。此外,还能够针对各实施方式的结构的一部分进行其他结构的追加、删除、置换。
-符号说明-
101…真空处理室、102…晶片、103…下部电极、104…微波透过窗、105…波导管、106…磁控管、107…电磁线圈、108…静电吸附电源、109…基板偏置电源、110…晶片送入口、111…气体供给口、112…等离子、113…磁控管驱动电源、201…硅侧壁、202…硬掩模、203…硅基板、204…氧化部分。
Claims (8)
1.一种等离子处理方法,在硅基板形成浅沟道隔离即STI,其特征在于,
所述等离子处理方法具有如下步骤:
形成鳍式场效应晶体管即fin FET的fin的fin形成工序;
沟道形成工序,在fin形成工序后,使用通过脉冲调制后的高频电力而生成的等离子,在fin形成工序后的所述硅基板形成沟道;以及
氧化工序,在所述沟道形成工序之后,仅使用氧气来使所述硅基板氧化,
将所述沟道形成工序和所述氧化工序重复多次,
所述fin形成工序包含:第一工序,使用通过脉冲调制后的高频电力而生成的等离子来对所述硅基板进行蚀刻;第二工序,对所述第一工序后的硅基板进行蚀刻;和第三工序,使用氧气来使所述硅基板氧化,将所述第一工序至所述第三工序重复多次。
2.根据权利要求1所述的等离子处理方法,其特征在于,
所述氧化工序使用基于连续放电的等离子来进行。
3.根据权利要求1或2所述的等离子处理方法,其特征在于,
一边将被脉冲调制后的高频电力供给到载置所述硅基板的试样台,一边进行所述沟道形成工序。
4.根据权利要求3所述的等离子处理方法,其特征在于,
用于生成所述等离子的被脉冲调制后的高频电力的占空比大于供给到所述试样台的脉冲调制后的高频电力的占空比。
5.根据权利要求4所述的等离子处理方法,其特征在于,
使用氯气、甲烷气和氩气的混合气体,来进行所述沟道形成工序。
6.根据权利要求5所述的等离子处理方法,其特征在于,
一边将未被调制的高频电力供给到所述试样台,一边进行所述氧化工序。
7.根据权利要求1至6的任一项所述的等离子处理方法,其特征在于,
所述第一工序是使用氯气而进行的。
8.根据权利要求1至7的任一项所述的等离子处理方法,其特征在于,
所述第二工序是使用SF6气体和CHF3气体而进行的。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2019/024708 WO2020100338A1 (ja) | 2019-06-21 | 2019-06-21 | プラズマ処理方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN112424912A CN112424912A (zh) | 2021-02-26 |
CN112424912B true CN112424912B (zh) | 2024-01-05 |
Family
ID=70730246
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201980005146.6A Active CN112424912B (zh) | 2019-06-21 | 2019-06-21 | 等离子处理方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US11373875B2 (zh) |
JP (1) | JP7000568B2 (zh) |
KR (1) | KR102447235B1 (zh) |
CN (1) | CN112424912B (zh) |
TW (1) | TWI759732B (zh) |
WO (1) | WO2020100338A1 (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20200135898A1 (en) * | 2018-10-30 | 2020-04-30 | International Business Machines Corporation | Hard mask replenishment for etching processes |
CN117769757A (zh) * | 2022-07-25 | 2024-03-26 | 株式会社日立高新技术 | 等离子体处理方法 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001110783A (ja) * | 1999-10-12 | 2001-04-20 | Hitachi Ltd | プラズマ処理装置およびプラズマ処理方法 |
JP2010287823A (ja) * | 2009-06-15 | 2010-12-24 | Denso Corp | 半導体装置の製造方法 |
JP2011211135A (ja) * | 2010-03-31 | 2011-10-20 | Hitachi High-Technologies Corp | プラズマ処理方法 |
US20130026539A1 (en) * | 2011-07-27 | 2013-01-31 | Advanced Ion Beam Technology, Inc. | Replacement source/drain finfet fabrication |
CN103871902A (zh) * | 2014-03-24 | 2014-06-18 | 上海华力微电子有限公司 | 半导体处理工艺及半导体器件的制备方法 |
CN104103486A (zh) * | 2013-04-09 | 2014-10-15 | 株式会社日立高新技术 | 等离子体处理方法以及等离子体处理装置 |
JP2014220360A (ja) * | 2013-05-08 | 2014-11-20 | 株式会社日立ハイテクノロジーズ | プラズマ処理方法 |
JP2015050440A (ja) * | 2013-09-04 | 2015-03-16 | 株式会社日立ハイテクノロジーズ | プラズマ処理方法 |
CN104425339A (zh) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | 用于鳍式场效应晶体管的浅沟槽隔离结构的形成方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101153396B (zh) * | 2006-09-30 | 2010-06-09 | 中芯国际集成电路制造(上海)有限公司 | 等离子刻蚀方法 |
JP5229711B2 (ja) * | 2006-12-25 | 2013-07-03 | 国立大学法人名古屋大学 | パターン形成方法、および半導体装置の製造方法 |
US20110061812A1 (en) * | 2009-09-11 | 2011-03-17 | Applied Materials, Inc. | Apparatus and Methods for Cyclical Oxidation and Etching |
US9324576B2 (en) * | 2010-05-27 | 2016-04-26 | Applied Materials, Inc. | Selective etch for silicon films |
MY188063A (en) * | 2013-12-23 | 2021-11-15 | Intel Corp | Advanced etching techniques for straight, tall and uniform fins across multiple fin pitch structures |
US9240315B1 (en) * | 2014-10-10 | 2016-01-19 | Applied Materials, Inc. | CVD oxide surface pre-conditioning by inductively coupled O2 plasma |
US9966312B2 (en) * | 2015-08-25 | 2018-05-08 | Tokyo Electron Limited | Method for etching a silicon-containing substrate |
US10037890B2 (en) * | 2016-10-11 | 2018-07-31 | Lam Research Corporation | Method for selectively etching with reduced aspect ratio dependence |
-
2019
- 2019-06-21 KR KR1020207009881A patent/KR102447235B1/ko active IP Right Grant
- 2019-06-21 CN CN201980005146.6A patent/CN112424912B/zh active Active
- 2019-06-21 WO PCT/JP2019/024708 patent/WO2020100338A1/ja active Application Filing
- 2019-06-21 US US16/957,835 patent/US11373875B2/en active Active
- 2019-06-21 JP JP2020520673A patent/JP7000568B2/ja active Active
-
2020
- 2020-04-28 TW TW109114150A patent/TWI759732B/zh active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001110783A (ja) * | 1999-10-12 | 2001-04-20 | Hitachi Ltd | プラズマ処理装置およびプラズマ処理方法 |
JP2010287823A (ja) * | 2009-06-15 | 2010-12-24 | Denso Corp | 半導体装置の製造方法 |
JP2011211135A (ja) * | 2010-03-31 | 2011-10-20 | Hitachi High-Technologies Corp | プラズマ処理方法 |
US20130026539A1 (en) * | 2011-07-27 | 2013-01-31 | Advanced Ion Beam Technology, Inc. | Replacement source/drain finfet fabrication |
CN104103486A (zh) * | 2013-04-09 | 2014-10-15 | 株式会社日立高新技术 | 等离子体处理方法以及等离子体处理装置 |
JP2014220360A (ja) * | 2013-05-08 | 2014-11-20 | 株式会社日立ハイテクノロジーズ | プラズマ処理方法 |
CN104425339A (zh) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | 用于鳍式场效应晶体管的浅沟槽隔离结构的形成方法 |
JP2015050440A (ja) * | 2013-09-04 | 2015-03-16 | 株式会社日立ハイテクノロジーズ | プラズマ処理方法 |
CN103871902A (zh) * | 2014-03-24 | 2014-06-18 | 上海华力微电子有限公司 | 半导体处理工艺及半导体器件的制备方法 |
Also Published As
Publication number | Publication date |
---|---|
CN112424912A (zh) | 2021-02-26 |
KR102447235B1 (ko) | 2022-09-27 |
JPWO2020100338A1 (ja) | 2021-02-15 |
TWI759732B (zh) | 2022-04-01 |
US20210066087A1 (en) | 2021-03-04 |
KR20200145823A (ko) | 2020-12-30 |
US11373875B2 (en) | 2022-06-28 |
TW202101585A (zh) | 2021-01-01 |
WO2020100338A1 (ja) | 2020-05-22 |
JP7000568B2 (ja) | 2022-01-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6138653B2 (ja) | ドライエッチング方法 | |
KR102460164B1 (ko) | 에칭 방법 | |
KR101679371B1 (ko) | 드라이 에칭 방법 | |
US9018075B2 (en) | Plasma processing method | |
US20220181162A1 (en) | Etching apparatus | |
CN112424912B (zh) | 等离子处理方法 | |
JP6095528B2 (ja) | プラズマ処理方法 | |
WO2021181613A1 (ja) | プラズマ処理方法 | |
JP6579786B2 (ja) | プラズマエッチング方法 | |
JP2014220360A (ja) | プラズマ処理方法 | |
TWI822106B (zh) | 電漿處理方法及半導體裝置之製造方法 | |
KR20210110657A (ko) | 플라스마 처리 방법 | |
JP5579374B2 (ja) | 半導体加工方法 | |
JP6113608B2 (ja) | プラズマエッチング方法 | |
WO2023203591A1 (ja) | プラズマ処理方法 | |
KR20240016242A (ko) | 플라스마 처리 방법 | |
KR20040080839A (ko) | 반도체 소자의 액티브 영역 손상 방지방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |