CN112416842A - LPC bus-based FARM read-write circuit and method thereof - Google Patents

Abstract

A FARM read-write circuit based on an LPC bus and a method thereof solve the problem of how to effectively and quickly read and write the FARM in a flight control system. The technical scheme of the invention is as follows: the transmission data of the CPU comprises: data signals LAD [3:0], clock signals PCICLK and control signals SERIRQ, LDRQ #, LFRAM # and PCIRST #, wherein the transmission data are communicated with F85266 through an LPC bus, an F85226 protocol chip converts LPC bus signals into a local ISA bus, and a low 18-bit data bus of the local ISA bus reads and writes data of FRAM through an 18-bit address signal, a 16-bit data signal, a read-write enabling signal and a high-low byte selection signal; the invention has the advantage that the implementation scheme of 'infinite-time' data reading and writing of the 512kB large-space memory is solved, and the difficult problem that programming is needed in the conversion process through the FPGA is avoided.

Description

LPC bus-based FARM read-write circuit and method thereof

The technical field is as follows:

the invention relates to the technical field of read-write circuits, in particular to a FARM read-write circuit based on an LPC bus.

Background art:

in an aircraft control system, 512kB data needs to be periodically stored and read in real time, and a pilot needs to detect changes of a flight environment and various condition indexes of an aircraft in real time due to the fact that the change of a natural environment is very constant, so that a device capable of reading data rapidly for a long time needs to be designed.

The FRAM is a random access memory which can carry out 1014 times of reading and writing and completely meets the use requirement. However, how to effectively utilize the FARM and operate the FARM in the flight control system becomes a necessary condition for fast reading and writing, and if the corresponding signals are converted by a certain method and then can be used, the purpose of fast response cannot be achieved. At present, no conversion device or conversion method which can meet the corresponding requirements exists.

In an actual control system, high-speed serial buses such as PCIe, SATA, LPC and the like are mostly used, and signals need to be converted by a certain conversion chip or FPGA and the like for use.

The problem to be solved by the invention is how to effectively and rapidly read and write the FARM in the flight control system.

Disclosure of Invention

The invention aims to solve the problem of how to effectively and quickly perform periodic reading and writing on the FARM in a flight control system.

The invention provides a FARM read-write circuit based on an LPC bus.

The technical scheme of the invention is as follows: the existing high-speed serial bus of the control system is converted into a local bus through an existing protocol conversion chip or FPGA, and the FRAM of 512kB is controlled to read and write for unlimited times.

The transmission data of the CPU comprises: data signals LAD [3:0], clock signals PCICLK and control signals SERIRQ, LDRQ #, LFRAM # and PCIRST #, wherein the transmission data are communicated with F85266 through an LPC bus, an F85226 protocol chip converts LPC bus signals into a local ISA bus, and a low 18-bit data bus of the local ISA bus reads and writes data of FRAM through an 18-bit address signal, a 16-bit data signal, a read-write enabling signal and a high-low byte selection signal;

the reading and writing method of the FARM reading and writing circuit is characterized in that: the method comprises the following steps:

1) the CPU sends the data to be written and the target address to the protocol conversion chip F85226 through the LPC data bus LAD [3:0] for data conversion,

2) because the LPC bus only has 4-bit parallel bus, F85226 splices the data of 5 groups of LPC buses into a group of 18-bit parallel data, and simultaneously splices the address data of 4 groups of LPC buses into a group of 16-bit parallel addresses;

3) after the CPU data is received, the F85226 sets the control signal related to the FRAM writing to an effective state and then writes the data into the target address of the FRAM;

4) FRAM read data flow: the CPU sends the target address of the data to be read to a protocol conversion chip F85226 through a data bus LAD [3:0] for data conversion;

because the LPC bus only has 4-bit parallel bus, F85226 needs to splice the address data of 4 sets of LPC buses into a set of 16-bit parallel addresses;

f85226 sets the control signal related to FRAM reading to be in an effective state after receiving the CPU data, then reads out the data in FRAM according to the target address, and sends the data to CPU through LPC data bus LAD [3:0] after splitting 18bit data into 5 groups of 4bit data.

The invention has the advantages that:

the implementation scheme of the 'infinite-time' data read-write implementation scheme of the 512kB large-space memory is simple, the requirement can be met only by performing data conversion through one standard protocol chip, and the difficult problem that programming is needed in the conversion process through an FPGA (field programmable gate array) is solved.

Drawings

Fig. 1 is a schematic diagram of the wiring connection of the present invention.

Detailed Description

As shown in fig. 1, in the implementation scheme of the present invention, the system CPU communicates with the protocol conversion chip F85226 through the LPC bus, and the communication signals mainly include data signal LAD [3:0], clock signal PCICLK, and control signals SERIRQ, LDRQ #, LFRAM # and PCIRST #, etc. The F85226 protocol chip may convert LPC bus signals to a local ISA bus, which contains a 20-bit address bus. The invention only uses ISA bus lower 18 data bus according to actual demand. The local ISA bus reads and writes data of the FRAM through an 18-bit address signal, a 16-bit data signal, a read-write enabling signal and a high-low byte selection signal. The FRAM chip is selected from FM22L16-55-TG of Cypress company.

The system read-write data work flow is as follows:

data writing flow of FRAM: the CPU sends the data to be written and the target address to a protocol conversion chip F85226 through an LPC data bus LAD [3:0] for data conversion, and because the LPC bus only has 4-bit parallel buses, the F85226 needs to splice 5 groups of data of the LPC bus into a group of 18-bit parallel data, and simultaneously splices 4 groups of address data of the LPC bus into a group of 16-bit parallel addresses. F85226 sets FRAM write-related control signals to an active state after receiving the completion CPU data, and then writes the data into the target address of the FRAM.

FRAM read data flow: the CPU sends the target address of the data to be read to the protocol conversion chip F85226 through a data bus LAD [3:0] for data conversion, and because the LPC bus only has 4-bit parallel bus, the F85226 needs to splice the address data of 4 groups of LPC buses into a group of 16-bit parallel addresses. F85226 sets the control signal related to FRAM reading to be in an effective state after receiving the CPU data, then reads out the data in FRAM according to the target address, and sends the data to CPU through LPC data bus LAD [3:0] after splitting 18bit data into 5 groups of 4bit data.

Claims (2)

1. An LPC bus based FARM read-write circuit, comprising: f85266, FARM, CPU and LPC bus, characterized by:

the transmission data of the CPU comprises: data signal LAD [3:0], clock signal PCICLK and control signals SERIRQ, LDRQ #, LFRAM # and PCIRST #, the above-mentioned transmission data are communicated with F85266 by LPC bus, F85226 protocol chip converts LPC bus signal into local ISA bus, the low 18bit data bus of the local ISA bus reads and writes data for FRAM by 18bit address signal, 16bit data signal, read-write enable signal and high-low byte selection signal.

2. A read-write method of a FARM read-write circuit based on an LPC bus is characterized in that: the method comprises the following steps:

1) the CPU sends the data to be written and the target address to the protocol conversion chip F85226 through the LPC data bus LAD [3:0] for data conversion,

2) because the LPC bus only has 4-bit parallel bus, F85226 splices the data of 5 groups of LPC buses into a group of 18-bit parallel data, and simultaneously splices the address data of 4 groups of LPC buses into a group of 16-bit parallel addresses;

3) after the CPU data is received, the F85226 sets the control signal related to the FRAM writing to an effective state and then writes the data into the target address of the FRAM;

4) FRAM read data flow: the CPU sends the target address of the data to be read to a protocol conversion chip F85226 through a data bus LAD [3:0] for data conversion;

because the LPC bus only has 4-bit parallel bus, F85226 needs to splice the address data of 4 sets of LPC buses into a set of 16-bit parallel addresses;

5) f85226 sets the control signal related to FRAM reading to be in an effective state after receiving the CPU data, then reads out the data in FRAM according to the target address, and sends the data to CPU through LPC data bus LAD [3:0] after splitting 18bit data into 5 groups of 4bit data.

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