CN111177027A - Dynamic random access memory, memory management method, system and storage medium - Google Patents
Dynamic random access memory, memory management method, system and storage medium Download PDFInfo
- Publication number
- CN111177027A CN111177027A CN201911121076.9A CN201911121076A CN111177027A CN 111177027 A CN111177027 A CN 111177027A CN 201911121076 A CN201911121076 A CN 201911121076A CN 111177027 A CN111177027 A CN 111177027A
- Authority
- CN
- China
- Prior art keywords
- central processing
- processing unit
- area
- instruction set
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Dram (AREA)
Abstract
The invention provides a dynamic random access memory, a memory management method, a system and a storage medium, wherein the dynamic random access memory comprises a circuit substrate, a DRAM chip set, a first memory controller, a second memory controller, a first interface, a second interface and a storage interface set, wherein the DRAM chip set, the first memory controller, the second memory controller, the first interface, the second interface and the storage interface set are integrated on the circuit substrate; the first memory controller is respectively connected with the first interface, the DRAM chip set and the storage interface set; the second memory controller is respectively connected with the second interface, the DRAM chip set and the storage interface set. The invention can enable a plurality of central processing units to be in an efficient operation state all the time, is suitable for the fields of cloud computing and the like, and can greatly improve the operation efficiency of the system.
Description
Technical Field
The present invention relates to the field of computers, and more particularly, to a dynamic random access memory, a memory management method, a system and a storage medium.
Background
At present, the technology of DRAM (Dynamic Random Access Memory) has been greatly developed, and various types of SDRAM (synchronous Dynamic Random Access Memory), Double Data Rate (DDR) SDRAM, double data rate generation 2 (DDR2) SDRAM, double data rate generation 3 (DDR3) SDRAM, and double data rate generation 4 (DDR4) SDRAM are mainly used. For the DRAM of the above type, a memory controller and a DRAM chip (i.e., a memory granule) are generally used, and a Central Processing Unit (CPU) sends control commands including clock signals, command control signals, address signals and the like to the DRAM chip via the memory controller, and controls the read/write operations of data signals to the DRAM chip through the control commands.
When the computer system executes the program, the relevant program and data executed by the CPU need to be put into the DRAM, when the program is executed, the CPU fetches an instruction from the DRAM according to the content of the current program pointer register and executes the instruction, then fetches the next instruction and executes the next instruction, and the execution is not stopped until the program finishes the instruction. The working process is the process of continuously fetching and executing the instruction, and finally, the calculated result is put into the memory address appointed by the instruction.
However, since the cost of the DRAM is high and the storage capacity of the DRAM is limited, most programs are stored in a mass storage device with relatively low cost, such as a hard disk, a solid state disk, and the like, and when the computer runs, the CPU needs to move data in the mass storage device to the DRAM and write data of the DRAM into the mass storage device. Moreover, the interaction speed between the mass storage device and the central processing unit is much lower than that between the central processing unit and the DRAM, so that the overall operation efficiency of the computer system is greatly influenced.
Disclosure of Invention
The present invention provides a dynamic random access memory, a memory management method, a system and a storage medium, aiming at the problem that the operating efficiency is affected by the interaction speed between a central processing unit and a mass storage device in the computer system.
The present invention provides a dynamic random access memory, which comprises a circuit substrate, a DRAM chipset integrated on the circuit substrate, a first memory controller, a second memory controller, a first interface for connecting to a first central processing unit, a second interface for connecting to a second central processing unit, and a storage interface set for connecting to a mass storage device set;
the first memory controller is respectively connected with the DRAM chip set and the first interface, responds to a read-write request of a first central processing unit connected to the first interface, acquires a first instruction set from the DRAM chip set, is connected to the first central processing unit through first interface data, and writes execution result data of the first central processing unit into the DRAM chip set; the first memory controller is also connected with the storage interface group, and when the first instruction set read by the first central processing unit in the DRAM chipset meets a first preset condition, the first memory controller acquires a first subsequent instruction set of the first instruction set in the DRAM chipset from a mass storage device group through the storage interface group and stores the first subsequent instruction set to the DRAM chipset;
the second memory controller is respectively connected with the DRAM chip set and the second interface, responds to a read-write request of a second central processing unit connected to the second interface, acquires a second instruction set from the DRAM chip set, is connected to the second central processing unit through second interface data and writes execution result data of the second central processing unit into the DRAM chip set; the second memory controller is further connected with the storage interface group, and when the second instruction set which is read by the second central processing unit in the DRAM chipset is waited to meet a second preset condition, the second memory controller acquires a second subsequent instruction set of the second instruction set in the DRAM chipset from a mass storage device group through the storage interface group and stores the second subsequent instruction set in the DRAM chipset.
Preferably, the DRAM chipset comprises a first private storage area and a second private storage area;
the first private storage area comprises at least two first logic storage areas which are a main mapping area and a standby mapping area, the first logic storage area where a first instruction set currently read by the first central processing unit is located is the main mapping area, and the other first logic storage areas are the standby mapping areas; the first preset condition is as follows: the number of the first instruction sets to be read in the first logic storage area serving as the main mapping area is smaller than a preset value, or the time for the first instruction sets to be read in the first logic storage area serving as the main mapping area to be executed in the first central processing unit is smaller than a preset time;
the second private storage area comprises at least two second logic storage areas which are a main mapping area and a standby mapping area, the second logic storage area where the second instruction set currently read by the second central processing unit is located is the main mapping area, and the other second logic storage areas are the standby mapping areas; the second preset condition is as follows: the number of the second instruction sets to be read in the second logic storage area as the main mapping area is smaller than a preset value, or the time for the second instruction sets to be read in the second logic storage area as the main mapping area to be executed in the second central processing unit is smaller than a preset time.
Preferably, the mass storage device group includes a first mass storage and a second mass storage; the storage interface group comprises a first storage interface used for connecting a first mass storage and a second storage interface used for connecting a second mass storage, and instruction sets stored in the first mass storage and the second mass storage are mutually independent; the DRAM chipset comprises a common storage area;
the first memory controller reads shared data from the public storage area according to the shared data read-write request of the first central processing unit, and writes the shared data generated by the first central processing unit when executing a first instruction set into the public storage area;
and the second memory controller reads the shared data from the public storage area according to the shared data read-write request of the second central processing unit and writes the shared data generated by the second central processing unit when executing the second instruction set into the public storage area.
Preferably, the mass storage device set comprises a third mass storage, and the storage interface set comprises a third storage interface for connecting the third mass storage; the first memory controller and the second memory controller are respectively connected with the third mass storage through the third storage interface;
said first central processing unit executing a first instruction set acquired from a first logical memory area as a main map area on the material input through an input terminal of said first central processing unit and updating said first logical memory area according to the execution result or outputting the execution result through an output terminal of said first central processing unit;
said second central processing unit executing a second instruction set from said second logical memory area in response to the data input from the input terminal of said second central processing unit and updating said second logical memory area in accordance with the execution result, or outputting the execution result through the output terminal of said second central processing unit.
Preferably, the sizes of the at least two first logical storage areas are equal, and the size of the subsequent instruction set acquired by the first memory controller is equal to that of the first logical storage area; the sizes of the at least two second logic storage areas are equal, and the sizes of the subsequent instruction sets acquired by the second memory controller and the second logic storage areas are equal;
before storing a first subsequent instruction set of a first instruction set in a first logic storage area as a main mapping area into a standby mapping area of a first private storage area, if original contents of the standby mapping area of the first private storage area are updated, the first memory controller writes contents in the standby mapping area of the first private storage area back to an original address of the mass storage device;
before storing a second subsequent instruction set of a second instruction set in a second logic storage area as a main mapping area into a standby mapping area of a second private storage area, if the original content of the standby mapping area of the second private storage area is updated, the second memory controller writes the content in the standby mapping area of the second private storage area back to the original address of the mass storage device.
Preferably, the first interface and the second interface are both DRAM interfaces;
the storage interface group comprises at least one PCIE interface, and the mass storage device group is connected to the storage interface group through a PCIE bus; or, the mass storage device group is composed of a mass flash memory chip group integrated to the circuit substrate, and the mass flash memory chip group is connected to the first memory controller and the second memory controller through the storage interface group.
An embodiment of the present invention further provides a memory management method, where the memory includes a DRAM chipset, and the memory is connected to a first central processing unit through a first interface, connected to a second central processing unit through a second interface, and connected to a large-capacity storage device group through a storage interface group, and the method includes:
responding to a read-write request of a first central processing unit connected to the first interface, acquiring a first instruction set from the DRAM chipset, connecting the first instruction set to the first central processing unit through first interface data, and writing execution result data of the first central processing unit into the DRAM chipset;
when a first instruction set read by a first central processing unit in the DRAM chipset meets a first preset condition, acquiring a first subsequent instruction set of the first instruction set in the DRAM chipset from a mass storage device group through the storage interface group, and storing the first subsequent instruction set to the DRAM chipset;
responding to a read-write request of a second central processing unit connected to the second interface, acquiring a second instruction set from the DRAM chipset, connecting the second instruction set to the second central processing unit through second interface data, and writing execution result data of the second central processing unit into the DRAM chipset;
when a second instruction set which is waited to be read by a second central processing unit in the DRAM chipset meets a second preset condition, a second subsequent instruction set of the second instruction set in the DRAM chipset is obtained from a mass storage device group through the storage interface group, and the second subsequent instruction set is stored in the DRAM chipset.
Preferably, the DRAM chipset comprises a first private storage area and a second private storage area, the DRAM chipset comprises a public storage area;
the first private storage area comprises at least two first logic storage areas which are a main mapping area and a standby mapping area, the first logic storage area where a first instruction set currently read by the first central processing unit is located is the main mapping area, and the other first logic storage areas are the standby mapping areas; the first preset condition is as follows: the number of the first instruction sets to be read in the first logic storage area serving as the main mapping area is smaller than a preset value, or the time for the first instruction sets to be read in the first logic storage area serving as the main mapping area to be executed in the first central processing unit is smaller than a preset time;
the second private storage area comprises at least two second logic storage areas which are a main mapping area and a standby mapping area, the second logic storage area where the second instruction set currently read by the second central processing unit is located is the main mapping area, and the other second logic storage areas are the standby mapping areas; the second preset condition is as follows: the number of the second instruction sets to be read in the second logic storage area serving as the main mapping area is smaller than a preset value, or the time for the second instruction sets to be read in the second logic storage area serving as the main mapping area to be executed in the second central processing unit is smaller than preset time;
the method further comprises the following steps:
reading shared data from the public storage area according to a shared data read-write request of the first central processing unit, and writing the shared data generated by the first central processing unit when executing a first instruction set into the public storage area;
reading shared data from the public storage area according to the shared data read-write request of the second central processing unit, and writing the shared data generated by the second central processing unit when executing a second instruction set into the public storage area;
before storing a first subsequent instruction set of a first instruction set in a first logic storage area as a main mapping area into a standby mapping area of a first private storage area, if original contents of the standby mapping area of the first private storage area are updated, the first memory controller writes contents in the standby mapping area of the first private storage area back to an original address of the mass storage device;
before storing a second subsequent instruction set of a second instruction set in a second logic storage area as a main mapping area into a standby mapping area of a second private storage area, if the original content of the standby mapping area of the second private storage area is updated, the second memory controller writes the content in the standby mapping area of the second private storage area back to the original address of the mass storage device.
The present invention also provides a computer system, including a central processing unit and a dynamic random access memory, wherein the dynamic random access memory includes a circuit substrate, and a DRAM chipset integrated on the circuit substrate, a first memory controller, a second memory controller, a first interface for connecting the first central processing unit, a second interface for connecting the second central processing unit, and a storage interface group interface for connecting a mass storage device group, the dynamic random access memory further includes a storage unit and a computer program stored in the storage unit and operable on the first memory controller and the second memory controller, and the first memory controller and the second memory controller implement the steps of the memory management method when executing the computer program.
The present invention also provides a computer readable storage medium, storing a computer program which, when executed by a processor, implements the steps of the memory management method as described above.
The dynamic random access memory, the memory management method, the system and the storage medium of the invention directly update the content in the DRAM chip set according to the instruction set which is executed by the central processing unit through the memory controller, so that the central processing unit does not need to interact with a large-capacity storage device, the central processing unit can be always in a high-efficiency running state, the invention is suitable for a system with a plurality of central processing units, and the running efficiency of the system can be greatly improved.
Drawings
FIG. 1 is a diagram of a DRAM according to an embodiment of the present invention;
FIG. 2 is a diagram of the interaction of the DRAM with the CPU and the mass storage device according to the present invention;
FIG. 3 is a diagram of the interaction between the DRAM and the CPU and the mass storage device according to another embodiment of the present invention;
FIG. 4 is a diagram of the interaction of a DRAM with a CPU and a mass storage device according to yet another embodiment of the present invention;
fig. 5 is a flowchart illustrating a memory management method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 is a schematic diagram of a dynamic random access memory according to an embodiment of the present invention, which can be applied to a computer system having a plurality of central processing units, such as a cloud server, and is used for temporarily storing programs and data executed by the plurality of central processing units. The dynamic random access memory of the present embodiment includes a circuit substrate 10, and a first memory controller 11, a second memory controller 12, a DRAM chipset 13, a first interface 14, a second interface 15, and a memory interface set 16 integrated on the circuit substrate 10. The DRAM chipset 13 may specifically include a plurality of DRAM chip particles.
The first interface 14 and the second interface 15 can be DRAM interfaces, respectively, and the DRAM can interact with the first cpu at a high speed through the first interface 14, and can interact with the second cpu at a high speed through the second interface 15. That is, the dram can be applied to a computer system having two cpu units, and the two cpu units can have the same or different data processing capabilities. Of course, in practical applications, the substrate 10 may further include more interfaces for connecting to the cpu and corresponding memory controllers, so as to be applied to systems with more cpus.
The storage interface set 16 may include one or more PCIE (peripheral component interconnect express) interfaces, and a dynamic random access memory (dram) or a mass storage device set may be connected through the storage interface set 16, and the mass storage device set may include a Solid State Disk (SSD) or a Hard Disk Drive (HDD).
In the circuit substrate 10, the first memory controller 11 is respectively connected to the DRAM chipset 13 and the first interface 14, and in response to a read/write request of a first central processing unit connected to the first interface 14, acquires a first instruction set from the DRAM chipset 13, connects to the first central processing unit through first interface data, and writes execution result data of the first central processing unit to the DRAM chipset (i.e., data interaction between the first central processing unit and the DRAM chipset 13 is realized, and specifically, the first central processing unit may acquire the instruction set from the DRAM chipset 11 according to a program pointer and execute the instruction set). The first memory controller 11 is also connected to the memory interface set 16 and enables the interaction of the DRAM chipset 13 with data in the mass storage device set connected to the memory interface set 16. Specifically, when a first instruction set (including instruction codes and data) waiting for being read by a first central processing unit in the DRAM chipset 13 meets a first preset condition, a first subsequent instruction set (including instruction codes and data) of the first instruction set in the DRAM chipset 13 is obtained from the mass storage device group through the storage interface group 16, and the first subsequent instruction set is stored into the DRAM chipset 13.
The second memory controller 12 is respectively connected to the DRAM chipset 13 and the second interface 15, and in response to a read/write request of a second central processing unit connected to the second interface 15, acquires a second instruction set from the DRAM chipset 13, connects to the second central processing unit through second interface data, and writes execution result data of the second central processing unit into the DRAM chipset 13 (i.e. implementing interaction between the second central processing unit and the DRAM chipset 13, specifically, the second central processing unit may acquire the instruction set from the DRAM chipset 13 according to a program pointer and execute the instruction set). The second memory controller 12 is also coupled to the memory interface set 16 and enables the interaction of the DRAM chipset 13 with data in the mass storage device set coupled to the memory interface set 16. Specifically, when a second instruction set (including instruction codes and data) waiting for being read by a second central processing unit in the DRAM chipset 13 meets a second preset condition, a second subsequent instruction set (including instruction codes and data) of the second instruction set in the DRAM chipset is obtained from the mass storage device group through the storage interface group 16, and the second subsequent instruction set is stored to the DRAM chipset 13.
The dynamic random access memory updates the content in the DRAM chipset 13 according to the instruction set being executed by the first central processing unit and the second central processing unit through the first memory controller 11 and the second memory controller 12, respectively, so that the dynamic random access memory can be automatically updated according to the operating state of each central processing unit, and thus the storage capacity of the dynamic random access memory is nearly infinite, each central processing unit does not need to interact with a large-capacity storage device, so that the central processing unit can always be in a high-efficiency operating state, and the dynamic random access memory is suitable for the fields of cloud computing and the like with higher requirements on computing resources, and can greatly improve the operating efficiency of the system.
In one embodiment of the present invention, as shown in fig. 2, the DRAM chipset 13 includes a first private storage area 131 and a second private storage area 132.
The first private storage area 131 includes two first logic storage areas that are a main mapping area and a standby mapping area, which are each other, and the two first logic storage areas are respectively a section of storage space in the DRAM chipset 13 and are respectively used for caching a first instruction set for processing by the first central processing unit 21, and the first central processing unit 21 also writes an execution result of the first instruction set into the first logic storage area. The first logical storage area where the instruction set currently read by the first central processing unit 21 is located is a main mapping area, and the other first logical storage area is a standby mapping area. The first instruction sets stored in the main mapping area and the standby mapping area are respectively from the mass storage device group, and the stored first instruction sets respectively correspond to a certain section of first instruction set in the mass storage device group, that is, the main mapping area and the standby mapping area correspond to two "windows" of the mass storage device group, and the first central processing unit 21 can obtain the first instruction set stored in the mass storage device group through the two "windows". The content shown in the "window" is controlled by the first memory controller 11 of the dram. Of course, in practical applications, the first private storage area 131 may include more first logical storage areas, and one of the first logical storage areas is a main mapping area, and the other first logical storage areas are standby mapping areas.
The two first logical memory areas can switch the main mapping area and the standby mapping area according to the program pointer executed by the first central processing unit 21. Specifically, the first cpu 21 may obtain the first instruction set from the host map area through the first interface 14 and the first memory controller 11 according to a Program address specified by a Program Counter (Program Counter). Under normal conditions, when the program counter finishes executing one instruction set, the original address +1 is automatically used as the program address of the next instruction set, so that the first CPU 21 obtains the next first instruction set from the main mapping area according to the updated program address; if the first CPU 21 executes the jump instruction, the program counter uses the original address + n or-n as the program address of the next first instruction set according to the jump value n, and the first CPU 21 obtains the next instruction set from the main mapping area according to the updated program address. When the program address specified by the program counter is located in the standby mapping area, the main mapping area and the standby mapping area complete the switch.
Preferably, the first preset condition may be (i.e. the first memory controller 11 may update the contents of the DRAM chipset 13 as follows): when the number of the first instruction sets waiting for being read by the first central processing unit 21 in the first logical storage area as the main mapping area is smaller than the preset value, or the time for executing the first instruction sets waiting for being read in the first central processing unit 21 in the first logical storage area as the main mapping area is smaller than the preset time, the first memory controller 11 acquires the first subsequent instruction set of the first instruction set in the DRAM chipset 13 from the mass storage device group through the storage interface group 16, and stores the first subsequent instruction set in the DRAM chipset 13 (meanwhile, the pointer is adjusted according to the first instruction set in the first logical storage area as the main mapping area and the updated first instruction set in the first logical storage area as the standby mapping area, so that the first central processing unit 21 can read the first instruction sets in sequence). In this way, the first instruction set in the dram can be updated in time, so that the instruction execution of the first cpu 21 is not affected. Moreover, by controlling the first preset condition, even if the capacity of the first logic storage area is small, the efficient operation of the first central processing unit 21 is not affected, and the resources of the DRAM chipset 13 are saved.
Specifically, when the first instruction set waiting for being read by the first central processing unit 21 in the DRAM chipset 13 does not contain a jump instruction, or the first instruction set waiting for being read by the first central processing unit 21 in the DRAM chipset 13 contains a jump instruction and the first instruction set pointed by the jump instruction is still in the DRAM chipset 13, the subsequent first instruction set starts from the next instruction of the last instruction of the first logical storage area as the main map area in the DRAM chipset 13; when the first instruction set waiting for being read by the second cpu 21 in the DRAM chipset 13 includes a jump instruction and the first instruction set pointed to by the jump instruction is not in the DRAM chipset 13, the first subsequent instruction set starts from the instruction pointed to by the jump instruction.
For management, the two first logical storage areas may be equal in size (i.e., equal in storage space), and the first memory controller 11 obtains the first subsequent instruction set and the first logical storage area with equal sizes. By the above manner, the access efficiency of the first memory controller 21 can be improved.
Similarly, the second private storage area 132 includes two second logic storage areas that are a main mapping area and a standby mapping area, which are each other, and the two second logic storage areas are respectively a section of storage space in the DRAM chipset 13 and are respectively used for caching a second instruction set for processing by the second central processing unit 22, and the second central processing unit 22 also writes an execution result of the second instruction set into the second logic storage areas. The second logical storage area where the instruction set currently read by the second central processing unit 22 is located is a main mapping area, the other first logical storage area is a standby mapping area, and the two second logical storage areas can switch the main mapping area and the standby mapping area according to the program pointer executed by the second central processing unit 22. The second instruction sets stored in the main mapping area and the standby mapping area are respectively from the mass storage device group, and the second instruction sets stored in the main mapping area and the standby mapping area respectively correspond to a certain section of second instruction set in the mass storage device group, that is, the main mapping area and the standby mapping area are equivalent to two "windows" of the mass storage device group, and the second central processing unit 22 can obtain the first instruction set stored in the mass storage device group through the two "windows". The content shown in the "window" is controlled by the second memory controller 12 of the dram. Of course, in practical applications, the second private storage area 132 may include more second logical storage areas, and one of the second logical storage areas is a main mapping area, and the other second logical storage areas are standby mapping areas.
The two second logical storage areas can switch the main mapping area and the standby mapping area according to the program pointer executed by the second cpu 22, and the switching manner is similar to that of the two first logical storage areas, and thus the description thereof is omitted.
Since the first cpu 21 writes the execution result into the first logical storage area when executing the first instruction set, before storing the first subsequent instruction set of the first instruction set in the first logical storage area as the main mapping area into the first logical storage area as the standby mapping area, if the original content of the first logical storage area as the standby mapping area is updated (i.e. the first cpu 21 writes the execution result of the first instruction set), the first memory controller 11 needs to write back the content in the first logical storage area as the standby mapping area (the result updated by the first cpu 21) to the original address of the mass storage device group. That is, before storing the first subsequent instruction set in the first logical storage area serving as the standby mapping area, the first memory controller 11 first determines whether the content of the first logical storage area serving as the standby mapping area is updated, and if not, directly stores the first subsequent instruction set in the first logical storage area serving as the standby mapping area, otherwise, writes the content (i.e., the updated content) in the first logical storage area serving as the standby mapping area back to the original address of the mass storage device group, and then stores the first subsequent instruction set in the first logical storage area serving as the standby mapping area.
Preferably, the second preset condition may be (i.e. the second memory controller 12 may update the contents of the DRAM chipset 13 as follows): when the number of the second instruction sets waiting for being read by the second central processing unit 22 in the second logical storage area as the main mapping area is smaller than the preset value, or the time for executing the second instruction sets waiting for being read in the second central processing unit 22 in the second logical storage area as the main mapping area is smaller than the preset time, the second memory controller 12 acquires a second subsequent instruction set of the second instruction set in the DRAM chipset 13 from the mass storage device group through the storage interface group 16, and stores the second subsequent instruction set to the DRAM chipset 13. In this way, the second instruction set in the dram can be updated in time, so that the instruction execution of the second cpu 22 is not affected. Moreover, by controlling the second preset condition, even if the capacity of the second logic storage area is small, the efficient operation of the second central processing unit 22 is not affected, and the resources of the DRAM chipset 13 are saved.
Specifically, when the second instruction set waiting for being read by the second central processing unit 22 in the DRAM chipset 13 does not contain a jump instruction, or the second instruction set waiting for being read by the second central processing unit 22 in the DRAM chipset 13 contains a jump instruction and the second instruction set pointed by the jump instruction is still in the DRAM chipset 13, the subsequent second instruction set starts from the next instruction of the last instruction of the second logical storage area as the main mapping area in the DRAM chipset 13; when the second instruction set waiting for being read by the second cpu 22 in the DRAM chipset 13 includes a jump instruction and the second instruction set pointed to by the jump instruction is not in the DRAM chipset 13, the second subsequent instruction set starts from the instruction pointed to by the jump instruction.
For management, the two second logical storage areas may be equal in size (i.e., equal in storage space), and the second memory controller 12 obtains the second subsequent instruction set and the second logical storage area with equal sizes. By the above manner, the access efficiency of the second memory controller 22 can be improved. And similar to the first memory controller 11, if the original content of the second logical storage area as the standby mapping area has been updated, the second memory controller 12 needs to write the content of the second logical storage area as the standby mapping area back to the original address of the mass storage device group.
In another embodiment of the present invention, the mass storage device group may specifically include a first mass storage 31 and a second mass storage 32, and correspondingly, the storage interface group 16 may include a first storage interface for connecting the first mass storage 31 and a second storage interface for connecting the second mass storage 32, and the instruction sets stored in the first mass storage 31 and the second mass storage 32 are independent from each other (i.e. the first mass storage 31 stores a first instruction set, and the second mass storage 32 stores a second instruction set). And the DRAM chipset 13 further includes a common storage area 133, the common storage area 133 may also buffer data. The first memory controller 11 may read the shared data from the common storage area 133 according to the shared data read/write request of the first central processing unit 21, and write the shared data generated by the first central processing unit 21 when executing the first instruction set into the common storage area 133; similarly, the second memory controller 12 may read the shared data from the common storage area 133 according to the read/write request of the shared data from the second central processing unit 22, and write the shared data generated by the second central processing unit 22 when executing the second instruction set into the common storage area 133. In the above manner, the cooperative work of the first central processing unit 21 and the second central processing unit 22 can be realized.
As shown in fig. 3, the mass storage device group may only include one mass storage, i.e. the third mass storage 33, and correspondingly, the storage interface group 16 also includes only one third storage interface for connecting the third mass storage 33; the first memory controller 11 and the second memory controller 12 are connected to the third mass storage 33 via a third storage interface, respectively. At this time, the first central processing unit 21 can execute the first instruction set (obtained from the first logical memory area as the main map area) on the material inputted through its input terminal and update the first logical memory area as the main map area according to the execution result, or output the execution result through its output terminal; the second cpu 21 executes a second set of instructions (from the second logical memory area as the main map area) on the data inputted at its input terminal and updates the second logical memory area as the main map area according to the execution result, or outputs the execution result through its output terminal.
Compared to the way in which the mass storage device group includes two independent memories, since the dynamic random access memory is connected to the third mass storage 33 through only one interface, the content update speed in the DRAM chipset 33 may be affected, and accordingly, the processing efficiency of the first central processing unit 21 and the second central processing unit 22 may be affected.
Furthermore, as shown in fig. 4, when the DRAM is connected to the third mass storage 33 only through a third storage interface, the DRAM chipset 33 may also include a common storage area 134 for the first central processing unit 21 and the second central processing unit 22 to work together. The first memory controller 11 may read the shared data from the common storage area 134 according to the shared data read/write request of the first central processing unit 21, and write the shared data generated by the first central processing unit 21 when executing the first instruction set into the common storage area 134; similarly, the second memory controller 12 can read the shared data from the common storage area 134 and write the shared data generated by the second central processing unit 22 when executing the second instruction set into the common storage area 134 according to the read/write request of the shared data from the second central processing unit 22.
In an embodiment of the present invention, the mass storage device set may also be integrated into the dynamic random access memory, for example, the mass storage device set may be formed by mass flash memory chips integrated onto the circuit substrate 10, and the mass flash memory chips are connected to the first memory controller 11 and the second memory controller 12 through the storage interface set 16, in which case the storage interface set 16 may adopt a PCIE interface or other high-speed interface to improve data throughput efficiency.
As shown in fig. 5, an embodiment of the present invention further provides a memory management method, where the memory may be a dynamic random access memory, and the memory includes a DRAM chipset 11, and the memory is connected to the first central processing unit through a first interface, connected to the second central processing unit through a second interface, and connected to the mass storage device through a storage interface set. The method of the present embodiment may be executed by a memory controller (e.g., two mutually independent memory controllers) in a memory, and the method includes:
step S51; in response to a read/write request of a first central processing unit connected to the first interface, a first instruction set is obtained from the DRAM chipset and is connected to the first central processing unit through first interface data, and execution result data of the first central processing unit is written into the DRAM chipset.
The DRAM chipset may include a first private storage area, and the first private storage area may include two first logical storage areas that are a master mapping area and a standby mapping area for each other, where a first logical storage area where a first instruction set read to the first central processing unit is located is the master mapping area, and the other first logical storage area is the standby mapping area, and the two second logical storage areas switch the master mapping area and the standby mapping area according to a program pointer executed by the first central processing unit. Of course, in practical applications, the DRAM chipset may include more first logical storage areas, and one of the first logical storage areas is a main mapping area, and the other second logical storage areas are standby mapping areas.
The first instruction sets stored in the main mapping area and the standby mapping area are respectively from the mass storage device group, and the stored first instruction sets respectively correspond to a certain section of first instruction set in the mass storage device group, namely the main mapping area and the standby mapping area are equivalent to two windows of the mass storage device group, and the first central processing unit can acquire the first instruction sets stored in the mass storage device group through the two windows. The content shown in the "window" is controlled by the dynamic random access memory.
Step S52; when the first instruction set read by the first central processing unit in the DRAM chipset meets a first preset condition, a first subsequent instruction set of the first instruction set in the DRAM chipset is obtained from the mass storage device group through the storage interface group, and the first subsequent instruction set is stored in the DRAM chipset.
The first preset condition may be: the number of the first instruction sets to be read in the first logic storage area as the main mapping area is smaller than a preset value, or the time for the first instruction sets to be read in the first logic storage area as the main mapping area to be executed in the first central processing unit is smaller than a preset time. In this step, before the first subsequent instruction set is stored in the first logical storage area as the spare map area, if the original content of the first logical storage area as the spare map area is updated (by the first cpu), the content in the first logical storage unit as the spare map area needs to be written back to the original address of the mass storage device group.
Step S53; and in response to the read-write request of the second central processing unit connected to the second interface, acquiring a second instruction set from the DRAM chipset, connecting the second instruction set to the second central processing unit through the second interface data, and writing the execution result data of the second central processing unit into the DRAM chipset.
The DRAM chipset may further include a second private storage area, and the second private storage area may include two second logical storage areas that are a main mapping area and a standby mapping area for each other, where the second logical storage area where the second instruction set read to the second central processing unit is located is the main mapping area, and the other second logical storage area is the standby mapping area, and the two second logical storage areas switch the main mapping area and the standby mapping area according to a program pointer executed by the second central processing unit. Of course, in practical applications, the DRAM chipset may include more second logical storage areas, and one of the second logical storage areas is a main mapping area, and the other second logical storage areas are standby mapping areas.
The second instruction sets stored in the main mapping area and the standby mapping area are respectively from the mass storage device group, and the second instruction sets stored in the main mapping area and the standby mapping area respectively correspond to a certain section of second instruction set in the mass storage device group.
Step S54; when a second instruction set which is waited to be read by a second central processing unit in the DRAM chipset meets a second preset condition, a second subsequent instruction set of the second instruction set in the DRAM chipset is obtained from a mass storage device group through the storage interface group, and the second subsequent instruction set is stored in the DRAM chipset.
The second preset condition may be: the number of the second instruction sets to be read in the second logical storage area as the main mapping area is smaller than a preset value, or the time for the second instruction sets to be read in the second logical storage area as the main mapping area to be executed in the second central processing unit is smaller than a preset time. In this step, before the second subsequent instruction set is stored in the second logical storage area as the spare mapping area, if the original content of the second logical storage area as the spare mapping area is updated (by the second cpu), the content in the second logical storage unit as the spare mapping area needs to be written back to the original address of the mass storage device group.
The steps S51 and S52 may be performed by a first memory controller, and the steps S53 and S54 may be performed by a second memory controller. And the above steps S51-S54 are independent of each other and need not be performed according to the sequence of fig. 5.
In another embodiment of the above memory management method, the DRAM chipset may further include a common storage area. Correspondingly, the memory management method may further include: reading the shared data from the common storage area according to the shared data read-write request of the first central processing unit, and writing the shared data generated by the first central processing unit when executing the first instruction set into the common storage area; reading the shared data from the common storage area according to the shared data read-write request of the second central processing unit, and writing the shared data generated by the second central processing unit when executing the second instruction set into the common storage area.
The memory management method in this embodiment is the same as the dram in the embodiment corresponding to fig. 1 to 4, and the specific implementation process is described in detail in the embodiment corresponding to the dram, and the technical features in the embodiment of the dram are applicable in this embodiment of the method, which is not described herein again.
The present invention also provides a computer system, including a central processing unit and a dynamic random access memory, wherein the dynamic random access memory includes a circuit substrate, and a DRAM chipset integrated on the circuit substrate, a first memory controller, a second memory controller, a first interface for connecting the first central processing unit, a second interface for connecting the second central processing unit, and a storage interface group interface for connecting a mass storage device group, the dynamic random access memory further includes a storage unit and a computer program stored in the storage unit and operable on the first memory controller and the second memory controller, and the first memory controller and the second memory controller implement the steps of the memory management method when executing the computer program.
The computer system in this embodiment and the dynamic random access memory in the embodiment corresponding to fig. 1 to 4 belong to the same concept, and specific implementation processes thereof are detailed in the corresponding dynamic random access memory embodiments, and technical features in the method embodiments are correspondingly applicable in the apparatus embodiments, and are not described herein again.
Embodiments of the present invention further provide a computer-readable storage medium (for example, located in a dynamic random access memory), where the storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the memory management method are implemented. The computer-readable storage medium in this embodiment and the dynamic random access memory in the embodiment corresponding to fig. 1 to 4 belong to the same concept, and specific implementation processes thereof are detailed in the corresponding method embodiments, and technical features in the method embodiments are correspondingly applicable in this device embodiment, which is not described herein again.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
It is obvious to those skilled in the art that, for convenience and simplicity of description, the foregoing functional units and modules are merely illustrated in terms of division, and in practical applications, the foregoing functions may be distributed as needed by different functional units and modules. Each functional unit and module in the embodiments may be integrated in one processor, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed dram, memory management method and computer system may be implemented in other ways. For example, the dynamic random access memory embodiments described above are merely illustrative.
In addition, functional units in the embodiments of the present application may be integrated into one processor, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow in the method of the embodiments described above can be realized by a computer program, which can be stored in a computer-readable storage medium and can realize the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any physical or interface switching device, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signal, telecommunication signal, software distribution medium, etc., capable of carrying said computer program code. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media which may not include electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A dynamic random access memory is characterized by comprising a circuit substrate, a DRAM chip set, a first memory controller, a second memory controller, a first interface, a second interface and a storage interface set, wherein the DRAM chip set, the first memory controller, the second memory controller, the first interface and the second interface are integrated on the circuit substrate;
the first memory controller is respectively connected with the DRAM chip set and the first interface, responds to a read-write request of a first central processing unit connected to the first interface, acquires a first instruction set from the DRAM chip set, is connected to the first central processing unit through first interface data, and writes execution result data of the first central processing unit into the DRAM chip set; the first memory controller is also connected with the storage interface group, and when the first instruction set read by the first central processing unit in the DRAM chipset meets a first preset condition, the first memory controller acquires a first subsequent instruction set of the first instruction set in the DRAM chipset from a mass storage device group through the storage interface group and stores the first subsequent instruction set to the DRAM chipset;
the second memory controller is respectively connected with the DRAM chip set and the second interface, responds to a read-write request of a second central processing unit connected to the second interface, acquires a second instruction set from the DRAM chip set, is connected to the second central processing unit through second interface data and writes execution result data of the second central processing unit into the DRAM chip set; the second memory controller is further connected with the storage interface group, and when the second instruction set which is read by the second central processing unit in the DRAM chipset is waited to meet a second preset condition, the second memory controller acquires a second subsequent instruction set of the second instruction set in the DRAM chipset from a mass storage device group through the storage interface group and stores the second subsequent instruction set in the DRAM chipset.
2. The dynamic random access memory of claim 1, wherein the DRAM chipset comprises a first private storage area and a second private storage area;
the first private storage area comprises at least two first logic storage areas which are a main mapping area and a standby mapping area, the first logic storage area where a first instruction set currently read by the first central processing unit is located is the main mapping area, and the other first logic storage areas are the standby mapping areas; the first preset condition is as follows: the number of the first instruction sets to be read in the first logic storage area serving as the main mapping area is smaller than a preset value, or the time for the first instruction sets to be read in the first logic storage area serving as the main mapping area to be executed in the first central processing unit is smaller than a preset time;
the second private storage area comprises at least two second logic storage areas which are a main mapping area and a standby mapping area, the second logic storage area where the second instruction set currently read by the second central processing unit is located is the main mapping area, and the other second logic storage areas are the standby mapping areas; the second preset condition is as follows: the number of the second instruction sets to be read in the second logic storage area as the main mapping area is smaller than a preset value, or the time for the second instruction sets to be read in the second logic storage area as the main mapping area to be executed in the second central processing unit is smaller than a preset time.
3. The dynamic random access memory of claim 2, wherein the set of mass storage devices includes a first mass storage device and a second mass storage device; the storage interface group comprises a first storage interface used for connecting a first mass storage and a second storage interface used for connecting a second mass storage, and instruction sets stored in the first mass storage and the second mass storage are mutually independent; the DRAM chipset comprises a common storage area;
the first memory controller reads shared data from the public storage area according to the shared data read-write request of the first central processing unit, and writes the shared data generated by the first central processing unit when executing a first instruction set into the public storage area;
and the second memory controller reads the shared data from the public storage area according to the shared data read-write request of the second central processing unit and writes the shared data generated by the second central processing unit when executing the second instruction set into the public storage area.
4. The dram of claim 2, wherein said set of mass storage devices includes a third mass storage device, and said set of storage interfaces includes a third storage interface for coupling to said third mass storage device; the first memory controller and the second memory controller are respectively connected with the third mass storage through the third storage interface;
said first central processing unit executing a first instruction set acquired from a first logical memory area as a main map area on the material input through an input terminal of said first central processing unit and updating said first logical memory area according to the execution result or outputting the execution result through an output terminal of said first central processing unit;
said second central processing unit executing a second instruction set from said second logical memory area in response to the data input from the input terminal of said second central processing unit and updating said second logical memory area in accordance with the execution result, or outputting the execution result through the output terminal of said second central processing unit.
5. The dynamic random access memory according to claim 3, wherein the sizes of the at least two first logical storage areas are equal, and the size of the first logical storage area is equal to the size of the subsequent instruction set fetched by the first memory controller; the sizes of the at least two second logic storage areas are equal, and the sizes of the subsequent instruction sets acquired by the second memory controller and the second logic storage areas are equal;
before storing a first subsequent instruction set of a first instruction set in a first logic storage area as a main mapping area into a standby mapping area of a first private storage area, if original contents of the standby mapping area of the first private storage area are updated, the first memory controller writes contents in the standby mapping area of the first private storage area back to an original address of the mass storage device;
before storing a second subsequent instruction set of a second instruction set in a second logic storage area as a main mapping area into a standby mapping area of a second private storage area, if the original content of the standby mapping area of the second private storage area is updated, the second memory controller writes the content in the standby mapping area of the second private storage area back to the original address of the mass storage device.
6. The dynamic random access memory of claim 1, wherein the first interface and the second interface are both DRAM interfaces;
the storage interface group comprises at least one PCIE interface, and the mass storage device group is connected to the storage interface group through a PCIE bus; or, the mass storage device group is composed of a mass flash memory chip group integrated to the circuit substrate, and the mass flash memory chip group is connected to the first memory controller and the second memory controller through the storage interface group.
7. A memory management method, said memory comprising a DRAM chipset, and said memory being connected to a first central processing unit via a first interface, to a second central processing unit via a second interface, and to a mass storage device via a storage interface set, said method comprising:
responding to a read-write request of a first central processing unit connected to the first interface, acquiring a first instruction set from the DRAM chipset, connecting the first instruction set to the first central processing unit through first interface data, and writing execution result data of the first central processing unit into the DRAM chipset;
when a first instruction set read by a first central processing unit in the DRAM chipset meets a first preset condition, acquiring a first subsequent instruction set of the first instruction set in the DRAM chipset from a mass storage device group through the storage interface group, and storing the first subsequent instruction set to the DRAM chipset;
responding to a read-write request of a second central processing unit connected to the second interface, acquiring a second instruction set from the DRAM chipset, connecting the second instruction set to the second central processing unit through second interface data, and writing execution result data of the second central processing unit into the DRAM chipset;
when a second instruction set which is waited to be read by a second central processing unit in the DRAM chipset meets a second preset condition, a second subsequent instruction set of the second instruction set in the DRAM chipset is obtained from a mass storage device group through the storage interface group, and the second subsequent instruction set is stored in the DRAM chipset.
8. The memory management method according to claim 7, wherein the DRAM chipset comprises a first private storage area and a second private storage area, the DRAM chipset comprises a public storage area;
the first private storage area comprises at least two first logic storage areas which are a main mapping area and a standby mapping area, the first logic storage area where a first instruction set currently read by the first central processing unit is located is the main mapping area, and the other first logic storage areas are the standby mapping areas; the first preset condition is as follows: the number of the first instruction sets to be read in the first logic storage area serving as the main mapping area is smaller than a preset value, or the time for the first instruction sets to be read in the first logic storage area serving as the main mapping area to be executed in the first central processing unit is smaller than a preset time;
the second private storage area comprises at least two second logic storage areas which are a main mapping area and a standby mapping area, the second logic storage area where the second instruction set currently read by the second central processing unit is located is the main mapping area, and the other second logic storage areas are the standby mapping areas; the second preset condition is as follows: the number of the second instruction sets to be read in the second logic storage area serving as the main mapping area is smaller than a preset value, or the time for the second instruction sets to be read in the second logic storage area serving as the main mapping area to be executed in the second central processing unit is smaller than preset time;
the method further comprises the following steps:
reading shared data from the public storage area according to a shared data read-write request of the first central processing unit, and writing the shared data generated by the first central processing unit when executing a first instruction set into the public storage area;
reading shared data from the public storage area according to the shared data read-write request of the second central processing unit, and writing the shared data generated by the second central processing unit when executing a second instruction set into the public storage area;
before storing a first subsequent instruction set of a first instruction set in a first logic storage area as a main mapping area into a standby mapping area of a first private storage area, if original contents of the standby mapping area of the first private storage area are updated, the first memory controller writes contents in the standby mapping area of the first private storage area back to an original address of the mass storage device;
before storing a second subsequent instruction set of a second instruction set in a second logic storage area as a main mapping area into a standby mapping area of a second private storage area, if the original content of the standby mapping area of the second private storage area is updated, the second memory controller writes the content in the standby mapping area of the second private storage area back to the original address of the mass storage device.
9. A computer system comprises a central processing unit and a dynamic random access memory, the dynamic random access memory comprises a circuit substrate, a DRAM chip set integrated on the circuit substrate, a first memory controller, a second memory controller, a first interface used for connecting a first central processing unit, a second interface used for connecting a second central processing unit and a storage interface group interface used for connecting a mass storage device group, the dynamic random access memory further comprises a storage unit and a computer program stored in the storage unit and operable on the first memory controller and the second memory controller, the steps of the memory management method according to any one of claims 7 to 8 are implemented when the first memory controller and the second memory controller execute the computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the memory management method according to one of claims 7 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911121076.9A CN111177027B (en) | 2019-11-15 | 2019-11-15 | Dynamic random access memory, memory management method, system and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911121076.9A CN111177027B (en) | 2019-11-15 | 2019-11-15 | Dynamic random access memory, memory management method, system and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111177027A true CN111177027A (en) | 2020-05-19 |
| CN111177027B CN111177027B (en) | 2023-07-18 |
Family
ID=70651907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911121076.9A Active CN111177027B (en) | 2019-11-15 | 2019-11-15 | Dynamic random access memory, memory management method, system and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111177027B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117130692A (en) * | 2023-10-23 | 2023-11-28 | 成都赛力斯科技有限公司 | Application management method, device, electronic equipment and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1716453A (en) * | 2004-01-30 | 2006-01-04 | 三星电子株式会社 | The multi-port memory device that between main frame and non-volatile memory device, cushions |
| CN106560893A (en) * | 2015-10-01 | 2017-04-12 | 株式会社东芝 | Storage Device And Method For Defect Scanning Of The Same |
| CN108664325A (en) * | 2017-03-30 | 2018-10-16 | 北京视联动力国际信息技术有限公司 | Handle the method and electronic equipment of data |
| CN109144419A (en) * | 2018-08-20 | 2019-01-04 | 浪潮电子信息产业股份有限公司 | A kind of solid state hard disk memory read-write method and system |
-
2019
- 2019-11-15 CN CN201911121076.9A patent/CN111177027B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1716453A (en) * | 2004-01-30 | 2006-01-04 | 三星电子株式会社 | The multi-port memory device that between main frame and non-volatile memory device, cushions |
| CN106560893A (en) * | 2015-10-01 | 2017-04-12 | 株式会社东芝 | Storage Device And Method For Defect Scanning Of The Same |
| CN108664325A (en) * | 2017-03-30 | 2018-10-16 | 北京视联动力国际信息技术有限公司 | Handle the method and electronic equipment of data |
| CN109144419A (en) * | 2018-08-20 | 2019-01-04 | 浪潮电子信息产业股份有限公司 | A kind of solid state hard disk memory read-write method and system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117130692A (en) * | 2023-10-23 | 2023-11-28 | 成都赛力斯科技有限公司 | Application management method, device, electronic equipment and storage medium |
| CN117130692B (en) * | 2023-10-23 | 2024-01-23 | 成都赛力斯科技有限公司 | Application management method, device, electronic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111177027B (en) | 2023-07-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11042297B2 (en) | Techniques to configure a solid state drive to operate in a storage mode or a memory mode | |
| CN110941395B (en) | Dynamic random access memory, memory management method, system and storage medium | |
| JP2004295885A (en) | Computer system permitting dynamic reallocation of main memory | |
| WO2020177577A1 (en) | Method and apparatus for controller to load multi-core firmware, and computer device | |
| RU2643499C2 (en) | Memory control | |
| CN105408875A (en) | Distributed procedure execution and file systems on a memory interface | |
| US20090049232A1 (en) | Execute-in-place implementation for a nand device | |
| US11055220B2 (en) | Hybrid memory systems with cache management | |
| US20190042415A1 (en) | Storage model for a computer system having persistent system memory | |
| US20210271599A1 (en) | Hybrid Memory Systems with Cache Management | |
| CN114647446A (en) | Storage-level storage device, computer module and server system | |
| US7689991B2 (en) | Bus management techniques | |
| US20190042443A1 (en) | Data acquisition with zero copy persistent buffering | |
| CN111177027A (en) | Dynamic random access memory, memory management method, system and storage medium | |
| JP2022050757A (en) | Memory system | |
| US8745363B2 (en) | Bootable volatile memory device, memory module and processing system comprising bootable volatile memory device, and method of booting processing system using bootable volatile memory device | |
| CN113220608B (en) | NVMe command processor and processing method thereof | |
| CN112486274B (en) | Computer expansion card and computer system | |
| CN109445686B (en) | Storage disk and data access method | |
| CN217588059U (en) | Processor system | |
| CN115176313A (en) | Memory startup and initialization system and method | |
| CN111949211B (en) | Storage device and storage control method | |
| CN115857805B (en) | Artificial intelligence computable storage system | |
| US20240119017A1 (en) | Bridge control chip and associated signal processing method | |
| JPH03656B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |