CN112398477A - Monoclinic ADC circuit structure with condition-dependent multi-sampling technology - Google Patents

Monoclinic ADC circuit structure with condition-dependent multi-sampling technology Download PDF

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CN112398477A
CN112398477A CN201910742636.6A CN201910742636A CN112398477A CN 112398477 A CN112398477 A CN 112398477A CN 201910742636 A CN201910742636 A CN 201910742636A CN 112398477 A CN112398477 A CN 112398477A
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comparator
input end
output
latch
tsw2
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CN112398477B (en
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徐江涛
史晓琳
聂凯明
高静
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Tianjin University Marine Technology Research Institute
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Tianjin University Marine Technology Research Institute
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0854—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of quantisation noise

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Abstract

A monoclinic ADC circuit structure with condition correlation multisampling technology is composed of a comparator, a counter, a latch and a CCMS control part; the right plate of the capacitor C2 is connected to the negative input end of the comparator; a ramp voltage Vramp1, Vramp2 are connected to the left plate of capacitor C1 via switches SW2 and SW2b, respectively; the right plate of the capacitor C1 is connected to the positive input end of the comparator; the common mode voltage Vcom is respectively connected to the positive input end and the negative input end of the comparator through two SW1 switches; the output CMP _ OUT of the comparator is connected to the input en of the counter; the output end of the counter is connected to the input end of the latch; the output CMP _ OUT of the comparator is also connected to the input of the CCMS control block; the structure effectively reduces random noise in the pixel; the resolution and the imaging quality of the image sensor are improved, and the application occasions of the image sensor are further expanded.

Description

Monoclinic ADC circuit structure with condition-dependent multi-sampling technology
Technical Field
The invention relates to the field of analog integrated circuits, in particular to a monoclinic ADC circuit structure with condition-dependent multi-sampling technology.
Background
Random Noise (RN) originates from pixel devices and analog readout circuits and is a key parameter affecting high quality CMOS Image Sensors (CIS). In recent years, as the demand of high-resolution CIS for mobile devices is increasing, the resolution of CIS is increasing and the chip area is also increasing. To alleviate this, a high-resolution CIS that reduces the pixel size has been developed to reduce the chip area and cost. Such small pixel size source followers cause worse flicker and Random Telegraph Signal (RTS) noise during analog readout. The random noise of the small pixel pitch CIS is around 1-2 e-root mean square.
The random noise introduced in the pixel imaging process can be effectively reduced by using a Correlated Multiple Sampling (CMS) technology in a column parallel Single-Slope ADC (SS ADC), and can be effectively reduced to 0.7 e-. The column parallel SS ADC has the advantages of simple circuit structure, low power consumption, good uniformity and the like, and is very suitable for using CMS technology. But since the conversion time is linear with the number of multisampling times, a long a/D conversion time is required for each pixel. The longer a/D conversion time slows down the frame rate of the sensor. As the frame rate decreases, low-frequency noise of pixel noise, i.e., 1/f noise of the pixel source follower, becomes a main noise contributor as the sampling time increases, thereby limiting the noise reduction effect of multiple sampling.
To solve the frame rate reduction problem due to Multiple Sampling, a Conditional Correlated Multiple Sampling (CCMS) technique is proposed to reduce random noise in pixels. The main idea of CCMS is to perform multiple quantization with the dark pixel output with small voltage range, small slope and small swing by determining the brightness of the pixel output voltage to reduce random noise and a/D conversion time of each pixel. Moreover, because the output of a bright pixel with a large swing is mainly photon shot noise and cannot be reduced by sampling for multiple times within a frame time, when the swing of the output voltage of the pixel exceeds a certain specific value, single quantization is performed by using a full voltage range slope.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a monoclinic ADC circuit structure with a condition-dependent multi-sampling technology, which can realize the multi-sampling of read signals under the condition of not reducing the frame frequency and effectively reduce the random noise in pixels; the resolution and the imaging quality of the image sensor are improved, and the application occasions of the image sensor are further expanded.
A single-slope ADC circuit structure with condition-dependent multi-sampling technology is shown in a dotted line box in figure 1 and comprises a comparator, a counter, a latch and a CCMS control part. The specific connection relationship is as follows: pixel via source follower MsfOutput voltage V ofsfThe left plate connected to capacitor C2; the right plate of the capacitor C2 is connected to the negative input end of the comparator; a ramp voltage Vramp1, Vramp2 are connected to the left plate of capacitor C1 via switches SW2 and SW2b, respectively; the right plate of the capacitor C1 is connected to the positive input end of the comparator; the common mode voltage Vcom is respectively connected to the positive input end and the negative input end of the comparator through two SW1 switches; the output CMP _ OUT of the comparator is connected to the input en of the counter; the output end of the counter is connected to the input end of the latch; the output CMP _ OUT of the comparator is also connected to the input of the CCMS control block; the S _ EN1, S _ EN2 and Index signals are input control signals of the CCMS control block; the State, Tsw2, Tsw2b signals are the output signals of the CCMS control block.
A monoclinic ADC circuit structure with a condition-dependent multi-sampling technology is disclosed, and the control sequence is shown in figure 3. VsfAnd CMP _ OUT are the pixel via the source follower output and the comparator output, respectively. To save time, the dark pixel detection operation is combined with pixel signal level a/D conversion. The CCMS control block controls the ramp type of the access comparator according to the different output states of the latch. The FD in the pixel is first reset. The pixel reset voltage is sampled and converted by the proposed SS ADC. Since the reset voltage is small, the output Tsw2 of the CCMS control block is "L", Tsw2b is "H", and the slope V isramp2Is connected to the positive input of the comparator and is sampled multiple times using a small voltage range ramp. The signal charge in the photodiode is then transferred to the FD and then detected by the dark pixel detection circuit in the dark pixel detection phase. The digital pulse (Index) controls the dark pixel detection area in the time domain. When CMP _ OUT toggles from "H" to "L", the latch is used to lock the value of Index. For dark pixels, logic "H" is latched by the latchOn the other hand, the latch output (State) becomes "H", the CCMS control block output Tsw2 is "L", Tsw2b is "H", and the ramp V is setramp2Is connected to the positive input of the comparator and is sampled multiple times using a small voltage range ramp. For bright pixels, logic "L" is latched by the latch, state remains "L", CCMS control block outputs Tsw2 is "H", Tsw2b is "L", ramp Vramp1Is connected to the positive input end of the comparator and adopts a full voltage range slope to carry out single quantization. Schematic diagram of the CCMS control block as shown in fig. 2, a digital control (Index) and digital latch are used to detect dark pixels. The output of the latch is fed back to its input through an or gate to lock the detection result and avoid overwriting during the pixel signal multi-sampling operation. Tsw2 and Tsw2b are control signals that control the comparator input ramp switches. State, S _ EN1, and S _ EN2 are used to generate Tsw2 and Tsw2 b. Since the module only comprises simple logic gates, the module can be easily integrated into a column parallel SS ADC with a small layout area.
A monoclinic ADC circuit structure with condition-dependent multi-sampling technology can be effectively applied to SS ADCs, so that the random noise in small-size pixels is effectively reduced, the resolution and the imaging quality of an image sensor are improved, the frame frequency under the condition of correlated multi-sampling is effectively ensured, and the application occasion of the image sensor is further enlarged.
Drawings
FIG. 1 is a SS ADC architecture with CCMS technology;
FIG. 2 is a schematic diagram of a CCMS control block;
fig. 3 is a SS ADC control timing with CCMS technology.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, a detailed description of the embodiments of the present invention will be given below with reference to examples.
A single-slope ADC circuit structure with condition-dependent multi-sampling technology is shown in a dotted line box in figure 1 and comprises a comparator, a counter, a latch and a CCMS control part. The specific connection relationship is as follows: pixel via source follower MsfOutput voltage V ofsfIs connected to electricityThe left plate of container C2; the right plate of the capacitor C2 is connected to the negative input end of the comparator; a ramp voltage Vramp1, Vramp2 are connected to the left plate of capacitor C1 via switches SW2 and SW2b, respectively; the right plate of the capacitor C1 is connected to the positive input end of the comparator; the common mode voltage Vcom is respectively connected to the positive input end and the negative input end of the comparator through two SW1 switches; the output CMP _ OUT of the comparator is connected to the input en of the counter; the output end of the counter is connected to the input end of the latch; the output CMP _ OUT of the comparator is also connected to the input of the CCMS control block; the S _ EN1, S _ EN2 and Index signals are input control signals of the CCMS control block; the State, Tsw2, Tsw2b signals are the output signals of the CCMS control block.
A monoclinic ADC circuit structure with a condition-dependent multi-sampling technology is disclosed, and the control sequence is shown in figure 3. VsfAnd CMP _ OUT are the pixel via the source follower output and the comparator output, respectively. To save time, the dark pixel detection operation is combined with pixel signal level a/D conversion. The CCMS control block controls the ramp type of the access comparator according to the different output states of the latch. The FD in the pixel is first reset. The pixel reset voltage is sampled and converted by the proposed SS ADC. Since the reset voltage is small, the output Tsw2 of the CCMS control block is "L", Tsw2b is "H", and the slope V isramp2Is connected to the positive input of the comparator and is sampled multiple times using a small voltage range ramp. The signal charge in the photodiode is then transferred to the FD and then detected by the dark pixel detection circuit in the dark pixel detection phase. The digital pulse (Index) controls the dark pixel detection area in the time domain. When CMP _ OUT toggles from "H" to "L", the latch is used to lock the value of Index. For dark pixels, logic "H" is latched by the latch, the latch output (State) becomes "H", the CCMS control block output Tsw2 is "L", Tsw2b is "H", and ramp Vramp2Is connected to the positive input of the comparator and is sampled multiple times using a small voltage range ramp. For bright pixels, logic "L" is latched by the latch, state remains "L", CCMS control block outputs Tsw2 is "H", Tsw2b is "L", ramp Vramp1Is connected to the positive input end of the comparator and is performed by adopting a full-voltage range slopeA single quantization. Schematic diagram of the CCMS control block as shown in fig. 2, a digital control (Index) and digital latch are used to detect dark pixels. The output of the latch is fed back to its input through an or gate to lock the detection result and avoid overwriting during the pixel signal multi-sampling operation. Tsw2 and Tsw2b are control signals that control the comparator input ramp switches. State, S _ EN1, and S _ EN2 are used to generate Tsw2 and Tsw2 b. Since the module only comprises simple logic gates, the module can be easily integrated into a column parallel SS ADC with a small layout area.
The invention adopts 110nm technology for simulation, wherein the resolution of a pixel array is 3296H multiplied by 2512V, the sampling frequency of an SS ADC is 75.36kHz, and the single sampling frame frequency is 15 frames/s. When 4 samples are taken using conventional CMS techniques, the frame rate drops to around 3.75 frames/s and 0.7 e-for random noise. In contrast, when the SS ADC using the CCMS technique performs 5 samples, the frame rate is 7.2 frames/s, and the random noise is reduced to 0.66 e-. The technology provided by the invention can reduce the frame frequency loss on the premise of effectively reducing random noise by sampling for many times.

Claims (2)

1. A monoclinic ADC circuit structure with condition-dependent multisampling technology is characterized in that: the device consists of a comparator, a counter, a latch and a CCMS control part; pixel via source follower MsfOutput voltage V ofsfThe left plate connected to capacitor C2; the right plate of the capacitor C2 is connected to the negative input end of the comparator; a ramp voltage Vramp1, Vramp2 are connected to the left plate of capacitor C1 via switches SW2 and SW2b, respectively; the right plate of the capacitor C1 is connected to the positive input end of the comparator; the common mode voltage Vcom is respectively connected to the positive input end and the negative input end of the comparator through two SW1 switches; the output CMP _ OUT of the comparator is connected to the input en of the counter; the output end of the counter is connected to the input end of the latch; the output CMP _ OUT of the comparator is also connected to the input of the CCMS control block; the S _ EN1, S _ EN2 and Index signals are input control signals of the CCMS control block; the State, Tsw2, Tsw2b signals are the output signals of the CCMS control block.
2. The method of claim 1A monoclinic ADC circuit structure with condition-dependent multisampling technology is characterized in that: the FD in the pixel is first reset and the pixel reset voltage is sampled and converted by the proposed SS ADC, the CCMS control block outputs Tsw2 as "L", Tsw2b as "H", ramp V, since the reset voltage is smallramp2The sampling circuit is connected to the positive input end of the comparator, and multiple times of sampling are carried out by applying a small voltage range slope; transferring the signal charge in the photodiode to the FD, and detecting by a dark pixel detection circuit in a dark pixel detection stage; the digital pulse Index controls the dark pixel detection area in the time domain; when CMP _ OUT is flipped from "H" to "L", the latch is used to lock the value of Index; for dark pixels, logic "H" is latched by the latch, latch output State changes to "H", CCMS control block output Tsw2 is "L", Tsw2b is "H", ramp Vramp2The sampling circuit is connected to the positive input end of the comparator, and multiple times of sampling are carried out by applying a small voltage range slope; for bright pixels, logic "L" is latched by the latch, state remains "L", CCMS control block outputs Tsw2 is "H", Tsw2b is "L", ramp Vramp1The single-time quantization is carried out by adopting a full-voltage range slope after being accessed to the positive input end of the comparator; tsw2 and Tsw2b are control signals that control the comparator input ramp switches; state, S _ EN1, and S _ EN2 are used to generate Tsw2 and Tsw2 b.
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