CN113960356B - Current comparison circuit, device and method for detecting image solar black element effect - Google Patents

Current comparison circuit, device and method for detecting image solar black element effect Download PDF

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Publication number
CN113960356B
CN113960356B CN202111313697.4A CN202111313697A CN113960356B CN 113960356 B CN113960356 B CN 113960356B CN 202111313697 A CN202111313697 A CN 202111313697A CN 113960356 B CN113960356 B CN 113960356B
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nmos tube
tube
signal
inverter
drain electrode
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CN113960356A (en
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芮松鹏
蔡化
陈飞
陈正
夏天
王勇
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Chengdu Image Design Technology Co Ltd
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Chengdu Image Design Technology Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2218/00—Aspects of pattern recognition specially adapted for signal processing

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  • General Physics & Mathematics (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

The invention provides a current comparison circuit, a device and a method for detecting the image solar black sub-effect, wherein the device for detecting the image solar black sub-effect comprises a current comparison circuit, a photosensitive module, a signal control module and a judging module, wherein the photosensitive module is used for outputting a pixel voltage signal according to an image signal, and the current comparison circuit is connected with the photosensitive module and is used for detecting and comparing the current at the output end of the photosensitive module; the signal control module is connected with the current comparison circuit and is used for providing a control signal for the current comparison circuit; the judging module is connected with the photosensitive module and the output end of the current comparison circuit and is used for judging the sun black of the image according to the comparison signal of the current comparison circuit.

Description

Current comparison circuit, device and method for detecting image solar black element effect
Technical Field
The invention relates to the technical field of image sensors, in particular to a current comparison circuit, a device and a method for detecting the sun black effect of an image.
Background
Complementary Metal Oxide Semiconductor (CMOS) refers to a technology for manufacturing a large-scale integrated circuit chip or a chip manufactured by the technology, and a CMOS image sensor (CMOS Image Sensor, CIS) based on the technology of the chip is used as an image sensing device, and has irreplaceability in the image field, and as the application range of the CMOS image sensor chip is wider, in order to display stable and reliable output images in various scenes, the performance requirements of corresponding products are higher and higher.
In various indexes of the CIS chip, the stability of an output image under a strong light source is a basic requirement of various CIS products, and particularly the CIS for vehicle-mounted application can often meet the direct irradiation scene of a solar light source. Under the CIS control time sequence based on the current Pixel (Pixel) process and the SS-ADC architecture with the greatest application, the sun black effect can appear on the strong light source, so that the Pixel is leaked after reset to reduce the reset voltage, and the collected photoelectric signal is smaller and even zero as a whole. In this way, the output is also zero signal after ADC conversion, and the corresponding pixel appears black or dark in the image.
Therefore, it is necessary to provide a novel current comparison circuit, an apparatus and a method for detecting the sun black effect of an image, so as to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a current comparison circuit, a device and a method for detecting the sun black effect of an image, which can rapidly detect whether the sun black phenomenon exists in the image through simple logic control so as to facilitate timely adjustment of the image.
In order to achieve the above object, the current comparing circuit of the present invention includes a first capacitor unit, a second capacitor unit, a first inverter unit, a second inverter unit, a first bias analog input unit, a second bias analog input unit, a first switch unit, a second switch unit, and a current sampling unit;
the first switch unit is connected with the first capacitor unit, the second switch unit is connected with the second capacitor unit, the first switch unit and the second switch unit are connected with sampling output ends, the first capacitor unit and the current sampling unit are connected with the first bias analog input unit, the second capacitor unit and the current sampling unit are connected with the second bias analog input unit, the current sampling unit, the first switch unit and the second switch unit are connected with the first inverter unit, and the current sampling unit is also connected with the input ends of the second inverter unit.
The current comparison circuit has the beneficial effects that: the current comparison circuit is used for detecting pixel voltage signals in the image, the pixel voltage signals of the image are detected through the currents of the first capacitor unit and the second capacitor unit respectively through the front detection and the rear detection, whether the image is subjected to the sun black phenomenon or not is determined through the magnitude of the current change between the first capacitor unit and the second capacitor unit, and therefore the quick detection of the sun black of the image is achieved, and the image can be quickly adjusted.
Optionally, the first capacitance unit includes a first NMOS tube and a first capacitance, where a source electrode of the first NMOS tube and one end of the first capacitance are grounded, a gate electrode of the first NMOS tube is connected with the other end of the first capacitance, and a drain electrode of the first NMOS tube is connected with the first bias analog input unit;
the second capacitance unit comprises a fourth NMOS tube and a second capacitance, wherein the source electrode of the fourth NMOS tube and one end of the second capacitance are grounded, the grid electrode of the fourth NMOS tube is connected with the other end of the second capacitance, and the drain electrode of the fourth NMOS tube is connected with the second bias analog input unit;
The first inverter unit comprises a first inverter and a second inverter, the input end of the first inverter is input with an enabling signal, the output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter is connected with the current sampling unit;
the second inverter unit comprises a third inverter and a fourth inverter, the input end of the third inverter is connected with the current sampling unit, the output end of the third inverter is connected with the input end of the fourth inverter, and the output end of the fourth inverter outputs a detection result;
the first switch unit comprises a first switch and a fifth NMOS tube, one end of the first switch is connected with the sampling output end, the other end of the first switch is connected with the grid electrode of the first NMOS tube, the grid electrode of the fifth NMOS tube is connected with the output end of the first inverter, the drain electrode of the fifth NMOS tube is connected with the other end of the first switch, and the source electrode of the fifth NMOS tube is grounded;
the second switch unit comprises a second switch and a sixth NMOS tube, one end of the second switch is connected with the sampling output end, the other end of the second switch is connected with the grid electrode of the fourth NMOS tube, the drain electrode of the sixth NMOS tube is connected with the other end of the second switch, the grid electrode of the sixth NMOS tube is connected with the output end of the first inverter, and the source electrode of the sixth NMOS tube is grounded;
The current sampling unit comprises a first PMOS tube, a second PMOS tube and a third PMOS tube, wherein the source electrode of the first PMOS tube, the source electrode of the second PMOS tube and the source electrode of the third PMOS tube are all connected with working voltages, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected with the input end of the third inverter, the drain electrode of the first PMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the first NMOS tube are all connected with the first bias analog input unit, the gate electrode of the third PMOS tube is connected with the output end of the second inverter, and the drain electrode of the second PMOS tube and the drain electrode of the fourth NMOS tube are all connected with the second bias analog input unit.
Optionally, the first bias analog input unit includes a second NMOS transistor, a gate of the second NMOS transistor is connected to a first bias voltage, a source of the second NMOS transistor is grounded, and a drain of the second NMOS transistor is connected to a drain of the first NMOS transistor and a drain of the first PMOS transistor;
the second bias analog input unit comprises a third NMOS tube, the grid electrode of the third NMOS tube is connected with a second bias voltage, the source electrode of the third NMOS tube is grounded, and the drain electrode of the third NMOS tube is connected with the drain electrode of the second PMOS tube and the drain electrode of the fourth NMOS tube. The beneficial effects are that: the current comparison circuit with the structure can realize the detection of the solar black effect of the image through logic control without additionally designing a special circuit to provide bias voltage or reference voltage.
Optionally, the current comparison circuit further includes a first input unit and a second input unit;
the first bias analog input unit comprises a seventh NMOS tube, an eighth NMOS tube and a ninth NMOS tube, wherein the drain electrode of the ninth NMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the ninth NMOS tube is connected with the drain electrode of the eighth NMOS tube and the grid electrode of the seventh NMOS tube, the grid electrode of the eighth NMOS tube is connected with the output end of the first inverter, the source electrode of the seventh NMOS tube, the source electrode of the eighth NMOS tube and the source electrode of the ninth NMOS tube are grounded, the grid electrode of the seventh NMOS tube is connected with the drain electrode of the seventh NMOS tube, and the drain electrode of the seventh NMOS tube is connected with the drain electrode of the first NMOS tube and the first input unit;
the second bias analog input unit comprises a tenth NMOS tube, an eleventh NMOS tube and a twelfth NMOS tube, wherein the drain electrode of the twelfth NMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the twelfth NMOS tube is connected with the drain electrode of the eleventh NMOS tube and the grid electrode of the tenth NMOS tube, the grid electrode of the eleventh NMOS tube is connected with the output end of the first inverter, the drain electrode of the tenth NMOS tube is respectively connected with the grid electrode of the tenth NMOS tube, the drain electrode of the fourth NMOS tube and the second input unit, and the source electrode of the tenth NMOS tube, the source electrode of the eleventh NMOS tube and the source electrode of the twelfth NMOS tube are all grounded;
The first input unit comprises a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube, wherein the source electrode of the fourth PMOS tube is connected with a first bias voltage, the grid electrode of the fourth PMOS tube is connected with the output end of the first inverter, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube, the grid electrode of the fifth PMOS tube is connected with the output end of the second inverter, the source electrodes of the fifth PMOS tube and the sixth PMOS tube are both connected with working voltages, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the seventh NMOS tube and the drain electrode of the first NMOS tube;
the second input unit comprises a seventh PMOS tube, an eighth PMOS tube and a ninth PMOS tube, wherein the source electrode of the seventh PMOS tube is connected with a second bias voltage, the grid electrode of the seventh PMOS tube is connected with the output end of the first inverter, the drain electrode of the seventh PMOS tube is connected with the grid electrode of the eighth PMOS tube and the drain electrode of the ninth PMOS tube, the grid electrode of the ninth PMOS tube is connected with the output end of the second inverter, the source electrodes of the eighth PMOS tube and the ninth PMOS tube are both connected with working voltages, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the tenth NMOS tube and the drain electrode of the fourth NMOS tube. The beneficial effects are that: through the current comparison circuit, the solar black sub effect is detected on the image, and meanwhile, the power consumption of the whole circuit is reduced and controllable.
The invention discloses a device for detecting the image sun black effect, which is characterized by comprising the current comparison circuit, wherein the device for detecting the image sun black effect further comprises:
the photosensitive module is used for outputting a pixel voltage signal according to the image signal;
the signal control module is connected with the current comparison circuit and is used for providing a control signal for the current comparison circuit;
and the judging module is connected with the photosensitive module and the output end of the current comparison circuit and is used for judging the sun black of the image according to the comparison signal of the current comparison circuit.
The invention relates to a device for detecting the sun black effect of an image, which comprises: the current comparison circuit is connected with the photosensitive module, the signal control module provides a control signal for the current comparison circuit so as to control the current comparison circuit to detect pixel voltage signals output by the photosensitive module twice at two sampling moments, and output detection signals according to the twice detection, so that the judgment module can judge whether the image in the photosensitive module has the solar black effect or not, and the detection of the solar black effect of the image can be realized in a logic control mode so as to facilitate the subsequent elimination of the solar black effect of the image.
Optionally, the signal control module controls the current comparison circuit to sample the photosensitive module twice successively by outputting a control signal and obtain a first sampling voltage and a second sampling voltage, the current comparison circuit outputs a comparison signal according to the difference value of the first sampling voltage and the second sampling voltage and the magnitude of a preset comparison threshold, and the judgment module receives the comparison signal to output a judgment result of the image solar black. The beneficial effects are that: the signal control module outputs a control signal to enable the current comparison circuit to sequentially sample to obtain a first sampling voltage and a second sampling voltage, whether the image has the solar black sub-effect or not is determined by judging the difference value of the first sampling voltage and the second sampling voltage and the preset comparison threshold value, whether the solar black sub-effect exists in the image or not can be rapidly detected in a mode of detecting the voltage difference without independently setting a reference voltage, a special circuit is not required to be independently added to provide the reference voltage, and the complexity of the circuit is reduced.
Optionally, the signal control module is further configured to generate an enable signal, when the enable signal is at a high level, the current comparison circuit is in a working state, and when the enable signal is at a low level, the current comparison circuit is in an off state. The beneficial effects are that: when the current comparison circuit is not needed to be used, the whole power consumption is reduced by generating a low-level enabling signal so that the current comparison circuit stops working.
Optionally, the device for detecting the sun black effect of the image further comprises an output module connected with the judging module, and the output module converts a black signal area in the image signal into a maximum signal bright point to output after determining that the sun black effect of the detected image of the image signal in the photosensitive module is effective according to the judging result output by the judging module. The beneficial effects are that: after the sun black effect in the image is detected, the black area in the image is converted into the maximum signal bright point to be output, so that the adjustment of the sun black of the image is finished, and the image can be ensured to be output normally.
The invention also provides a method for detecting the sun black sub effect of the image, which comprises the following steps:
sending a first sampling pulse signal and a second sampling pulse signal to the current comparison circuit through a signal control module;
the current comparison circuit samples the photosensitive module according to the first sampling pulse signal to obtain a first sampling voltage, and samples the photosensitive module according to the second sampling pulse signal to obtain a second sampling voltage;
the current comparison circuit is used for obtaining a voltage difference value between the first sampling voltage and the second sampling voltage, and outputting a comparison signal according to the voltage difference value and a preset comparison threshold value;
And the judging module receives the comparison signal and outputs a judging result of the image sun black according to the comparison signal.
The method for detecting the sun black effect of the image has the beneficial effects that: the current comparison circuit is used for sampling the output end of the photosensitive module according to the received pulse signals to obtain a first sampling voltage and a second sampling voltage, and outputting a comparison signal according to the voltage difference between the first sampling voltage and the second sampling voltage and the magnitude of a preset comparison threshold value, and then the judging module is used for outputting a judging result of an image solar black sub-effect in the photosensitive module according to the received comparison signal, so that the rapid detection of the image solar black sub-effect in the photosensitive module is completed.
Optionally, the determining module receives the comparison signal, and outputs a result of determining the image sun black according to the comparison signal, including:
and the judging module correspondingly outputs a detection result of the solar black sub effect of the image according to the level of the received comparison signal.
Optionally, after the judging module outputs the effect of detecting the sun black sub effect of the image, the black signal area in the image signal is converted into the maximum signal bright point through the output module to be output. The beneficial effects are that: and the black signal area of the solar black sub effect is converted into the maximum signal bright point through the output module to be output, so that the finally output image is ensured to be normal, and the image abnormality caused by the solar black sub effect is reduced.
Drawings
FIG. 1 is a block diagram of an apparatus for detecting the sun black effect of an image according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a first circuit configuration of a current comparison circuit according to an embodiment of the invention;
FIG. 3 is a timing diagram of various control signals in an embodiment of the present invention;
FIG. 4 is a schematic diagram of related timing and signals of a CIS image system under normal operation according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of the timing and signals associated with normal operation of a CIS image system in an embodiment of the invention;
FIG. 6 is a schematic diagram of related timing and signals when the CIS image system is operating normally under super-strong light and the sun black effect occurs in the embodiment of the invention;
FIG. 7 is a schematic diagram of a logic signal processing circuit for the switch control signals S1 and S2 according to an embodiment of the invention;
FIG. 8 is a schematic diagram of the input/output logic of the current comparator circuit in the first case of the embodiment of the invention;
FIG. 9 is a schematic diagram of the input/output logic of the current comparison circuit in the second case of the embodiment of the invention;
FIG. 10 is a schematic diagram of a second circuit configuration of the current comparing circuit according to the embodiment of the invention;
FIG. 11 is a flowchart of a method for detecting the sun black effect of an image according to an embodiment of the present invention;
fig. 12 is a block diagram of an apparatus for detecting the sun black effect of an image when the photosensitive module of the embodiment of the invention adopts a 4T pixel structure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items.
In order to solve the problems in the prior art, the present invention provides a device for detecting the sun black effect of an image, as shown in fig. 1, including:
a photosensitive module 31 for outputting a pixel voltage signal according to the image signal;
the current comparison circuit 30 is connected with the photosensitive module 31 and is used for detecting a voltage signal in the photosensitive module 31 and outputting a comparison signal;
a signal control module 32, connected to the current comparison circuit 30, for providing a control signal to the current comparison circuit 30;
and the judging module 33 is connected with the photosensitive module 31 and the output end of the current comparing circuit 30 and is used for judging the sun black of the image according to the comparison signal of the current comparing circuit 30.
Referring to fig. 1, in the present embodiment, the signal control module 32 is a bias and digital control (Bias Digital Control, BDC) circuit, and the signal control module 32 is mainly configured to provide a control signal to control the current comparison circuit 30.
Fig. 12 is a block diagram of a device for detecting the sun black effect of an image when the photosensitive module of the embodiment of the invention adopts a 4T pixel structure, referring to fig. 12, in this embodiment, the photosensitive module 31 adopts a 4T pixel structure, the determining module 33 adopts a column-level analog-to-digital conversion ADC, and the pixel output voltage vpix_out of the photosensitive module 31 is connected to the input ends of the current comparing circuit 30 and the determining module 33, wherein, since the photosensitive module 31 adopts a 4T pixel structure in the prior art, the pixel voltage signal is mainly output according to the image, the scheme does not involve improvement of the photosensitive module 31, and the specific structure thereof will not be repeated herein.
In some embodiments, the signal control module 32 outputs a control signal to control the current comparison circuit 31 to sample the photosensitive module 30 twice and obtain a first sampling voltage and a second sampling voltage, the current comparison circuit outputs a comparison signal according to the difference value of the first sampling voltage and the second sampling voltage and the magnitude of a preset comparison threshold, and the judging module 33 receives the comparison signal to output a judging result of the image sun black.
Specifically, when the sun black sub-effect is detected on the image output by the photosensitive module 31, two groups of control signals are output by the control signal control module 32 in cooperation with the system time sequence, so that the current comparison circuit 31 samples the output end vpix_out of the photosensitive module 31 twice successively to obtain a first sampling voltage and a second sampling voltage respectively, then the current comparison circuit 31 compares the voltage values of the two samples, if the voltage value of the second sampling voltage of the last sample, which is lower than the voltage value of the first sampling voltage of the previous sample, exceeds a preset comparison threshold value, it is indicated that the reduction of the second sampling voltage, which is higher than the first sampling voltage, exceeds a preset condition, and therefore the current comparison circuit 30 outputs a comparison signal to the judgment module 33, and the judgment module 33 determines that the sun black sub-effect exists on the image output by the photosensitive module 31 according to the comparison signal; otherwise, the current comparison circuit 30 outputs a comparison signal, and the judging module 33 determines that the image in the photosensitive module 30 has no solar black effect according to the low-level comparison signal.
In still other embodiments, the judging module 33 includes a counter, when the current comparing circuit 30 outputs a high level comparing signal, the counter counts to directly output a full width, for example, the counter is 10 bits, and the judging module 33 outputs DATA data_out as 1023, or eclp_out does not affect the counter count, and the DATA can be given to the digital part to be comprehensively processed, so that the terminal DATA output to IO by the CIS system is full width, and the processing is finally performed in any way to form a bright point from original zero signal black to maximum signal in the image.
In some embodiments, fig. 2 is a schematic diagram of a first circuit structure of the current comparing circuit according to the present invention, and referring to fig. 2, the current comparing circuit 30 includes a first capacitor unit 10, a second capacitor unit 11, a first inverter unit 12, a second inverter unit 13, a first bias analog input unit 14, a second bias analog input unit 15, a first switch unit 16, a second switch unit 17, and a current sampling unit 18;
the first switch unit 16 is connected to the first capacitor unit 10, the second switch unit 17 is connected to the second capacitor unit 11, the first switch unit 16 and the second switch unit 17 are all connected to sampling output ends, the first capacitor unit 10 and the current sampling unit 18 are all connected to the first offset analog input unit 14, the second capacitor unit 11 and the current sampling unit 18 are all connected to the second offset analog input unit 15, the current sampling unit 18, the first switch unit 16 and the second switch unit 17 are all connected to the first inverter unit 12, and the current sampling unit 18 is also connected to the input end of the second inverter unit 13.
Specifically, the first capacitance unit 10 includes a first NMOS 101 and a first capacitor 102, where a source of the first NMOS 101 and one end of the first capacitor 102 are grounded, a gate of the first NMOS 101 is connected to the other end of the first capacitor 102, and a drain of the first NMOS 101 is connected to the first bias analog input unit 14;
the second capacitance unit 11 includes a fourth NMOS tube 111 and a second capacitance 112, where a source of the fourth NMOS tube 111 and one end of the second capacitance 112 are both grounded, a gate of the fourth NMOS tube 111 is connected to the other end of the second capacitance 112, and a drain of the fourth NMOS tube 111 is connected to the second bias analog input unit 15;
the first inverter unit 12 includes a first inverter 121 and a second inverter 122, an enable signal is input to an input terminal of the first inverter 121, an output terminal of the first inverter 121 is connected to an input terminal of the second inverter 122, and an output terminal of the second inverter 122 is connected to the current sampling unit 18;
the second inverter unit 13 includes a third inverter 131 and a fourth inverter 132, wherein an input end of the third inverter 131 is connected to the current sampling unit 18, an output end of the third inverter 131 is connected to an input end of the fourth inverter 132, and an output end of the fourth inverter 132 outputs a detection result;
The first switch unit 16 includes a first switch 161 and a fifth NMOS tube 162, one end of the first switch 161 is connected to the sampling output end, the other end of the first switch 161 is connected to the gate of the first NMOS tube 101, the gate of the fifth NMOS tube 162 is connected to the output end of the first inverter 121, the drain of the fifth NMOS tube 162 is connected to the other end of the first switch 161, and the source of the fifth NMOS tube 162 is grounded;
the second switch unit 17 includes a second switch 171 and a sixth NMOS tube 172, one end of the second switch 171 is connected to the sampling output end, the other end of the second switch 171 is connected to the gate of the fourth NMOS tube 111, the drain of the sixth NMOS tube 172 is connected to the other end of the second switch 171, the gate of the sixth NMOS tube 172 is connected to the output end of the first inverter 121, and the source of the sixth NMOS tube 172 is grounded;
the current sampling unit 18 includes a first PMOS transistor 181, a second PMOS transistor 182, and a third PMOS transistor 183, where the source of the first PMOS transistor 181, the source of the second PMOS transistor 182, and the source of the third PMOS transistor 183 are all connected to an operating voltage, the gate of the first PMOS transistor 181 is connected to the gate of the second PMOS transistor 182, the drain of the second PMOS transistor 182 is connected to the input of the third inverter 131, the drain of the first PMOS transistor 181 is connected to the gate of the first PMOS transistor 181, the drain of the third PMOS transistor 183, and the drain of the first NMOS transistor 101 are all connected to the first bias analog input unit 14, the gate of the third PMOS transistor 183 is connected to the output of the second inverter 122, and the drain of the second PMOS transistor 182 and the drain of the fourth NMOS transistor 111 are all connected to the second bias analog input unit 15.
In some embodiments, the first bias analog input unit 14 includes a second NMOS transistor 141, a gate of the second NMOS transistor 141 is connected to a first bias voltage, a source of the second NMOS transistor is grounded, and a drain of the second NMOS transistor 141 is connected to a drain of the first NMOS transistor 101 and a drain of the first PMOS transistor 181;
the second bias analog input unit 15 includes a third NMOS transistor 151, a gate of the third NMOS transistor 151 is connected to a second bias voltage, a source of the third NMOS transistor 151 is grounded, and a drain of the third NMOS transistor 151 is connected to a drain of the second PMOS transistor 12 and a drain of the fourth NMOS transistor 111.
It should be noted that, the circuit power supply of the current comparison circuit 30 adopts an analog power supply AVDD (not labeled in the figure), and a power supply ground AVSS (not labeled in the figure), wherein the first bias voltage VBN1 and the second bias voltage VBN2 belong to an analog bias portion, and are provided to the full-array current comparison circuit 30 for use, and the analog bias voltage is generated and adjustable by the ADC main bias circuit.
The following describes the present scheme in detail with reference to the current comparison circuit with the above circuit structure, and fig. 3 is a timing chart of control signals in the present invention, and in addition to the conventional CIS control timing, the eclp_det and eclp_sh signals need to be added. Wherein eclp_det is used as an enable signal of the current comparing circuit 30, and when the signal is low, it indicates that the current comparing circuit 30 is not operated, and the current comparing circuit 30 is in an off state so that no power consumption is generated; eclp_sh is a pulse signal sampled by the current comparing circuit 30 from the output vpix_out of the photosensitive module 31, and indicates that sampling is on when the signal is high, while TX, RX, SEL in fig. 3 are control signals corresponding to the photosensitive module 31 in fig. 1, RAMP is a reference RAMP of the judging module 33, and is typically generated by a digital-to-analog converter DAC, and rst_cm is a reset signal of the judging module 33.
Fig. 4 is a schematic diagram of related timing and signals of the CIS image system under normal operation, referring to fig. 4, when the CIS image system is in normal operation, a first sampling voltage sampled by the current comparison circuit 30 under a first sampling signal is denoted as Vpix1, and a second sampling voltage sampled by the current comparison circuit 30 under a second sampling signal is denoted as Vpix2, wherein the timing of the first sampling signal is before the timing of the second sampling signal. Signals irrelevant to the description are omitted in fig. 3, wherein VPIX is the pixel output voltage of the output terminal of the photosensitive module 31, voltages between VPIX1 and VPIX2 are all reset phase voltages, ramp_cm is the voltage signal of one input terminal of the judging module 33, and vpix_cm is the voltage signal of the other input terminal of the judging module 33. When the input light source in the image is not yet strong enough for the pixel to undergo the solar black sub-effect, the two voltages Vpix1 and Vpix2 sampled by eclp_sh are of approximately the same magnitude.
Fig. 5 is a schematic diagram of timing and signals related to normal operation of the CIS image system under relatively high light, when the light intensity is enhanced, as shown in fig. 5, the reset voltage can be reduced but not greatly, and still the ramp_cm and vpix_cm can generate the intersection point at this stage, so that the output of the judging module 33 can be inverted to generate a corresponding logic signal, and the value range in RAMP in fig. 3 is designed so that the voltage difference between VPIX1 and VPIX2 does not exceed the preset comparison threshold, so that the pixel light signal can be converted normally.
Fig. 6 is a schematic diagram of related timing and signals when the CIS image system works normally under super-strong light and the sun black effect occurs, referring to fig. 6, the reset voltage drops seriously under super-strong light, the reset voltage and the photoelectric conversion voltage are already equal, the signal is zero at the moment in the system working principle, which is not practical, the vpix_cm drops by an amplitude exceeding the range of ramp_cm, and no intersection point exists, that is, the voltage difference between VPIX1 and VPIX2 exceeds the preset comparison threshold. From fig. 5 and 6, it is apparent that the voltages Vpix1 and Vpix2 sampled by eclp_sh have been different from the case shown in fig. 4, vpix2< Vpix1. However, the system in the case of fig. 5 is also able to convert the light signal normally, so detecting the difference between Vpix1 and Vpix2 should leave a margin in the current comparison circuit 30, i.e. the voltage difference between Vpix1 and Vpix2 does not exceed the preset comparison threshold in fig. 5, i.e. the current comparison circuit 30 does not generate a valid eclp_out corresponding to the voltage vp_delta in fig. 5; corresponding to the situation in fig. 6, the output signal eclp_out of the current comparing circuit 30 is high, which indicates that the solar black detection is effective, whereas vp_delta is generally around 200mv, i.e. if the Vpix2 voltage is lower than the Vpix1 voltage by 200mv or more, the output eclp_out is high, which indicates that the solar black detection is effective.
Specifically, in fig. 2, VBN1 and VBN2 come from a current bias circuit, the bias circuit is a conventionally used functional module, and is multiplexed by a main bias circuit at the top layer of an ADC, the first inverter 121 and the fourth inverter 132 are all the same size, the second inverter 122 and the third inverter 131 are all the same size, and the inverters in fig. 2 are all logic gates operating under an analog power supply rail, so in order to communicate with digital signals, corresponding Level-Shift transmission gates need to be added at a front stage of an input signal and a rear stage of an output signal in addition to the analog signal. The final purpose of the current comparison circuit 30 is to detect whether the pixel reset voltage drop amplitude is too large by sampling the VPIX _ OUT voltage twice before and after, and to output a corresponding decision logic level if so. When the comparator reset phase, i.e., rst_cm, is high, eclp_det turns on the EDC circuit, when eclp_sh is high, corresponding to the signals S1 and S2 in fig. 3 being both high, the first switch 161 and the second switch 171 are turned on to sample vpix_out to the first capacitor 102 and the second capacitor 112, then the end of eclp_sh pulse S1 and S2 are low, the first switch 161 and the second switch 171 are turned off, and the gate voltages of the first NMOS transistor 101 and the fourth NMOS transistor 111 are maintained and the current directly reflects the magnitude of vpix_out, and the currents of these two MOS transistors are equal because the voltages are equal.
Wherein, eclp_det and switch control signals S1, S2 belong to a digital control part, and are generated by an internal logic circuit of the ADC, which is not described herein.
The current comparison circuit 30 has not completed the entire detection process at the first sampling, and since eclp_out is high indicating that solar black detection is active, the output eclp_out should be low. The size relationship between VBN2 and VNB1 is regulated to VBN2>VBN1, currents of the first NMOS transistor 101, the second NMOS transistor 141, the third NMOS transistor 151, and the fourth NMOS transistor 111 are respectively denoted as INM1, INM2, INM3, INM4, I 1 Indicating the current flowing through the first PMOS tube 181, I 2 Representing the current flowing through the second PMOS transistor 182, in conjunction with the labels in the figures, the first sampling each current relationship may be expressed as:
I NM1 ＝I NM4
I 1 ＝I NM1 +I NM2
I 3 ＝I NM3 +I NM4
I 1 ＝I 2
I NM2 <I NM3
it is easy to see I 2 <I 3 In fig. 2, the node OUT is pulled low in the circuit at the drain of the second PMOS transistor 182, and the output eclp_out is low. After the judgment module 33 is reset to the end of the first ramp, the eclp_sh pulse is valid again, and only the second switch 171 is turned on in the judgment module 33, that is, S1 keeps low level so that the first switch 161 is turned off, and S2 starts a pulse again so that the second switch 171 is turned on, so that the voltage of the first capacitor 102 remains unchanged, the voltage vpix_out is sampled by the second capacitor 112, and the current of the fourth NMOS transistor 111 is also changed to reflect the magnitude of the current pixel voltage signal. When the second sampling is completed, the current comparison circuit 30 completes the detection process, and I 2 And I 3 The relative magnitude relationship will change due to the second sampling, I due to the first NMOS 101 still maintaining the current magnitude of the first sampling 2 The current value is approximately constant. While the fourth NMOS tube 111 current decreases with decreasing sampling voltage, when NM4 current decreases to a certain value, I is caused 3 <I 2 In the second PMOS tubeThe circuit node OUT at the drain of 182 will be pulled high, thus outputting ECLP_OUT high, indicating that solar black spot detection is active; if the fourth NMOS tube 111 current is not reduced sufficiently, then continue to hold I3>I2, the ECLP_OUT output remains low, indicating that the solar black detection is not valid.
Fig. 7 is a schematic diagram of a logic signal processing circuit of the switch control signals S1 and S2 in the embodiment of the invention, as shown in fig. 7, and a logic gate processing circuit of the switch control signals S1 and S2 and control timings rst_cm, eclp_sh, eclp_det in the current comparison circuit 30, and the corresponding timings and output results are shown in fig. 8 and 9. Wherein fig. 8 shows that the reset voltage drops by an insufficient magnitude, the output eclp_out is not flipped, the eclp_out output remains low, the solar black detection is not valid, and fig. 9 shows that the reset voltage drops to reach the preset comparison threshold of the current comparison circuit 30, the eclp_out has flipped, and the output eclp_out is high, indicating that the solar black detection is valid.
As described above, in the description with reference to fig. 5 and 6, it is assumed that the preset comparison threshold of the current comparison circuit 30 is vpix_out decreased by about 200mv, so that the current of the fourth NMOS tube 111 after the second sampling is I NM4_2 Compared with the first sampling current I NM4 The reduced value is Δi, the following relationship can be obtained:
I NM1 ＝I NM4 ＝I NM4_2 +ΔI
that is to say when I NM4 After decreasing ΔI, the corresponding VPIX_OUT decrease is about 200mv, and ECLP_OUT should be flipped from low to high, determining that the current has the following relationship when detecting the flipped threshold:
I 2 ＝I 3
I 2 ＝I NM1 +I NM2
I 3 ＝I NM3 +I NM4 -ΔI
the current relationship of NM2 and NM3 can then be obtained
I NM2 ＝I NM3 -ΔI
Delta I in the above formula is the current comparison margin reserved for the circuit.
In summary, the current relationship of each path in the EDC circuit may be basically determined by the MOS transistor size parameters, and for example, in fig. 2, since the overall power consumption of the circuit is determined by the NMOS transistors, all NMOS transistors in the circuit use the inverse ratio transistor, and the static power consumption may be set to about 1 uA. First, about 300nA of each NMOS path is drawn, and the reset voltage is estimated to be about 1.8-1.2 v according to the experimental value of the test, so that the simulation can determine the sizes and the delta I values of the first NMOS tube 101 and the fourth NMOS tube 111, and the values of the first bias voltage VBN1 and the second bias voltage VBN2 can be determined. It should be noted here that the first bias voltage VBN1 and the second bias voltage VBN2 need to be trimmed to make trimming shift, so as to adjust the detection margin Δi during actual testing to set a suitable vpix_out detection value, and this control function is implemented by the bias circuit. When eclp_det is low and the current comparison circuit is turned off, the whole circuit is completely turned off through the fifth NMOS transistor 162, the sixth NMOS transistor 172 and the third PMOS transistor 183, and simultaneously the first bias voltage VBN1 and the second bias voltage VBN2 are both pulled to the ground potential, so that the circuit is completely turned off, and the power consumption can be ignored. The average power consumption of the entire current comparison circuit 30 is relatively low throughout the operating period.
The invention is based on the phenomenon of solar black effect, and the image sensor based on the SS-ADC architecture samples the pixel output voltage twice successively, compared with the use of MOS tube clamp or voltage comparator, the invention converts the voltage signals detected twice into current signals for comparison, and does not need to provide a globally used fixed reference signal, thus avoiding the need of adjusting the reference signal due to the potential difference between different slices. Since the signals sampled twice are the output values of the same pixel, the difference value compared by the signals of the same pixel at different moments is absolute, so that no external reference signal is needed and no potential difference is worried. Meanwhile, the circuit for realizing the sampling and current comparison can be simple and diversified, and the power consumption is easier to lower due to the simple structure.
In some embodiments, fig. 10 is a schematic diagram of a second circuit structure of the current comparing circuit according to the present invention, referring to fig. 10, in order to further determine the power consumption of the entire current comparing circuit 30, the current comparing circuit 30 further includes a first input unit 20 and a second input unit 19;
The first bias analog input unit 14 includes a seventh NMOS transistor 143, an eighth NMOS transistor 144, and a ninth NMOS transistor 142, wherein a drain of the ninth NMOS transistor 142 is connected to a drain of the first PMOS transistor 181, a gate of the ninth NMOS transistor 142 is connected to a drain of the eighth NMOS transistor 144 and a gate of the seventh NMOS transistor 143, a gate of the eighth NMOS transistor 144 is connected to an output end ENP of the first inverter 121, a source of the seventh NMOS transistor 143, a source of the eighth NMOS transistor 144, and a source of the ninth NMOS transistor 142 are all grounded, a gate of the seventh NMOS transistor 143 is connected to a drain of the seventh NMOS transistor 143, and a drain of the seventh NMOS transistor 143 is connected to a drain of the first NMOS transistor 101 and the first input unit 20;
the second bias analog input unit 15 includes a tenth NMOS transistor 152, an eleventh NMOS transistor 153, and a twelfth NMOS transistor 154, wherein a drain of the twelfth NMOS transistor 154 is connected to a drain of the second PMOS transistor 182, a gate of the twelfth NMOS transistor 154 is connected to a drain of the eleventh NMOS transistor 153 and a gate of the tenth NMOS transistor 152, a gate of the eleventh NMOS transistor 153 is connected to an output end ENP of the first inverter 121, a drain of the tenth NMOS transistor 152 is connected to a gate of the tenth NMOS transistor 152, a drain of the fourth NMOS transistor 111, and the second input unit 21, respectively, and a source of the tenth NMOS transistor 152, a source of the eleventh NMOS transistor 153, and a source of the twelfth NMOS transistor 154 are all grounded;
The first input unit 20 includes a fourth PMOS transistor 201, a fifth PMOS transistor 202, and a sixth PMOS transistor 203, where a source of the fourth PMOS transistor 201 is connected to a first bias voltage VPB1, a gate of the fourth PMOS transistor 201 is connected to an output end ENP of the first inverter 121, a drain of the fourth PMOS transistor 201 is connected to a drain of the fifth PMOS transistor 202 and a gate of the sixth PMOS transistor 203, a gate of the fifth PMOS transistor 202 is connected to an output end ENN of the second inverter 122, sources of the fifth PMOS transistor 202 and the sixth PMOS transistor 203 are both connected to a working voltage, and a drain of the sixth PMOS transistor 203 is connected to a drain of the seventh NMOS transistor 143 and a drain of the first NMOS transistor 101;
the second input unit 19 includes a seventh PMOS tube 191, an eighth PMOS tube 192, and a ninth PMOS tube 193, where a source of the seventh PMOS tube 191 is connected to a second bias voltage VPB2, a gate of the seventh PMOS tube 191 is connected to an output end ENP of the first inverter 121, a drain of the seventh PMOS tube 191 is connected to a gate of the eighth PMOS tube 192 and a drain of the ninth PMOS tube 193, a gate of the ninth PMOS tube 193 is connected to an output end ENN of the second inverter 122, sources of the eighth PMOS tube 192 and the ninth PMOS tube 193 are both connected to an operating voltage, and a drain of the eighth PMOS tube 192 is connected to a drain of the tenth NMOS tube 152 and a drain of the fourth NMOS tube 111.
The power consumption of the whole circuit is determined by the mirror bias current of the sixth PMOS tube 203 and the eighth PMOS tube 192 in the circuit, and the bias voltages VPB1 and VPB2 are similar to VBN1 and VBN2 in the principle of FIG. 2. The first NMOS tube 101 and the fourth NMOS tube 111 sample the vpix_out voltage to convert the voltage into a current, it is easy to see that the currents of the ninth NMOS tube 193 and the twelfth NMOS tube 154 are the currents of the sixth PMOS tube 203 and the eighth PMOS tube 192 minus the currents of the first NMOS tube 101 and the fourth NMOS tube 111, and since the currents passed by the sixth PMOS tube 203 and the eighth PMOS tube 192 are determined after the bias determination, the comparison of the currents of the ninth NMOS tube 193 and the twelfth NMOS tube 154, that is, the comparison of the currents of the first NMOS tube 101 and the fourth NMOS tube 111, the specific working principle is the same as that of fig. 2, and the effect achieved finally is the same, but the current comparison circuit in the embodiment is more controllable.
The implementation manner of the current comparison circuit 30 may also take other forms, and any current comparison circuit capable of implementing the function of the present scheme may be applied to the present scheme, which is not described herein.
In some embodiments, the signal control module 32 is further configured to generate an enable signal, where the current comparing circuit 30 is in an operating state when the enable signal is at a high level, and the current comparing circuit 30 is in an off state when the enable signal is at a low level, and the enable signal is used to control the on-off state of the current comparing circuit 30, so that the power consumption of the current comparing circuit 30 can be reduced when the current comparing circuit is not in use.
In some embodiments, the apparatus for detecting an image sun black effect further includes an output module 34 connected to the judging module 33, where the output module 34 converts a black signal area in the image signal into a maximum signal bright point for outputting after determining that the detected image sun black effect of the image signal in the photosensitive module 31 is effective according to the judging result output by the judging module 33. The black signal area with the sun black sub effect in the image is converted into the maximum signal bright point to be output through the output module 34, so that the image is restored, and the authenticity of the image is ensured.
The invention further discloses a method for detecting the sun black sub effect of an image, which is shown in fig. 11 and comprises the following steps:
s1101, sending a first sampling pulse signal and a second sampling pulse signal to the current comparison circuit through a signal control module;
s1102, the current comparison circuit samples the photosensitive module according to the first sampling pulse signal to obtain a first sampling voltage, and the current comparison circuit samples the photosensitive module according to the second sampling pulse signal to obtain a second sampling voltage;
s1103, obtaining a voltage difference value of the first sampling voltage and the second sampling voltage through the current comparison circuit, and outputting a comparison signal by the current comparison circuit according to the voltage difference value and a preset comparison threshold value;
S1104, receiving the comparison signal through a judging module, and outputting a judging result of the image sun black according to the comparison signal.
In some embodiments, the determining module may output a detection result of the sun black effect of the image according to the received level of the comparison signal, specifically, in step S1103, the voltage difference between the first sampled voltage and the second sampled voltage is obtained by the current comparing circuit, and the current comparing circuit outputs a comparison signal according to the voltage difference and a preset comparison threshold, where the step S1103 includes:
acquiring a voltage difference value of the first sampling voltage and the second sampling voltage, wherein the sampling time of the first sampling voltage is earlier than that of the second sampling voltage;
after determining that the voltage difference is greater than or equal to the preset comparison threshold, the current comparison circuit outputs a high-level comparison signal;
after determining that the voltage difference is smaller than the preset comparison threshold, the current comparison circuit outputs a low-level comparison signal;
the judging module receives the comparison signal and outputs a judging result of the image sun black according to the comparison signal, and the judging module comprises the following steps:
After the judging module receives the high-level comparison signal, the judging module outputs a detection image sun black sub-effect to be effective;
after the judging module receives the low-level comparison signal, the judging module outputs a detection image that the sun black sub effect is invalid.
Detecting pixel voltage signals of an image by the method for detecting the sun black effect of the image, sampling the output end of the photosensitive module to obtain a first sampling voltage and a second sampling voltage, calculating a voltage difference value between the second sampling voltage and the first sampling voltage, further judging the magnitude between the voltage difference value and a preset comparison threshold value, and outputting a high-level comparison signal by a current comparison circuit after determining that the voltage difference value is greater than or equal to the preset comparison threshold value, and outputting a judging result of effective sun black detection by a judging module; and after the voltage difference value is determined to be smaller than the preset comparison threshold value, the current comparison circuit outputs a low-level comparison signal, and the judgment module outputs a judgment result that the solar black sub effect of the detection image is invalid.
Compared with the method using MOS tube clamp or voltage comparator, the method provided by the invention has the advantages that the voltage signals detected twice are converted into current signals for comparison by sampling the pixel output voltage twice successively, and a global fixed reference signal is not required to be provided, so that the reference signal can be prevented from being adjusted due to potential difference among different slices. Since the signals sampled twice are the output values of the same pixel, the difference value compared by the signals of the same pixel at different moments is absolute, so that no external reference signal is needed and no potential difference is worried. Meanwhile, the circuit for realizing the sampling and current comparison can be simple and diversified, and the power consumption is easier to lower due to the simple structure, and the steps of the method for detecting the image solar black sub effect in the scheme are in one-to-one correspondence with the modules of the device for detecting the image solar black sub effect, so that the description is omitted.
In some embodiments, after the judging module outputs the effect of detecting the sun black in the image, the output module converts the black signal area in the image signal into the maximum signal bright point for outputting, so as to ensure that the finally output image can be normally output.
From the foregoing description of the embodiments, it will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of functional modules is illustrated, and in practical application, the above-described functional allocation may be implemented by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to implement all or part of the functions described above. The specific working processes of the above-described systems, devices and units may refer to the corresponding processes in the foregoing method embodiments, which are not described herein.
The functional units in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the embodiments of the present application may be essentially or a part contributing to the prior art or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the method described in the embodiments of the present application. And the aforementioned storage medium includes: flash memory, removable hard disk, read-only memory, random access memory, magnetic or optical disk, and the like.
The foregoing is merely a specific implementation of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited to this, and any changes or substitutions within the technical scope disclosed in the embodiment of the present application should be covered in the protection scope of the embodiment of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.
While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.

Claims (9)

1. The current comparison circuit is characterized by comprising a first capacitance unit, a second capacitance unit, a first inverter unit, a second inverter unit, a first bias analog input unit, a second bias analog input unit, a first switch unit, a second switch unit and a current sampling unit;
the first switch unit is connected with the first capacitor unit, the second switch unit is connected with the second capacitor unit, the first switch unit and the second switch unit are connected with sampling output ends, the first capacitor unit and the current sampling unit are connected with the first bias analog input unit, the second capacitor unit and the current sampling unit are connected with the second bias analog input unit, the current sampling unit, the first switch unit and the second switch unit are connected with the first inverter unit, and the current sampling unit is also connected with the input ends of the second inverter unit;
The first capacitance unit comprises a first NMOS tube and a first capacitance, wherein the source electrode of the first NMOS tube and one end of the first capacitance are grounded, the grid electrode of the first NMOS tube is connected with the other end of the first capacitance, and the drain electrode of the first NMOS tube is connected with the first bias analog input unit;
the second capacitance unit comprises a fourth NMOS tube and a second capacitance, wherein the source electrode of the fourth NMOS tube and one end of the second capacitance are grounded, the grid electrode of the fourth NMOS tube is connected with the other end of the second capacitance, and the drain electrode of the fourth NMOS tube is connected with the second bias analog input unit;
the first inverter unit comprises a first inverter and a second inverter, the input end of the first inverter is input with an enabling signal, the output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter is connected with the current sampling unit;
the second inverter unit comprises a third inverter and a fourth inverter, the input end of the third inverter is connected with the current sampling unit, the output end of the third inverter is connected with the input end of the fourth inverter, and the output end of the fourth inverter outputs a detection result;
The first switch unit comprises a first switch and a fifth NMOS tube, one end of the first switch is connected with the sampling output end, the other end of the first switch is connected with the grid electrode of the first NMOS tube, the grid electrode of the fifth NMOS tube is connected with the output end of the first inverter, the drain electrode of the fifth NMOS tube is connected with the other end of the first switch, and the source electrode of the fifth NMOS tube is grounded;
the second switch unit comprises a second switch and a sixth NMOS tube, one end of the second switch is connected with the sampling output end, the other end of the second switch is connected with the grid electrode of the fourth NMOS tube, the drain electrode of the sixth NMOS tube is connected with the other end of the second switch, the grid electrode of the sixth NMOS tube is connected with the output end of the first inverter, and the source electrode of the sixth NMOS tube is grounded;
the current sampling unit comprises a first PMOS tube, a second PMOS tube and a third PMOS tube, wherein the source electrode of the first PMOS tube, the source electrode of the second PMOS tube and the source electrode of the third PMOS tube are all connected with working voltages, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected with the input end of the third inverter, the drain electrode of the first PMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the first NMOS tube are all connected with the first bias analog input unit, the gate electrode of the third PMOS tube is connected with the output end of the second inverter, and the drain electrode of the second PMOS tube and the drain electrode of the fourth NMOS tube are all connected with the second bias analog input unit;
The first bias analog input unit comprises a second NMOS tube, the grid electrode of the second NMOS tube is connected with a first bias voltage, the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube and the drain electrode of the first PMOS tube;
the second bias analog input unit comprises a third NMOS tube, the grid electrode of the third NMOS tube is connected with a second bias voltage, the source electrode of the third NMOS tube is grounded, and the drain electrode of the third NMOS tube is connected with the drain electrode of the second PMOS tube and the drain electrode of the fourth NMOS tube.
2. The current comparison circuit of claim 1, further comprising a first input unit and a second input unit;
the first bias analog input unit comprises a seventh NMOS tube, an eighth NMOS tube and a ninth NMOS tube, wherein the drain electrode of the ninth NMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the ninth NMOS tube is connected with the drain electrode of the eighth NMOS tube and the grid electrode of the seventh NMOS tube, the grid electrode of the eighth NMOS tube is connected with the output end of the first inverter, the source electrode of the seventh NMOS tube, the source electrode of the eighth NMOS tube and the source electrode of the ninth NMOS tube are grounded, the grid electrode of the seventh NMOS tube is connected with the drain electrode of the seventh NMOS tube, and the drain electrode of the seventh NMOS tube is connected with the drain electrode of the first NMOS tube and the first input unit;
The second bias analog input unit comprises a tenth NMOS tube, an eleventh NMOS tube and a twelfth NMOS tube, wherein the drain electrode of the twelfth NMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the twelfth NMOS tube is connected with the drain electrode of the eleventh NMOS tube and the grid electrode of the tenth NMOS tube, the grid electrode of the eleventh NMOS tube is connected with the output end of the first inverter, the drain electrode of the tenth NMOS tube is respectively connected with the grid electrode of the tenth NMOS tube, the drain electrode of the fourth NMOS tube and the second input unit, and the source electrode of the tenth NMOS tube, the source electrode of the eleventh NMOS tube and the source electrode of the twelfth NMOS tube are all grounded;
the first input unit comprises a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube, wherein the source electrode of the fourth PMOS tube is connected with a first bias voltage, the grid electrode of the fourth PMOS tube is connected with the output end of the first inverter, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube, the grid electrode of the fifth PMOS tube is connected with the output end of the second inverter, the source electrodes of the fifth PMOS tube and the sixth PMOS tube are both connected with working voltages, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the seventh NMOS tube and the drain electrode of the first NMOS tube;
The second input unit comprises a seventh PMOS tube, an eighth PMOS tube and a ninth PMOS tube, wherein the source electrode of the seventh PMOS tube is connected with a second bias voltage, the grid electrode of the seventh PMOS tube is connected with the output end of the first inverter, the drain electrode of the seventh PMOS tube is connected with the grid electrode of the eighth PMOS tube and the drain electrode of the ninth PMOS tube, the grid electrode of the ninth PMOS tube is connected with the output end of the second inverter, the source electrodes of the eighth PMOS tube and the ninth PMOS tube are both connected with working voltages, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the tenth NMOS tube and the drain electrode of the fourth NMOS tube.
3. An apparatus for detecting the image sun black effect, comprising the current comparison circuit of any one of claims 1 to 2, the apparatus for detecting the image sun black effect further comprising:
the photosensitive module is used for outputting a pixel voltage signal according to the image signal;
the signal control module is connected with the current comparison circuit and is used for providing a control signal for the current comparison circuit;
and the judging module is connected with the photosensitive module and the output end of the current comparison circuit and is used for judging the sun black of the image according to the comparison signal of the current comparison circuit.
4. The apparatus for detecting an image solar black sub-effect according to claim 3, wherein the signal control module outputs a control signal to control the current comparison circuit to sample the photosensitive module twice in sequence and obtain a first sampling voltage and a second sampling voltage, the current comparison circuit outputs a comparison signal according to a difference value between the first sampling voltage and the second sampling voltage and a preset comparison threshold value, and the judgment module receives the comparison signal to output a judgment result of the image solar black sub-effect.
5. The apparatus for detecting a sun black sub effect according to claim 3, wherein the signal control module is further configured to generate an enable signal, wherein the current comparing circuit is in an operating state when the enable signal is at a high level, and wherein the current comparing circuit is in an off state when the enable signal is at a low level.
6. The apparatus for detecting an image sun black sub-effect according to claim 5, further comprising an output module connected to the judging module, wherein the output module converts a black signal area in the image signal into a maximum signal bright point to output after determining that the image sun black sub-effect of the image signal in the photosensitive module is detected effectively according to the judging result output by the judging module.
7. A method of detecting an image sun black effect according to any one of claims 3 to 6, comprising:
sending a first sampling pulse signal and a second sampling pulse signal to the current comparison circuit through a signal control module;
the current comparison circuit samples the first sampling pulse signal on the photosensitive module to obtain a first sampling voltage, and samples the second sampling pulse signal on the photosensitive module to obtain a second sampling voltage;
the current comparison circuit is used for obtaining a voltage difference value between the first sampling voltage and the second sampling voltage, and outputting a comparison signal according to the voltage difference value and a preset comparison threshold value;
and receiving the comparison signal through a judging module, and outputting a judging result of the image sun black according to the comparison signal.
8. The method of detecting the sun black effect of an image according to claim 7,
the judging module receives the comparison signal and outputs a judging result of the image sun black according to the comparison signal, and the judging module comprises the following steps:
And the judging module correspondingly outputs a detection result of the solar black sub effect of the image according to the level of the received comparison signal.
9. The method of claim 7, wherein after the judging module outputs the effect of detecting the image sun black, the black signal area in the image signal is converted into a maximum signal bright point output by the output module.
CN202111313697.4A 2021-11-08 2021-11-08 Current comparison circuit, device and method for detecting image solar black element effect Active CN113960356B (en)

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CN202068388U (en) * 2011-04-25 2011-12-07 上海集成电路研发中心有限公司 Current comparator
JP2018019354A (en) * 2016-07-29 2018-02-01 キヤノン株式会社 Imaging apparatus
CN110798637A (en) * 2019-11-29 2020-02-14 成都微光集电科技有限公司 Image sensor reading circuit and method for inhibiting sun black sub effect
CN111629161A (en) * 2019-02-28 2020-09-04 爱思开海力士有限公司 Comparator and image sensing device including the same
CN111787250A (en) * 2020-06-30 2020-10-16 成都微光集电科技有限公司 Comparator circuit, image sensing device and method

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Publication number Priority date Publication date Assignee Title
US5136184A (en) * 1991-05-24 1992-08-04 Analog Devices, Incorporated Fast-acting current comparator
CN102014017A (en) * 2010-09-30 2011-04-13 华为技术有限公司 Signal detection circuit, method and system
CN202068388U (en) * 2011-04-25 2011-12-07 上海集成电路研发中心有限公司 Current comparator
JP2018019354A (en) * 2016-07-29 2018-02-01 キヤノン株式会社 Imaging apparatus
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CN111629161A (en) * 2019-02-28 2020-09-04 爱思开海力士有限公司 Comparator and image sensing device including the same
CN110798637A (en) * 2019-11-29 2020-02-14 成都微光集电科技有限公司 Image sensor reading circuit and method for inhibiting sun black sub effect
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