CN112382664A - Flip MOSFET device and manufacturing method thereof - Google Patents
Flip MOSFET device and manufacturing method thereof Download PDFInfo
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- CN112382664A CN112382664A CN202011207956.0A CN202011207956A CN112382664A CN 112382664 A CN112382664 A CN 112382664A CN 202011207956 A CN202011207956 A CN 202011207956A CN 112382664 A CN112382664 A CN 112382664A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims abstract description 57
- 229910001195 gallium oxide Inorganic materials 0.000 claims abstract description 57
- 239000002086 nanomaterial Substances 0.000 claims abstract description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 230000017525 heat dissipation Effects 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 17
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims abstract description 14
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000002161 passivation Methods 0.000 claims abstract description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 12
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 12
- 239000002105 nanoparticle Substances 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 26
- 230000008569 process Effects 0.000 claims description 19
- 238000001312 dry etching Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005566 electron beam evaporation Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000009616 inductively coupled plasma Methods 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 3
- 238000011161 development Methods 0.000 abstract description 5
- 238000012827 research and development Methods 0.000 abstract description 3
- 238000013461 design Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 9
- 239000002253 acid Substances 0.000 description 6
- 239000007789 gas Substances 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910015844 BCl3 Inorganic materials 0.000 description 2
- 241001354791 Baliga Species 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3738—Semiconductor materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses a flip MOSFET device and a manufacturing method thereof, wherein the flip MOSFET device comprises a gallium oxide substrate, an n-type doped gallium oxide layer, an n-type heavily doped gallium oxide layer, a silicon dioxide passivation layer, an aluminum oxide dielectric layer, a bonding layer and an aluminum nitride heat conduction layer which are sequentially arranged from top to bottom; a source electrode and a drain electrode are arranged between the n-type heavily doped gallium oxide layer and the silicon dioxide passivation layer, and a gate electrode is arranged on the aluminum oxide dielectric layer; and a heat dissipation structure formed by a micro-nano structure array is etched on the free end face of the gallium oxide substrate, and the cross section of the micro-nano structure is micron-sized or nano-sized. According to the invention, the micro-nano structure array is etched on the surface of the gallium oxide substrate, so that the heat dissipation efficiency is improved. Compared with the radiator of the electronic device, the invention reserves the heat dissipation window in the design stage of the device, shortens the development time of the device and reduces the research and development cost of the device on the premise of ensuring the service life and the reliability of the high-power device.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a flip MOSFET device and a manufacturing method thereof.
Background
Gallium oxide (Ga)2O3) The third generation wide band gap semiconductor material has the advantages of an ultra-wide band gap (4.9eV), ultra-high breakdown field strength (8MV/cm) and ultra-high Baliga figure of merit (3444). The Baliga optimum of gallium oxide is four and ten times that of GaN and SiC, respectively, providing a wider field of view for the development of power devices. However, gallium oxide has very low thermal conductivity, which is about 1/10 of GaN, SiC and other materials, and thus, local temperature of electronic devices such as high-temperature, high-frequency and high-power gallium oxide-based electronic devices is very high, which may cause problems such as poor reliability of the devices and reduction of output power. Therefore, the heat dissipation problem becomes a key bottleneck restricting the development of the gallium oxide power device.
For the heat dissipation problem of a gallium Oxide-Semiconductor Field-Effect Transistor (MOSFET) device, the prior art generally solves the heat dissipation problem by the following two ways: 1. heteroepitaxially growing or bonding a material with excellent thermal conductivity on the gallium oxide material so as to improve the heat conduction efficiency; however, the high temperature environment required for epitaxy and bonding can introduce residual stress, which can lead to material delamination and edge bending, and can seriously affect device performance. 2. Utilize the thermal module to dispel the heat at the back end encapsulation stage, if: heat-conducting silicone grease, heat-conducting silicone pieces, fans and the like; and the heat dissipation problem of the device is considered in the back end packaging stage, so that the development time can be prolonged, and the research and development cost of the device can be increased.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention aims to provide a flip-chip MOSFET device and a manufacturing method thereof.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a flip MOSFET device comprises a gallium oxide substrate, an n-type doped gallium oxide layer, an n-type heavily doped gallium oxide layer, a silicon dioxide passivation layer, an aluminum oxide medium layer, a bonding layer and an aluminum nitride heat conduction layer which are sequentially arranged from top to bottom; a source electrode and a drain electrode are arranged between the n-type heavily doped gallium oxide layer and the silicon dioxide passivation layer, and a gate electrode is arranged on the aluminum oxide dielectric layer; and a heat dissipation structure formed by a micro-nano structure array is etched on the free end face of the gallium oxide substrate, and the cross section of the micro-nano structure is micron-sized or nano-sized.
Preferably, the height of the micro-nano structure is 500 nm-10 μm, the length of the micro-nano structure is 1 μm-100 μm, the length of the bottom edge of the cross section is 200 nm-5 μm, and the distance between the adjacent micro-nano structures is 200 nm-10 μm. Researches find that the micro-nano structure size is smaller than the radiation wavelength, which is the basis for ensuring the high-efficiency heat dissipation effect. The wavelength range in the heat radiation is infrared wave of 8-13 μm, the efficiency of the atmospheric radiation is high, and the heat dissipation effect is good. The size of the micro-nano structure is smaller than the wavelength of the wave band, so that the high-efficiency heat dissipation effect can be ensured.
Preferably, the cross section of the micro-nano structure is in a geometric shape with a narrow top and a wide bottom, such as: trapezoidal, triangular, etc.
Preferably, the micro-nano structure is manufactured by adopting a dry etching process or a wet etching process.
The gas adopted by the dry etching process comprises Cl2、BCl3、SF6、Ar、CF4/O2One or more combinations of mixed gases.
In some embodiments, the acid used in the wet etching process is HF acid, and the temperature of the acid solution is between room temperature and 200 ℃.
Preferably, the material of the source electrode, the drain electrode and the gate electrode is one of Al, Ti, Pd, Pt and Au.
The invention also provides a manufacturing method of the flip MOSFET device, which comprises the following steps:
(1) manufacturing a gallium oxide-based MOSFET device:
a: depositing an n-type doped gallium oxide layer and an n-type heavily doped gallium oxide layer on a gallium oxide substrate in sequence by using a chemical vapor deposition method;
b: setting a source electrode and a drain electrode by electron beam evaporation;
c: etching a channel by utilizing an ICP (inductively coupled plasma) process, and depositing a silicon dioxide passivation layer and an aluminum oxide medium layer by utilizing a chemical vapor deposition method;
d: setting a gate electrode by electron beam evaporation to prepare the gallium oxide-based MOSFET device;
(2) manufacturing a heat dissipation structure:
etching the micro-nano structure array on the free end face of the gallium oxide substrate of the gallium oxide-based MOSFET device by using a dry etching process or a wet etching process;
(3) inversely welding the gallium oxide-based MOSFET device on an aluminum nitride carrier to obtain an inversely-welded MOSFET device; the aluminum nitride carrier consists of a bonding layer and an aluminum nitride heat conduction layer.
Compared with the prior art, the invention has the beneficial effects that: according to the invention, a micro-nano structure array with a specific size is etched on the surface of the gallium oxide substrate by adopting a dry etching or wet etching process, the cross section of the micro-nano structure is in a geometric shape with a narrow top and a wide bottom, and the material proportion is changed in a gradient manner from top to bottom, so that the gradient change of the refractive index of the material can be caused, the radiation bandwidth is effectively improved, and the heat dissipation efficiency is improved. The invention solves the heat dissipation problem of the gallium oxide-based MOSFET device, reserves the heat dissipation window in the design stage of the gallium oxide-based MOSFET device, shortens the development time of the device and reduces the research and development cost of the device on the premise of ensuring the service life and the reliability of a high-power device.
Drawings
FIG. 1 is a schematic diagram of a flip-chip MOSFET device according to the present invention;
FIG. 2 is a schematic structural diagram of the micro-nano structure (A-section is triangle; B-section is trapezoid).
In fig. 1, a gallium oxide substrate 1, a micro-nano structure array 2, an n-type doped gallium oxide layer 3, an n-type heavily doped gallium oxide layer 4, a silicon dioxide passivation layer 5, an aluminum oxide dielectric layer 6, a source electrode 7, a gate electrode 8, a drain electrode 9, a bonding layer 10, and an aluminum nitride heat conduction layer 11.
Detailed Description
The technical solutions of the present invention will be further described with reference to the following embodiments and the accompanying drawings, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. The starting materials used in the examples are commercially available and the methods or process conditions used are conventional in the art unless otherwise specified.
As shown in fig. 1-2, the present embodiment provides a flip-chip MOSFET device, which includes a gallium oxide substrate 1, an n-type doped gallium oxide layer 3, an n-type heavily doped gallium oxide layer 4, a silicon dioxide passivation layer 5, an aluminum oxide dielectric layer 6, a bonding layer 10, and an aluminum nitride heat conduction layer 11, which are sequentially stacked from top to bottom. Wherein, a source electrode 7 and a drain electrode 9 are arranged between the n-type heavily doped gallium oxide layer 4 and the silicon dioxide passivation layer 5, and a gate electrode 8 is arranged on the aluminum oxide dielectric layer 6. And a micro-nano structure array 2 is etched on the free end face of the gallium oxide substrate 1, and the cross section area of the micro-nano structure array 2 is micron-scale or nano-scale. Correspondingly, the height of the micro-nano structure array 2 is 500 nm-10 μm, the length is 1 μm-100 μm, the length of the bottom edge of the cross section is 200 nm-5 μm, and the distance between adjacent micro-nano structure arrays 2 is 200 nm-10 μm. Moreover, the cross section of the micro-nano structure array 2 is in a geometric shape with a narrow top and a wide bottom, such as: trapezoidal, triangular, etc. The material of the source electrode 7, the gate electrode 8 and the drain electrode 9 is one of Al, Ti, Pd, Pt and Au.
The manufacturing method of the flip-chip MOSFET device comprises the following steps:
(1) manufacturing a gallium oxide-based MOSFET device:
a: depositing an n-type doped gallium oxide layer 3 and an n-type heavily doped gallium oxide layer 4 on a gallium oxide substrate 1 in sequence by using a chemical vapor deposition method;
b: setting a source electrode 7 and a drain electrode 9 by electron beam evaporation;
c: etching a channel by utilizing an ICP (inductively coupled plasma) process, and depositing a silicon dioxide passivation layer 5 and an aluminum oxide medium layer 6 by utilizing a chemical vapor deposition method;
d: arranging a gate electrode 8 by electron beam evaporation to prepare the gallium oxide-based MOSFET device;
(2) manufacturing a heat dissipation structure:
etching the micro-nano structure array 2 on the free end face of the gallium oxide substrate 1 of the gallium oxide-based MOSFET device by using a dry etching process or a wet etching process; wherein, the gas adopted by the dry etching process can be Cl2、BCl3、SF6、Ar、CF4/O2One or more of the mixed gases are combined, the acid adopted by the wet etching process can be HF acid, and the temperature of the acid solution is between room temperature and 200 ℃;
(3) inversely welding the gallium oxide-based MOSFET device on an aluminum nitride carrier to obtain an inversely-welded MOSFET device; the aluminum nitride carrier is composed of a bonding layer 10 and an aluminum nitride heat conduction layer 11.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting the protection scope of the present invention, and although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.
Claims (6)
1. A flip MOSFET device is characterized by comprising a gallium oxide substrate, an n-type doped gallium oxide layer, an n-type heavily doped gallium oxide layer, a silicon dioxide passivation layer, an aluminum oxide medium layer, a bonding layer and an aluminum nitride heat conduction layer which are sequentially arranged from top to bottom; a source electrode and a drain electrode are arranged between the n-type heavily doped gallium oxide layer and the silicon dioxide passivation layer, and a gate electrode is arranged on the aluminum oxide dielectric layer; and a heat dissipation structure formed by a micro-nano structure array is etched on the free end face of the gallium oxide substrate, and the cross section of the micro-nano structure is micron-sized or nano-sized.
2. The flip-chip MOSFET device of claim 1, wherein the micro-nano structures have a height of 500nm to 10 μm, a length of 1 μm to 100 μm, a length of a bottom side of a cross section of 200nm to 5 μm, and a pitch between adjacent micro-nano structures of 200nm to 10 μm.
3. The flip-chip MOSFET device of claim 1, wherein the micro-nano structure has a cross-section with a narrow top and a wide bottom geometry.
4. The flip-chip MOSFET device of claim 1, wherein the micro-nano structure is fabricated using a dry etching process or a wet etching process.
5. The flip-chip MOSFET device of claim 1, wherein the source, drain and gate electrodes are made of one of Al, Ti, Pd, Pt, Au.
6. A method of fabricating a flip-chip MOSFET device according to any one of claims 1 to 5, comprising the steps of:
(1) manufacturing a gallium oxide-based MOSFET device:
a: depositing an n-type doped gallium oxide layer and an n-type heavily doped gallium oxide layer on a gallium oxide substrate in sequence by using a chemical vapor deposition method;
b: setting a source electrode and a drain electrode by electron beam evaporation;
c: etching a channel by utilizing an ICP (inductively coupled plasma) process, and depositing a silicon dioxide passivation layer and an aluminum oxide medium layer by utilizing a chemical vapor deposition method;
d: setting a gate electrode by electron beam evaporation to prepare the gallium oxide-based MOSFET device;
(2) manufacturing a heat dissipation structure:
etching the micro-nano structure array on the free end face of the gallium oxide substrate of the gallium oxide-based MOSFET device by using a dry etching process or a wet etching process;
(3) inversely welding the gallium oxide-based MOSFET device on an aluminum nitride carrier to obtain an inversely-welded MOSFET device; the aluminum nitride carrier consists of a bonding layer and an aluminum nitride heat conduction layer.
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| CN202011207956.0A CN112382664A (en) | 2020-11-03 | 2020-11-03 | Flip MOSFET device and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114446904A (en) * | 2021-12-30 | 2022-05-06 | 光梓信息科技(深圳)有限公司 | Wafer packaging structure and method based on nanoscale radiator |
| CN116631847A (en) * | 2023-05-04 | 2023-08-22 | 中国科学院上海微***与信息技术研究所 | Gallium oxide heterogeneous integrated structure and preparation method thereof |
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| JP2015002293A (en) * | 2013-06-17 | 2015-01-05 | 株式会社タムラ製作所 | Ga2O3-BASED SEMICONDUCTOR ELEMENT |
| US20180114693A1 (en) * | 2016-10-20 | 2018-04-26 | QROMIS, Inc. | Method and system for integration of elemental and compound semiconductors on a ceramic substrate |
| CN109103091A (en) * | 2018-07-11 | 2018-12-28 | 西安电子科技大学 | Ga2O3The process for transferring epitaxial layer of base MOSFET element |
| CN109923678A (en) * | 2016-11-09 | 2019-06-21 | Tdk株式会社 | Schottky barrier diode and the electronic circuit for having it |
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- 2020-11-03 CN CN202011207956.0A patent/CN112382664A/en active Pending
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| JP2015002293A (en) * | 2013-06-17 | 2015-01-05 | 株式会社タムラ製作所 | Ga2O3-BASED SEMICONDUCTOR ELEMENT |
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| US20180114693A1 (en) * | 2016-10-20 | 2018-04-26 | QROMIS, Inc. | Method and system for integration of elemental and compound semiconductors on a ceramic substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114446904A (en) * | 2021-12-30 | 2022-05-06 | 光梓信息科技(深圳)有限公司 | Wafer packaging structure and method based on nanoscale radiator |
| CN116631847A (en) * | 2023-05-04 | 2023-08-22 | 中国科学院上海微***与信息技术研究所 | Gallium oxide heterogeneous integrated structure and preparation method thereof |
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