CN114613770A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
CN114613770A
CN114613770A CN202210200010.4A CN202210200010A CN114613770A CN 114613770 A CN114613770 A CN 114613770A CN 202210200010 A CN202210200010 A CN 202210200010A CN 114613770 A CN114613770 A CN 114613770A
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layer
gate
dielectric layer
nanowire
gate dielectric
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李永亮
张佳熠
殷华湘
罗军
王文武
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET

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Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for solving the problem of poor compatibility when the device structures of a core device and an input/output device are all ring gate transistors. The semiconductor device includes: the transistor comprises a substrate, a first gate-all-around transistor and a second gate-all-around transistor. A first gate-all-around transistor is formed on a first element region provided on a substrate. The periphery of at least one layer of first nanowire or piece of the first gate-all-around transistor is sequentially surrounded by a first gate dielectric layer and a second gate dielectric layer. A second ring-gate transistor is formed on a second element region provided on the substrate. The second ring gate transistor has at least one layer of second nanowire or chip surrounded by a third gate dielectric layer. The total thickness of the first gate dielectric layer and the second gate dielectric layer is larger than that of the third gate dielectric layer. The thickness of the first nanowire or patch is less than the thickness of the second nanowire or patch. The semiconductor device includes a number of layers of the first nanowire or patch equal to a number of layers of the second nanowire or patch.

Description

Semiconductor device and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
The gate-all-around transistor has the advantages of higher gate control capability and the like compared with a planar transistor and a fin field effect transistor, so that the working performance of an integrated circuit comprising the core device can be improved when the device structure of the core device is the gate-all-around transistor.
However, when the core device and the input/output device in the conventional integrated circuit are all ring-gate transistors, the compatibility between the core device and the input/output device is poor, and the integration of the core device and the input/output device is difficult to realize by adopting the conventional manufacturing method.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which are used for solving the problem of poor compatibility when the device structures of a core device and an input/output device are all ring gate transistors, and reducing the integration difficulty of the core device and the input/output device.
In order to achieve the above object, the present invention provides a semiconductor device comprising:
a substrate having a first element region and a second element region.
And a first gate-all-around transistor formed on the first element region. The first gate-all-around transistor has at least one layer of first nanowires or sheets. And the periphery of at least one layer of the first nanowire or sheet is sequentially surrounded by a first gate dielectric layer and a second gate dielectric layer.
And a second gate-all-around transistor formed on the second element region. The second ring-gate transistor has at least one layer of second nanowires or sheets. And a third gate dielectric layer is surrounded on the periphery of at least one layer of second nanowire or chip. The total thickness of the first gate dielectric layer and the second gate dielectric layer is larger than that of the third gate dielectric layer. The thickness of the first nanowire or patch is less than the thickness of the second nanowire or patch. The first gate-all-around transistor has a number of first nanowires or slices equal to a number of second nanowires or slices the second gate-all-around transistor has.
Compared with the prior art, in the semiconductor device provided by the invention, the first gate-all-around transistor has the number of the first nanowires or the number of the second sheets, which are equal to that of the first gate-all-around transistor. And the thickness of the first nanowire or sheet is smaller than that of the second nanowire or sheet, so that the distance between the first nanowire or sheet and the substrate is larger than that between the second nanowire or sheet and the substrate. Meanwhile, under the condition that the first gate-all-around transistor has at least two layers of first nanowires or sheets and the second gate-all-around transistor has at least two layers of second nanowires or sheets, the thickness of the first nanowires or sheets is smaller than that of the second nanowires or sheets, so that the distance between the adjacent first nanowires or sheets is larger than that between the adjacent second nanowires or sheets. Based on the above, even if the total thickness of the first gate dielectric layer and the second gate dielectric layer surrounding the periphery of the at least one first nanowire or chip is larger than the thickness of the third gate dielectric layer surrounding the periphery of the at least one second nanowire or chip, the problem that the gate electrode of the subsequent first gate-all transistor cannot be filled or can only be partially filled due to the fact that the total thickness of the first gate dielectric layer and the second gate dielectric layer is larger, the distance between the first nanowire or chip and the substrate and the distance between the adjacent first nanowire or chips are too small can not occur. Therefore, when the semiconductor device provided by the invention is applied to an integrated circuit, and the first gate-all-around transistor is an input/output device in the integrated circuit and the second gate-all-around transistor is a core device, the thickness of the first nanowire or slice is smaller than that of the second nanowire or slice, so that the problem that the compatibility of the input/output device adopting the gate-all-around transistor structure and the core device is poor is solved, and the integration difficulty of the input/output device and the core device is reduced.
The present invention also provides a method of manufacturing a semiconductor device, the method of manufacturing the semiconductor device including:
a substrate is provided. The substrate has a first element region and a second element region.
A first gate all around transistor is formed on the first element region, and a second gate all around transistor is formed on the second element region. The first gate-all-around transistor has at least one layer of first nanowires or sheets. And a first gate dielectric layer and a second gate dielectric layer are sequentially surrounded on the periphery of at least one layer of the first nanowire or the first nanowire sheet. The second ring-gate transistor has at least one layer of second nanowires or sheets. And a third gate dielectric layer is surrounded on the periphery of at least one layer of second nanowire or chip. The total thickness of the first gate dielectric layer and the second gate dielectric layer is larger than that of the third gate dielectric layer. The thickness of the first nanowire or patch is less than the thickness of the second nanowire or patch. The first gate-all-around transistor has the number of layers of the first nanowires or the number of layers of the second gate-all-around transistor.
Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention has the same beneficial effects as the semiconductor device provided by the invention, and the details are not repeated here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural diagram of a core device of a gate-all-around transistor and an input/output device integrated in a prior art;
FIG. 2 is a schematic structural diagram illustrating a substrate and a film layer formed thereon for fabricating at least one laminated material layer according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a first fin structure and a second fin structure after forming the first fin structure and the second fin structure according to an embodiment of the invention;
FIG. 4 is a schematic structural diagram after shallow trench isolation is formed in the embodiment of the present invention;
FIG. 5 is a cross-sectional view of the structure of FIG. 4 taken along line B-B';
FIG. 6 is a cross-sectional view along the direction B-B' of the structure after forming the sacrificial gate and the sidewall spacer in the embodiment of the present invention;
FIG. 7 is a cross-sectional view of the structure taken along the direction B-B' after source and drain regions are formed in an embodiment of the present invention;
FIG. 8 is a schematic structural diagram illustrating a dielectric layer formed according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view taken along line B-B' of the structure after removing portions of the sacrificial gate over the corresponding first device region in accordance with an embodiment of the present invention;
FIG. 10 is a cross-sectional view taken along the direction B-B' of a structure after forming nanowires or chips in an embodiment of the invention;
FIG. 11 is a cross-sectional view of the structure taken along line B-B' after formation of a sacrificial oxide layer in accordance with an embodiment of the present invention;
FIG. 12 is a cross-sectional view taken along line B-B' of the structure after removal of the sacrificial oxide layer in an embodiment of the present invention;
FIG. 13 is a cross-sectional view taken along line B-B' of the structure after formation of a first gate dielectric layer in an embodiment of the present invention;
FIG. 14 is a cross-sectional view of a structure after forming a capping layer in accordance with an embodiment of the present invention, taken along line B-B';
FIG. 15 is a cross-sectional view taken along line B-B' of the structure after removal of the sacrificial layer and formation of a second nanowire or patch in an embodiment of the invention;
FIG. 16 is a cross-sectional view taken along line B-B' of the first structure after forming a third gate dielectric layer in accordance with an embodiment of the present invention;
FIG. 17 is a cross-sectional view of the first structure taken along line B-B' after forming a gate electrode for a second pass gate transistor in an embodiment of the present invention;
FIG. 18 is a cross-sectional view taken along line B-B' of the first construction after removal of the cap layer in an embodiment of the present invention;
fig. 19 is a cross-sectional view along direction B-B' of a gate structure formed in a first gate-all-around transistor and a second gate dielectric layer on the basis of the structure shown in fig. 18;
FIG. 20 is a cross-sectional view taken along line B-B' of the second structure after removal of the capping layer and formation of the second and third gate dielectric layers in an embodiment of the present invention;
FIG. 21 is a cross-sectional view taken along line B-B' of the first structure after forming the gate electrode of the first gate-all-around transistor and the gate electrode of the second gate-all-around transistor in accordance with an embodiment of the present invention;
fig. 22 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Reference numerals are as follows: 11 is a substrate, 111 is a first element region, 112 is a second element region, 12 is a stacked material layer, 121 is a sacrificial material layer, 1211 is a sacrificial layer, 122 is a channel material layer, 1221 is a channel layer, 123 is a stack, 13 is a first fin-shaped structure, 131 is a first fin portion, 14 is a second fin-shaped structure, 141 is a second fin portion, 15 is a transition region, 16 is a source region forming region, 17 is a drain region forming region, 18 is a shallow trench isolation, 19 is a sacrificial gate, 20 is a sidewall, 21 is a source region, 22 is a drain region, 23 is a dielectric layer, 24 is a nanowire or a sheet, 25 is a sacrificial oxide layer, 26 is a first nanowire or sheet, 27 is a first gate dielectric layer, 28 is a capping layer, 29 is a second nanowire or sheet, 30 is a second gate dielectric layer, 31 is a third gate layer, 32 is a gate, 33 is a channel, 34 is a dielectric layer, 35 is a metal gate, 36 is an input/output device, and 37 is a core device.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
An integrated circuit has input/output (IO) devices and Core (Core) devices. The input/output device is mainly used for realizing input and output functions between a chip and a peripheral circuit in an integrated circuit. Because the input/output device needs to bear higher working voltage (usually 1.8V, 2.5V, 3.3V or 5V, etc.), the input/output device has a thicker gate dielectric layer. The core device is a device used in the chip, and is mainly used for realizing logic operation in the chip. Because the number of core devices in the chip is large, the core devices usually use a lower operating voltage (usually 1.0V or 1.2V, etc.) to achieve the purpose of saving power consumption and increasing the operation speed. Correspondingly, the thickness of the gate dielectric layer of the core device is smaller.
In addition, the gate-all-around transistor has the advantages of higher gate control capability and the like compared with a planar transistor and a fin field effect transistor, so that the working performance of the integrated circuit can be improved when the core device is the gate-all-around transistor. In the process of manufacturing the Core device and the input/output device of the gate all around transistor on the same substrate, as shown in fig. 1, after forming a gate dielectric layer 34 (the gate dielectric layer 34 has a smaller thickness) around the periphery of the channel 33 of the Core device 37 on the Core device region of the substrate 11 and a gate dielectric layer 34 (the gate dielectric layer 34 has a larger thickness) around the periphery of the channel 33 of the input/output device 36 on the IO device region, because the distance between adjacent nanowires or sheets only meets the structural requirement of the Core device 37, compared with the input/output device 36, after forming the thicker gate dielectric layer 34, the gate dielectric layer 34 fills the gap between the smaller nanowires or sheets or only leaves a smaller gate forming space between the nanowires or sheets, and then cannot form an input meeting the working requirement in the gap or the smaller gate space The metal gate 35 of the output device 36 causes a phenomenon of "pinch-off" between adjacent nanowires or chips in the IO device region, thereby affecting the electrical performance of the input/output device 36 formed in the IO device region, i.e., it is difficult to integrate the core device 37 and the input/output device 36, which are all gate-all-around transistors, and reduce the working performance of the input/output device 36.
In order to solve the above technical problem, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by the embodiment of the invention, the thickness of the first nanowire or chip is smaller than that of the second nanowire or chip, so that the distance between the first nanowire or chip and the substrate can be larger than that between the second nanowire or chip and the substrate. Therefore, even if the total thickness of the first gate dielectric layer and the second gate dielectric layer surrounding the periphery of at least one first nanowire or chip is larger than the thickness of the third gate dielectric layer surrounding the periphery of at least one second nanowire or chip, the problem that the gate electrode of the subsequent first gate-all transistor cannot be filled or can only be partially filled due to the fact that the distance between the first nanowire or chip and the substrate and the distance between the adjacent first nanowire or chips are too small because the total thickness of the first gate dielectric layer and the second gate dielectric layer is larger does not occur.
As shown in fig. 19 and 21, an embodiment of the present invention provides a semiconductor device. The semiconductor device includes: the transistor comprises a substrate 11, a first gate-all-around transistor and a second gate-all-around transistor.
As shown in fig. 19 and 21, the substrate 11 has a first element region 111 and a second element region 112. The first gate all around transistor is formed on the first element region 111. The first gate-all-around transistor has at least one layer of first nanowires or patches 26. The periphery of at least one layer of the first nanowire or chip 26 is sequentially surrounded by a first gate dielectric layer 27 and a second gate dielectric layer 30. A second ring-gate transistor is formed on the second element region 112. The second ring-gate transistor has at least one layer of second nanowires or patches 29. The outer periphery of the at least one second nanowire or chip 29 is surrounded by a third gate dielectric layer 31. The total thickness of the first gate dielectric layer 27 and the second gate dielectric layer 30 is greater than the thickness of the third gate dielectric layer 31. The thickness of the first nanowire or patch 26 is smaller than the thickness of the second nanowire or patch 29. The first gate-all-around transistor has a number of layers of first nanowires or patches 26 equal to the number of layers of second nanowires or patches 29 the second gate-all-around transistor has.
Specifically, the substrate may be any semiconductor substrate such as a silicon substrate, a silicon-on-insulator substrate, a silicon-germanium substrate, or a germanium substrate. As shown in fig. 19 and 21, the substrate 11 has the first element region 111 which is a region corresponding to the formation of the first gate-all-around transistor, and thus the position and the number of the first element region 111 on the substrate 11 can be set according to the formation position and the number of the first gate-all-around transistor on the substrate 11, respectively. The substrate 11 has the second element region 112 corresponding to the formation of the second pass gate transistor, so that the position and the number of the second element region 112 on the substrate 11 can be set according to the formation position and the number of the second pass gate transistor on the substrate 11.
For example: in a case where the semiconductor device provided in the embodiment of the present invention is applied to an integrated circuit, and a device structure of an input/output device in the integrated circuit is the first gate all around transistor, and a device structure of a core device is the second gate all around transistor, the first device region is located at a periphery of the second device region.
In some cases, shallow trench isolations for defining active regions are also formed on the substrate. The shallow trench isolation may contain SiN or Si3N4、SiO2Or an insulating material such as SiCO.
For the first gate-all-around transistor and the second gate-all-around transistor, the materials contained in the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer can be set according to actual requirements. Illustratively, the first gate dielectric layer may be a gate oxide layer made of silicon dioxide or the like. The second gate dielectric layer and the third gate dielectric layer may contain HfO2、ZrO2、TiO2Or Al2O3And materials with higher dielectric constants. The second gate dielectric layer and the third gate dielectric layer may be made of the same material or different materials. As shown in fig. 20, in the case where the second gate dielectric layer 30 and the third gate dielectric layer 31 are simultaneously formed in the same operation step, the second gate dielectric layer 30 and the third gate dielectric layer 31 contain the same material. As shown in fig. 16 to 19, when the second gate dielectric layer 30 and the third gate dielectric layer 31 are separately formed in different operation steps, the materials contained in the second gate dielectric layer 30 and the third gate dielectric layer 31 may be the same or different.
It should be understood that the first gate dielectric layer is a part of the gate dielectric layer which constitutes the first gate-all-around transistor, so the thickness of the first gate dielectric layer can be set according to the requirement of the operating voltage of the first gate-all-around transistor in the practical application scenario. For example: in the case where the first gate all around transistor is an input/output device, when the operating voltage of the input/output device is 1.5V or 1.8V, the thickness of the first gate dielectric layer may be 3 nm. And when the operating voltage of the input/output device is 2.5V or 2.8V, the thickness of the first gate dielectric layer can be 5 nm. The thicknesses of the second gate dielectric layer and the third gate dielectric layer can be set according to actual requirements. As shown in fig. 20, in the case that the second gate dielectric layer 30 and the third gate dielectric layer 31 are formed simultaneously in the same operation step, the second gate dielectric layer 30 and the third gate dielectric layer 31 have the same material and thickness. As shown in fig. 16 to fig. 19, when the second gate dielectric layer 30 and the third gate dielectric layer 31 are separately formed in different operation steps, the thicknesses of the second gate dielectric layer 30 and the third gate dielectric layer 31 may be the same or different.
As for the first nanowire or chip and the second nanowire or chip, the materials contained in the two can be semiconductor materials such as silicon, silicon germanium and the like. The number of layers of the first nanowire or chip and the second nanowire or chip, and the thickness of the second nanowire or chip can be set according to actual requirements. In addition, the thickness of the first nanowire or chip may be determined according to a difference between a total thickness of the first gate dielectric layer and the second gate dielectric layer and a thickness of the third gate dielectric layer, a size of the gate electrode of the first gate-all-around transistor, and actual requirements, and is not particularly limited herein. Illustratively, as shown in fig. 19 and 21, the total thickness of the structure formed by the first nanowire or chip 26 and the first gate dielectric layer 27 may be equal to the thickness of the second nanowire or chip 29. Or, in the case that the total thickness of the second gate dielectric layer and the gate electrode of the first gate-all-around transistor is greater than the total thickness of the third gate dielectric layer and the gate electrode of the second gate-all-around transistor, the total thickness of the structure formed by the first nanowire or the first sheet and the first gate dielectric layer may be less than the thickness of the second nanowire or the first sheet. Or, in the case that the total thickness of the second gate dielectric layer and the gate electrode of the first gate-all-around transistor is smaller than the total thickness of the third gate dielectric layer and the gate electrode of the second gate-all-around transistor, the total thickness of the structure formed by the first nanowire or the first nanowire sheet and the first gate dielectric layer may also be larger than the thickness of the second nanowire or the second nanowire sheet.
In one example, as shown in fig. 19 and 21, the width of the first nanowire or chip 26 may be smaller than the width of the second nanowire or chip 29.
In practical application, the first nanowire or chip and the first gate dielectric layer surrounding the periphery of the first nanowire or chip can be obtained by performing selective oxidation treatment on the nanowire or chip. In the selective oxidation process, not only the thickness of the nanowire or the sheet is reduced, but also the width of the nanowire or the sheet is reduced, so that the width of the first nanowire or the sheet is smaller than that of the second nanowire or the sheet.
Specifically, the width difference between the first nanowire or chip and the second nanowire or chip can be determined according to the thickness difference between the two nanowires or chips, and is not limited herein. Illustratively, as shown in fig. 19 and 21, the total width of the structure formed by the first nanowire or chip 26 and the first gate dielectric layer 27 may be equal to the width of the second nanowire or chip 29. Or, in the case that the total thickness of the second gate dielectric layer and the gate electrode of the first gate-all-around transistor is greater than the total thickness of the third gate dielectric layer and the gate electrode of the second gate-all-around transistor, the total width of the structure formed by the first nanowire or the first sheet and the first gate dielectric layer may be smaller than the width of the second nanowire or the first sheet. Or, in the case that the total thickness of the second gate dielectric layer and the gate electrode of the first gate-all-around transistor is smaller than the total thickness of the third gate dielectric layer and the gate electrode of the second gate-all-around transistor, the total width of the structure formed by the first nanowire or the first gate dielectric layer and the first nanowire or the second nanowire or the first gate dielectric layer may be larger than the width of the second nanowire or the first gate dielectric layer.
In practical applications, as shown in fig. 7, 19 and 21, the first gate-all-around transistor and the second gate-all-around transistor each further have a source region 21, a drain region 22 and a gate electrode 32. Wherein the first nanowire or patch 26 is located between the source region 21 and the drain region 22 of the first gate-all-around transistor and is in contact with the source region 21 and the drain region 22, respectively. A second nanowire or patch 29 is located between the source region 21 and the drain region 22 of the second ring gate transistor and is in contact with the source region 21 and the drain region 22, respectively. The first gate-all-around transistor has a gate electrode 32 formed on the second gate dielectric layer 30. The second gate-all-around transistor has a gate electrode 32 formed on the third gate dielectric layer 31.
The material contained in the source region and the drain region may be a semiconductor material such as silicon, silicon germanium, or the like. The gate electrode may be made of a conductive material such as TiN, TaN, or TiSiN. Specifically, the gate electrode of the first gate-all-around transistor and the gate electrode of the second gate-all-around transistor may be made of the same or different materials.
In some cases, as shown in fig. 8, 19 and 21, the first gate-all-around transistor and the second gate-all-around transistor may further have a sidewall spacer 20 and a dielectric layer 23. Wherein the dielectric layer 23 covers the first element region 111 and the second element region 112. And, the top of the portion of the dielectric layer 23 covering the first element region 111 is flush with the top of the gate electrode 32 of the first gate-all-around transistor. The top of the portion of the dielectric layer 23 overlying the second device region 112 is flush with the top of the gate 32 provided by the second pass gate transistor. It is to be understood that, in the process of manufacturing the semiconductor device provided by the embodiment of the present invention, as shown in fig. 8 to 15, the presence of the dielectric layer 23 may protect the source region 21 and the drain region 22 from the etching, cleaning, and the like operations when the sacrificial gate 19 and the sacrificial layer 1211 are etched. Specifically, the material contained in the dielectric layer 23 may be SiO2Or an insulating material such as SiN.
For the above sidewall spacer, the sidewall spacer of the first gate-all-around transistor may be formed between the dielectric layer and the gate electrodes of the first gate dielectric layer, the second gate dielectric layer and the first gate-all-around transistor. The second gate-around transistor has a sidewall formed between the dielectric layer and the gate electrodes of the third gate dielectric layer and the second gate-around transistor. The existence of the side walls is convenient for forming the gate dielectric layer and the grid electrode of the first gate-all-around transistor and the second gate-all-around transistor and isolating the gate dielectric layer and the grid electrode from a subsequently formed conductive structure. The side wall is made of insulating material. Specifically, the materials contained in the side wall and the thickness of the side wall may be designed according to an actual application scenario, which is not specifically limited herein.
In one example, the first gate all around transistor may be an input/output device. The second pass gate transistor may be a core device. Of course, the first gate-all-around transistor can also be other types of devices with larger operating voltages. The second pass gate transistor may also be another type of operating device having a smaller operating voltage.
As can be seen from the above, as shown in fig. 19 and 21, in the semiconductor device provided in the embodiment of the present invention, even if the total thickness of the first gate dielectric layer 27 and the second gate dielectric layer 30 surrounding the outer periphery of the at least one first nanowire or chip 26 is greater than the thickness of the third gate dielectric layer 31 surrounding the outer periphery of the at least one second nanowire or chip 29, the problem that the gate 32 of the subsequent first gate-all transistor cannot be filled or can be only partially filled due to the large total thickness of the first gate dielectric layer 27 and the second gate dielectric layer 30, which causes the small distance between the first nanowire or chip 26 and the substrate 11 and the small distance between the adjacent first nanowires or chips 26 does not occur. Therefore, when the semiconductor device provided by the embodiment of the present invention is applied to an integrated circuit, and the first gate-all-around transistor is an input/output device in the integrated circuit, and the second gate-all-around transistor is a core device, the thickness of the first nanowire or slice 26 is smaller than that of the second nanowire or slice 29, which is beneficial to solving the problem of poor compatibility when both the input/output device and the core device adopt a gate-all-around transistor structure, and reducing the integration difficulty of the input/output device and the core device.
As shown in fig. 22, an embodiment of the present invention provides a method of manufacturing a semiconductor device. The manufacturing process will be described below with reference to the perspective and cross-sectional views of the operation shown in fig. 2 to 21. Specifically, the manufacturing method of the semiconductor device comprises the following steps:
first, a substrate is provided. The substrate has a first element region and a second element region. Specifically, reference may be made to the foregoing for information such as the material and structure of the substrate, and the positions of the first element region and the second element region, which are not described herein again.
As shown in fig. 2 to 21, a first gate-all-around transistor on the first element region 111 is formed, and a second gate-all-around transistor on the second element region 112 is formed. The first gate-all-around transistor has at least one layer of first nanowires or patches 26. The periphery of at least one layer of the first nanowire or chip 26 is sequentially surrounded by a first gate dielectric layer 27 and a second gate dielectric layer 30. The second ring-gate transistor has at least one layer of second nanowires or patches 29. The outer periphery of the at least one second nanowire or chip 29 is surrounded by a third gate dielectric layer 31. The total thickness of the first gate dielectric layer 27 and the second gate dielectric layer 30 is greater than the thickness of the third gate dielectric layer 31. The thickness of the first nanowire or patch 26 is smaller than the thickness of the second nanowire or patch 29. The first gate-all-around transistor has a number of layers of first nanowires or patches 26 equal to the number of layers of second nanowires or patches 29 the second gate-all-around transistor has.
Specifically, the information of each structure, the specification of each structure, the contained material, and the like included in the first gate all around transistor and the second gate all around transistor may refer to the foregoing, and are not described herein again.
In practical applications, the first gate-all-around transistor and the second gate-all-around transistor also have a source region and a drain region, as described above. Based on this, after providing a substrate, in the process of forming the first gate-all-around transistor and the second gate-all-around transistor, the following steps may be performed:
as shown in fig. 2 to 5, a first fin 131 is formed on the first device region 111, and a second fin 141 is formed on the second device region 112. Each of the first fin 131 and the second fin 141 has a source region formation region 16, a drain region formation region 17, and a transition region 15 between the source region formation region 16 and the drain region formation region 17. The extending directions of the lengths of the first fin 131 and the second fin 141 may be the same or different.
Specifically, the specific structures of the first fin portion and the second fin portion may be set according to actual requirements. For example, as shown in fig. 4, the first fin 131 and the second fin 141 may each include at least one stacked material layer 12 along a thickness direction of the substrate 11. Each stacked material layer 12 includes a sacrificial material layer 121, and a channel material layer 122 on the sacrificial material layer 121. As shown in fig. 4 to 15, the channel material layer 122 included in the at least one laminated material is a film layer for forming the first nanowire or chip 26 or the second nanowire or chip 29. Based on this, the number of layers of the laminated material layer 12 formed on the substrate 11 may be set with reference to the number of layers of the first nanowire or chip 26 and the second nanowire or chip 29. Example (b)Such as: in case the number of layers of the first nanowire or chip 26 and the second nanowire or chip 29 is two, respectively, the first fin 131 and the second fin 141 each comprise two layers of laminated material 12. In addition, the channel material layer 122 contains the same material as that contained in the first nanowire or chip 26 and the second nanowire or chip 29. For example: the channel material layer 122 may be made of a semiconductor material such as silicon or silicon germanium. The sacrificial material layer 121 and the channel material layer 122 need to have a certain etching selection ratio, so as to prevent the channel material layer 122 from being affected by operations such as etching and cleaning when the sacrificial material layer 121 is subsequently removed from the transition region 15, thereby improving the quality of the first nanowire or chip 26 and the second nanowire or chip 29, and improving the yield of the manufactured semiconductor device. For example: when the channel material layer 122 includes Si, the sacrificial material layer 121 may include Si0.5Ge0.5Or Ge.
In practical applications, as shown in fig. 2, a film layer for manufacturing at least one stacked material layer may be formed on the substrate 11 by using epitaxial growth or the like. As shown in fig. 3, the film layer and the substrate 11 for fabricating the at least one stacked material layer may be etched by photolithography and etching processes to form the first fin structure 13 and the second fin structure 14. The first fin structure 13 is located on the first element region 111. The second fin structure 14 is located on the second element region 112. Wherein, the depth of the substrate 11 is greater than or equal to the thickness of the shallow trench isolation formed later. As shown in fig. 4, an isolation material covering the substrate 11 and the first and second fin structures may be formed by a chemical vapor deposition or a physical vapor deposition, and a planarization process may be performed on the isolation material by a chemical mechanical polishing process, so that tops of the remaining isolation material are flush with tops of the first and second fin structures, respectively, and thus, after the remaining isolation material is etched back to form the shallow trench isolation 18, regions of the shallow trench isolation 18 are in the same plane, thereby preventing the nanowire or chip and the second nanowire or chip that are formed subsequently from being released due to the fact that the shallow trench isolation 18 surrounds the periphery of the sacrificial material layer 121 at the bottom layer, and improving yield of the semiconductor device. After the shallow trench isolation 18 is formed, the exposed portion of the first fin structure outside the shallow trench isolation 18 is a first fin 131. The exposed portion of the second fin structure outside the shallow trench isolation 18 is a second fin 141.
As shown in fig. 6, a sacrificial gate 19 and a sidewall 20 are formed on the periphery of the transition region 15 of the first fin and the transition region 15 of the second fin. The length extension direction of the sacrificial gate 19 is different from the length extension direction of the first fin portion and the second fin portion. The side walls 20 are formed at least on both sides of the sacrificial gate 19 in the width direction. Specifically, the length extending direction of the sacrificial gate 19 may be any direction parallel to the substrate 11 and different from the length extending directions of the first fin and the second fin. Preferably, the length extension direction of the sacrificial gate 19 is orthogonal to the length extension direction of the first fin portion and the second fin portion, respectively. In addition, the above-mentioned side walls 20 may be formed only on both sides of the sacrificial gate 19 in the width direction. Alternatively, the sidewall spacer may surround the sidewall of the sacrificial gate.
In practical applications, a gate material for forming a sacrificial gate may be deposited over the first device region and the second device region by a chemical vapor deposition process. And then, etching the gate material by adopting a dry etching mode, and reserving a part of the gate material covering the peripheries of the transition region of the first fin part and the transition region of the second fin part to obtain the sacrificial gate. The gate material may be amorphous silicon, polysilicon, or other materials that are easily removed. As shown in fig. 6, after the sacrificial gate 19 is formed, the sidewall spacers 20 may be formed at least on the sidewalls of the sacrificial gate 19 in the above manner. The material of the sidewall spacers 20 may be an insulating material such as silicon nitride. The thickness of the side wall 20 can be set according to actual requirements.
As shown in fig. 6 and 7, at least the source region formation region 16 and the drain region formation region 17 of the first fin portion are processed to form a source region 21 and a drain region 22 of the first gate-all-around transistor; and processing at least the source region forming region 16 and the drain region forming region 17 of the second fin portion to form a source region 21 and a drain region 22 of the second ring gate transistor.
In an actual application process, a dry etching process or a wet etching process may be used to remove portions of the first fin portion located in the source region formation region and the drain region formation region, and to remove portions of the second fin portion located in the source region formation region and the drain region formation region. As shown in fig. 7, a source region 21 is epitaxially formed at least in the source region formation region and a drain region 22 is epitaxially formed at least in the drain region formation region by epitaxial growth or the like, so that the source region 21 and the drain region 22 of the first gate-all-around transistor and the second gate-all-around transistor can be obtained at the same time. Or, ion implantation processing may be directly performed on the portion of the first fin portion located in the source region formation region and the drain region formation region, and on the portion of the second fin portion located in the source region formation region and the drain region formation region, so that the source region formation region forms a source region correspondingly, and the drain region formation region forms a drain region correspondingly.
Illustratively, as described above, referring to fig. 8, in the case that the manufactured semiconductor device further includes the dielectric layer 23, after the source region 21 and the drain region of the first gate-all-around transistor are formed and the source region 21 and the drain region of the second gate-all-around transistor are formed, before the subsequent operations are performed, the manufacturing method of the semiconductor device further includes the steps of: a dielectric layer 23 is formed overlying the first element region 111 and the second element region 112. The top of the dielectric layer 23 is flush with the top of the sacrificial gate 19.
In practical applications, a physical vapor deposition or chemical vapor deposition process may be used to form a dielectric material covering the first device region and the second device region, and a chemical mechanical polishing process may be used to planarize the dielectric material to expose the top of the sacrificial gate. Wherein the portion of the dielectric material remaining over the first element region and the second element region forms a dielectric layer. The dielectric layer may be made of an insulating material such as silicon oxide.
It is noted that the above-described structure can be formed in various ways. How to form the above-described structure is not an essential feature of the embodiments of the present invention, and thus, in the present specification, it is only briefly described so that those skilled in the art can easily implement the present invention. It is fully contemplated by one of ordinary skill in the art that the above-described structures may be otherwise made.
In one example, the forming a first gate all around transistor on the first element region and forming a second gate all around transistor on the second element region further includes:
as shown in fig. 9 and 10, at least one layer of nanowires or chips 24 is formed on the first element region 111, and a channel formation portion is formed on the second element region 112. The channel forming part includes at least one stacked layer 123. Each of the stacked layers 123 includes a sacrificial layer 1211, and a channel layer 1221 on the sacrificial layer 1211.
In an actual application process, as shown in fig. 8, after the dielectric layer 23 is formed, a portion of the sacrificial gate 19 corresponding to the first element region 111 and a portion of the sacrificial gate 19 corresponding to the second element region 112 respectively cover peripheries of transition regions of the first fin portion and the second fin portion. On this basis, it is also necessary to expose the transition region of the first fin portion for forming at least one layer of nanowires or chips on the first device region. At least one layer of nanowires or chips is then formed based on the transition region of the first fin. For example, as mentioned above, in the case that the first fin portion and the second fin portion each include the at least one stacked material layer, the forming of the at least one layer of nanowires or flakes on the first device region and the forming of the channel formation portion on the second device region include the following steps:
as shown in fig. 9, a portion of the sacrificial gate 19 corresponding to the first device region 111 is selectively removed, and a portion of the sacrificial gate 19 corresponding to the second device region 112 is remained. The portion of the at least one laminated material layer 12 located in the transition region 15 is a channel formation.
In actual practice, a photoresist mask may be formed over the formed structure using a photolithography process. The exposed region of the photoresist mask is at least the region where the upper part of the first element region corresponding to the sacrificial gate is located. And then, under the action of the mask of the photoresist mask layer, removing the part of the sacrificial layer corresponding to the first element region by adopting the processes of dry etching and the like, so that the transition region of the first fin part is exposed. And the part of the at least one laminated material layer in the transition region is a channel forming part. And the part of the sacrifice gate corresponding to the second element region is protected by the photoresist mask and remains, so that the selective etching of the sacrifice gate is realized. And finally removing the photoresist mask.
As shown in fig. 10, the portion of the sacrificial material layer located in the transition region of the first fin is removed, so that the portion of the channel material layer included in the at least one stacked material layer located in the transition region of the first fin forms at least one layer of nanowires or fins 24. Specifically, a dry etching process or a wet etching process may be used to remove a portion of the sacrificial material layer located in the transition region of the first fin portion, so as to obtain at least one layer of nanowires or fins 24. The etchant and the specific etching conditions used in the dry etching process or the wet etching process may be selected according to the material of the sacrificial material layer and the actual application scenario, and are not specifically limited herein.
As shown in fig. 10 and 13, the at least one layer of nanowires or flakes 24 is selectively oxidized such that the remaining portion of the at least one layer of nanowires or flakes 24 forms at least one layer of first nanowires or flakes 26 and a first gate dielectric layer 27 is formed around the periphery of the at least one layer of first nanowires or flakes 26. The thickness of the first gate dielectric layer 27 can be referred to above, and is not described herein again.
It is understood that the first fin portion and the second fin portion are formed on the substrate at the same time based on the same film layer, so that the first fin portion and the second fin portion have the same structure. Based on this, after at least one layer of nanowires or sheets is formed, the thickness of the at least one layer of nanowires or sheets is equal to the thickness of the channel material layer (which is a layer structure for forming the second nanowires or sheets) of the second fin portion. Therefore, after at least one layer of nanowires or sheets is obtained, the at least one layer of nanowires or sheets is required to be thinned, so that the thickness of a first nanowire or sheet obtained based on the at least one layer of nanowires or sheets is smaller than that of a second nanowire or sheet formed subsequently, and therefore the problem that the filling of the second gate dielectric layer and the gate electrode of the first gate-all-around transistor is difficult due to the fact that the first gate dielectric layer is directly deposited on the periphery of the nanowire or sheet is solved. Specifically, after at least one layer of nanowire or sheet is subjected to selective oxidation treatment, the thickness and the width of the nanowire or sheet can be reduced, a first gate dielectric layer can be formed on the periphery of the obtained first nanowire or sheet, and the manufacturing efficiency of the semiconductor device is improved. The process and the treatment conditions used in the selective oxidation may be set according to actual requirements, and are not specifically limited herein.
Illustratively, at least one layer of nanowires or sheets may be selectively oxidized using an In Situ moisture Generation process (which may be abbreviated as ISSG). The conditions of the selective oxidation treatment may be: at least under the environment of oxygen-containing atmosphere, the treatment temperature is 600 ℃ to 950 ℃. Preferably, the processing temperature is 650 to 750 ℃, and the processing temperature in this range is relatively low, so that the influence of the doping in the nanowire or the chip caused by the selective oxidation processing at the high processing temperature can be prevented, and the yield of the semiconductor device can be improved. The oxygen-containing atmosphere may be an ozone atmosphere, an ozone and oxygen atmosphere, or an oxygen and hydrogen atmosphere.
In an actual application process, in the case where the nanowire or the sheet can be thinned to the thickness of the first nanowire or the sheet only by performing the selective oxidation treatment, after forming at least one layer of the nanowire or the sheet on the first element region and forming the channel formation portion on the second element region, before performing the selective oxidation treatment on at least one layer of the nanowire or the sheet, the method for manufacturing the semiconductor device may further include the steps of: at least one layer of nanowires or sheets is surface treated. The conditions of the surface treatment are as follows: under the hydrogen environment, the treatment temperature is 700-950 ℃. The treatment time is 10 s-2 min. The surface treatment is carried out on at least one layer of nanowire or sheet to improve the interface characteristic of at least one layer of nanowire or sheet, and the working performance of the first gate-all-around transistor is improved. Specifically, the specific treatment conditions of the surface treatment may be selected from other suitable ranges according to actual conditions, and are not particularly limited herein.
In another example, if the obtained nanowire or chip has a small pitch from the substrate and the adjacent nanowire or chip, and it is difficult to reduce the thickness of the nanowire or chip to the thickness of the first nanowire or chip by performing the selective oxidation process only on the nanowire or chip, the method for manufacturing a semiconductor device may further include the steps of, after forming at least one layer of the nanowire or chip on the first element region and forming the channel formation portion on the second element region, before performing the selective oxidation process on at least one layer of the nanowire or chip: as shown in fig. 11, at least one layer of nanowires or flakes 24 is subjected to a sacrificial oxidation process to form a sacrificial oxide layer 25 around the periphery of at least one layer of nanowires or flakes 24. As shown in fig. 12, the sacrificial oxide layer is removed. The above operations are repeated until the thickness of at least one layer of nanowires or sheets 24 is reduced to a preset threshold. The preset threshold value is larger than zero and smaller than or equal to the total thickness of the structure formed by the first nanowire or the first nanowire sheet and the first gate dielectric layer.
In the actual application process, at least one layer of nanowires or chips can be subjected to sacrificial oxidation treatment by adopting processes such as in-situ water vapor generation and the like. The processing conditions of the sacrificial oxidation treatment can be set according to actual requirements. In addition, the thickness and width of the nanowire or the chip are reduced during the sacrificial oxidation treatment, and a sacrificial oxide layer is formed on the periphery of the nanowire or the chip. The sacrificial oxide layer may have a thickness of
Figure BDA0003528943080000171
In addition, the etching process and the etchant used in removing the sacrificial oxide layer may be determined according to the material contained in the sacrificial oxide layer. For example: in the case where the sacrificial Oxide layer contains silicon Oxide, a wet etching process, such as a hydrofluoric acid solution or a Buffered Oxide Etch (abbreviated as BOE), may be used to remove the sacrificial Oxide layer. Another example is: in the case where the sacrificial oxide layer contains silicon oxide, a dry etching process, such as SiCoNi, may be used to remove the sacrificial oxide layer.
In addition, the specific cycle number of the two steps of sacrificial oxidation treatment and sacrificial oxide layer removal may be determined according to the thinned thickness of the nanowire or the chip after each sacrificial oxidation treatment and the size of the preset threshold, which is not specifically limited herein.
In actual practice, after forming the first nanowire or pellet 26 and the first gate dielectric layer 27, the remaining portion of the sacrificial gate 19 is still located on the second element region 112, as shown in fig. 13. Based on this, after the selective oxidation treatment is performed on at least one layer of nanowires or sheets, and before the subsequent operation, the method for manufacturing a semiconductor device further comprises the steps of: and under the mask action of the covering layer, removing the part of the sacrificial gate, which corresponds to the second element region, so as to expose the channel forming part covered by the partial sacrificial gate, thereby facilitating the operation of the channel forming part to form a second nanowire or a second nanowire. As shown in fig. 14, the cover layer 28 covers the first device region 111.
In particular, the material contained in the cover layer can be set according to actual requirements. Illustratively, the capping layer may be a Spin On Carbon (SOC) or Advanced Patterning (APF) layer. Alternatively, the capping layer may include an amorphous silicon capping layer and a hard mask layer on the amorphous silicon capping layer.
Specifically, the process for forming the cover layer may be selected according to the material contained in the cover layer. For example: in the case where the capping layer is a spin-on carbon capping layer, a spin coating process may be employed to form a capping material layer overlying the formed structure. And then, selectively etching the covering material layer by adopting photoetching and etching processes, removing the part of the covering material layer on the second element area, and reserving the part of the covering material layer on the first element area to obtain the covering layer. Another example is: in the case where the capping layer comprises the amorphous silicon capping layer and the hard mask layer, a chemical vapor deposition process or the like may be used to form a layer of amorphous silicon material overlying the formed structure. Then, a hard mask layer is formed on the amorphous silicon material layer by deposition, selective etching and other processes. The hard mask layer overlies the first element region. And finally, under the mask action of the hard mask layer, selectively etching the amorphous silicon material layer to obtain an amorphous silicon covering layer. After the covering layer is obtained, under the mask effect of the covering layer, a portion of the sacrificial gate corresponding to the second element region may be removed by a dry etching process or the like.
As shown in fig. 15, the sacrificial layer is removed such that at least one layer of the stack comprises a channel layer forming at least one second nanowire or patch 29. Specifically, the process and the etchant used for removing the sacrificial layer may be selected according to actual requirements, and are not specifically limited herein.
As shown in fig. 16 to 20, a second gate dielectric layer 30 is formed on the first gate dielectric layer 27, and a third gate dielectric layer 31 is formed around the outer circumference of the at least one second nanowire or chip 29. The materials and thicknesses of the second gate dielectric layer 30 and the third gate dielectric layer 31 may refer to the foregoing, and are not described herein again.
It is noted that, as described above, a capping layer is formed over the first device region before removing the portion of the sacrificial gate over the second device region. In an actual application process, after the second nanowire or chip is formed, the forming sequence of the second gate dielectric layer and the third gate dielectric layer is different according to the removing sequence of the covering layer. There are at least two cases:
in one example, after removing the sacrificial layer, and before forming a second gate dielectric layer on the first gate dielectric layer and forming a third gate dielectric layer around the periphery of at least one second nanowire or chip, the method for manufacturing a semiconductor device further comprises the steps of: and removing the covering layer.
Specifically, the process and the etchant used for removing the capping layer may be determined according to the material of the capping layer. For example: in the case where the capping layer is a spin-on carbon capping layer or an advanced patterning layer, a dry etching process, such as removal of the capping layer by an oxygen plasma, may be employed. Another example is: in the case that the capping layer includes the amorphous silicon capping layer and the hard mask layer, and the hard mask layer contains silicon nitride, the capping layer may be removed by a wet etching process. Specifically, H can be used3PO4Removing the hard mask layer made of silicon nitride material by the solution, and then passing through NH4And removing the amorphous silicon covering layer by using the OH solution.
In the above case, as shown in fig. 20, the second gate dielectric layer 30 on the first gate dielectric layer 27 and the third gate dielectric layer 31 around the outer circumference of the at least one second nanowire or chip 29 may be simultaneously formed in one operation by a chemical vapor deposition or the like. As shown in fig. 21, the gate electrodes 32 of the first and second gate-all-around transistors may then be formed simultaneously by chemical vapor deposition and chemical mechanical polishing. At this time, the second gate dielectric layer 30 and the third gate dielectric layer 31 both contain the same material and thickness. The first and second pass-gate transistors have gates 32 of the same material.
In another example, as shown in fig. 16 to 18, after forming a third gate dielectric layer 31 around the periphery of at least one second nanowire or chip 29 and before forming a second gate dielectric layer 30 on the first gate dielectric layer 27, the method for manufacturing the semiconductor device further comprises the following steps: a gate electrode 32 of the second gate-all-around transistor is formed on the third gate dielectric layer 31. The capping layer 28 is then removed.
Specifically, in this case, as shown in fig. 16 and 17, the third gate dielectric layer 31 surrounding the outer periphery of the at least one second nanowire or chip 29 may be formed first using the above-described process. And a gate electrode 32 of the second gate-all-around transistor is formed on the third gate dielectric layer 31. Since the capping layer 28 is formed on the first device region 111, the third gate dielectric layer 31 and the gate electrode 32 of the second pass gate transistor are not formed in the gate formation region located on the first device region 111. As shown in fig. 18 and 19, the capping layer 28 may be removed by the above-mentioned process, the gate forming region on the first device region 111 is released, and the second gate dielectric layer 30 and the gate 32 of the first gate-around transistor are formed in the gate forming region. As can be seen from the above, the second gate dielectric layer 30 and the third gate dielectric layer 31 are formed in different operation steps, and therefore, the materials and the thicknesses of the two layers may be the same or different. Similarly, the gate 32 of the first gate-all-around transistor and the gate 32 of the second gate-all-around transistor may have the same or different materials.
Specifically, the gate of the first gate-all-around transistor and the gate of the second gate-all-around transistor may contain materials, which are not described in detail herein.
Compared with the prior art, the manufacturing method of the semiconductor device provided by the embodiment of the invention has the same beneficial effects as the semiconductor device provided by the embodiment of the invention, and the details are not repeated herein.
In the above description, details of the techniques such as patterning and etching of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (13)

1. A semiconductor device, comprising:
a substrate having a first element region and a second element region;
a first gate-all-around transistor formed on the first element region; the first gate-all-around transistor is provided with at least one layer of first nanowires or sheets; a first gate dielectric layer and a second gate dielectric layer are sequentially arranged on the periphery of the at least one layer of the first nanowire or the at least one layer of the first nanowire;
and a second gate-all-around transistor formed on the second element region; the second ring-gate transistor is provided with at least one layer of second nanowires or sheets; a third gate dielectric layer is surrounded on the periphery of the at least one layer of second nanowire or sheet; the total thickness of the first gate dielectric layer and the second gate dielectric layer is larger than that of the third gate dielectric layer; the thickness of the first nanowire or sheet is less than the thickness of the second nanowire or sheet; the first gate-all-around transistor has a number of first nanowires or sheets equal to a number of second nanowires or sheets of the second gate-all-around transistor.
2. The semiconductor device according to claim 1, wherein the first gate-all-around transistor is an input/output device; the second ring gate transistor is a core device.
3. The semiconductor device of claim 1, wherein a width of the first nanowire or patch is less than a width of the second nanowire or patch; and/or the presence of a gas in the gas,
the total thickness of the structure formed by the first nanowire or chip and the first gate dielectric layer is equal to the thickness of the second nanowire or chip; and/or the presence of a gas in the gas,
the total width of the structure formed by the first nanowire or sheet and the first gate dielectric layer is equal to the width of the second nanowire or sheet.
4. The semiconductor device according to claim 1, wherein the second gate dielectric layer and the third gate dielectric layer comprise the same material; the thicknesses of the second gate dielectric layer and the third gate dielectric layer are equal; or the like, or, alternatively,
the second gate dielectric layer and the third gate dielectric layer are made of different materials.
5. A method of manufacturing a semiconductor device, comprising:
providing a substrate; the substrate has a first element region and a second element region;
forming a first gate-all-around transistor on the first element region and forming a second gate-all-around transistor on the second element region; the first gate-all-around transistor is provided with at least one layer of first nanowires or sheets; a first gate dielectric layer and a second gate dielectric layer are sequentially arranged on the periphery of the at least one layer of the first nanowire or the at least one layer of the first nanowire; the second ring-gate transistor is provided with at least one layer of second nanowires or sheets; a third gate dielectric layer is surrounded on the periphery of the at least one layer of second nanowire or sheet; the total thickness of the first gate dielectric layer and the second gate dielectric layer is larger than that of the third gate dielectric layer; the thickness of the first nanowire or sheet is less than the thickness of the second nanowire or sheet; the first gate-all-around transistor has a number of first nanowires or sheets equal to a number of second nanowires or sheets of the second gate-all-around transistor.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the forming a first gate-all-around transistor located on the first element region and forming a second gate-all-around transistor located on the second element region includes:
forming at least one layer of nanowires or sheets on the first element region, and forming a channel formation on the second element region; the channel forming part comprises at least one laminated layer; each of the laminated layers includes a sacrificial layer and a channel layer on the sacrificial layer;
subjecting the at least one layer of nanowires or sheets to a selective oxidation treatment such that remaining portions of the at least one layer of nanowires or sheets form the at least one layer of first nanowires or sheets and form the first gate dielectric layer around the periphery of the at least one layer of first nanowires or sheets;
removing the sacrificial layer so that the channel layer comprised by at least one layer stack forms the at least one second nanowire or patch;
and forming the second gate dielectric layer on the first gate dielectric layer and forming the third gate dielectric layer around the periphery of the at least one layer of second nanowire or sheet.
7. The method for manufacturing a semiconductor device according to claim 6, wherein the selective oxidation treatment is performed on the at least one layer of nanowires or sheets by an in-situ water vapor generation process; the conditions of the selective oxidation treatment are as follows: at least under the environment of oxygen-containing atmosphere, the treatment temperature is 600 ℃ to 950 ℃.
8. The method of manufacturing a semiconductor device according to claim 6, wherein after the forming of the at least one layer of nanowires or flakes on the first element region and the forming of the channel formation portion on the second element region, before the performing of the selective oxidation treatment on the at least one layer of nanowires or flakes, the method further comprises: performing surface treatment on the at least one layer of nanowires or sheets; the conditions of the surface treatment are as follows: under the hydrogen environment, the treatment temperature is 700-950 ℃; the treatment time is 10 s-2 min; or the like, or, alternatively,
after the forming of the at least one layer of nanowires or flakes on the first element region and the forming of the channel formation portion on the second element region, and before the performing of the selective oxidation treatment on the at least one layer of nanowires or flakes, the method for manufacturing a semiconductor device further includes:
performing sacrificial oxidation treatment on the at least one layer of nanowires or sheets to form a sacrificial oxide layer surrounding the periphery of the at least one layer of nanowires or sheets;
removing the sacrificial oxide layer;
the operation is circulated until the thickness of the at least one layer of the nanowire or the sheet is reduced to a preset threshold value; the preset threshold value is larger than zero and smaller than or equal to the total thickness of a structure formed by the first nanowire or sheet and the first gate dielectric layer.
9. The method for manufacturing a semiconductor device according to claim 6, wherein after the providing of a substrate, before the forming of the at least one layer of nanowires or sheets on the first element region and the forming of the channel formation portion on the second element region, the method further comprises:
forming a first fin part on the first element region and forming a second fin part on the second element region; the first fin portion and the second fin portion are provided with a source region forming region, a drain region forming region and a transition region located between the source region forming region and the drain region forming region;
forming a sacrificial gate and a side wall on the peripheries of a transition region of the first fin part and a transition region of the second fin part; the length extension direction of the sacrificial gate is different from the length extension direction of the first fin part and the length extension direction of the second fin part; the side walls are at least formed on two sides of the sacrificial gate along the width direction;
processing at least a source region forming region and a drain region forming region of the first fin portion to form a source region and a drain region of the first gate-all-around transistor; and at least processing a source region forming region and a drain region forming region of the second fin part to form a source region and a drain region of the second ring-gate transistor.
10. The method of manufacturing the semiconductor device according to claim 9, wherein the first fin portion and the second fin portion each include at least one stacked material layer in a thickness direction of the substrate; each laminated material layer comprises a sacrificial material layer and a channel material layer positioned on the sacrificial material layer;
the forming at least one layer of nanowires or sheets on the first element region and forming a channel formation on the second element region includes:
selectively removing the part of the sacrificial gate corresponding to the first element region, and reserving the part of the sacrificial gate corresponding to the second element region; the part of the at least one laminated material layer, which is positioned in the transition region, is the channel forming part;
and removing the part of the sacrificial material layer, which is positioned in the transition region of the first fin part, so that the part of the channel material layer, which is included in the at least one laminated material layer, which is positioned in the transition region of the first fin part forms the at least one layer of nanowire or chip.
11. The method of claim 9, wherein after the selectively oxidizing the at least one layer of nanowires or flakes, the removing the sacrificial layer is performed such that at least one layer of the stack comprises the channel layer before the at least one layer of the second nanowires or flakes is formed, and wherein the method further comprises:
under the mask action of the covering layer, removing the part of the sacrificial gate corresponding to the second element region; the cover layer covers the first element region.
12. The method of claim 11, wherein after removing the sacrificial layer, before forming a second gate dielectric layer on the first gate dielectric layer and forming a third gate dielectric layer around the periphery of the at least one second nanowire or chip, the method further comprises: removing the cover layer; or the like, or, alternatively,
after forming the third gate dielectric layer around the periphery of the at least one second nanowire or sheet, and before forming the second gate dielectric layer on the first gate dielectric layer, the method for manufacturing the semiconductor device further includes: forming a grid electrode of a second ring grid transistor on the third grid dielectric layer; and removing the covering layer.
13. The method for manufacturing a semiconductor device according to claim 11, wherein the capping layer is a spin-on carbon capping layer or an advanced patterning layer; or, the covering layer comprises an amorphous silicon covering layer and a hard mask layer positioned on the amorphous silicon covering layer.
CN202210200010.4A 2022-03-02 2022-03-02 Semiconductor device and manufacturing method thereof Pending CN114613770A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117352459A (en) * 2023-09-21 2024-01-05 北京大学 Preparation method of semiconductor structure, device and equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117352459A (en) * 2023-09-21 2024-01-05 北京大学 Preparation method of semiconductor structure, device and equipment

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