CN112350672A - IF chip with digital compensation function and digital compensation method thereof - Google Patents
IF chip with digital compensation function and digital compensation method thereof Download PDFInfo
- Publication number
- CN112350672A CN112350672A CN202011299972.7A CN202011299972A CN112350672A CN 112350672 A CN112350672 A CN 112350672A CN 202011299972 A CN202011299972 A CN 202011299972A CN 112350672 A CN112350672 A CN 112350672A
- Authority
- CN
- China
- Prior art keywords
- compensation
- current
- frequency
- digital
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention provides an IF chip with a digital compensation function and a digital compensation method thereof. Wherein the IF chip includes: the analog processing module is configured to acquire a measured current input into the IF chip and perform frequency conversion on the measured current to obtain an initial frequency pulse signal; the digital processing module is configured to generate a corresponding compensation control signal according to the initial frequency pulse signal; the compensation current source is configured to adjust the magnitude of compensation current output by the compensation current source according to the compensation control signal, so that the compensation current and the measured current are superposed to obtain superposed current; and the analog processing module is also configured to perform frequency conversion on the superposed current to obtain an output frequency pulse signal. The scheme of the invention improves the compensation precision, does not influence the bandwidth of the originally output frequency signal, has wider application range, improves the reliability and greatly reduces the cost.
Description
Technical Field
The present invention relates to semiconductor chips, and more particularly, to an IF chip having a digital compensation function and a digital compensation method thereof.
Background
Current frequency conversion (IF conversion) is a common analog-to-digital signal conversion (AD conversion) method, and is widely used. Compared with the traditional AD conversion technology, the current frequency conversion technology has the characteristics of simple circuit, small volume, high sensitivity, large output amplitude, good linearity and the like. The current frequency conversion specifically refers to a signal processing technique for converting a current input signal into a corresponding pulse output signal, and the frequency value of the pulse output signal corresponds to the current amplitude of the input signal. The linearity of the current frequency conversion is an important index indicating the performance of the current frequency conversion, and particularly refers to the linear relationship between the input current amplitude and the output frequency value.
A current frequency conversion chip (IF chip) is a chip that realizes an IF conversion function. With the development of integrated circuits, IF chips are designed by using a System On Chip (SOC) to further reduce the cost, reduce the size and improve the stability.
However, in a large scale integrated circuit, due to the deviation of the CMOS (complementary metal oxide semiconductor) process, the linearity of the IF chip is difficult to be improved due to the interference between a large number of analog circuits and digital circuits.
In order to improve the linearity of IF, the prior art generally needs digital algorithm for compensation, and the conventional solution is to use integrated ADC (AD converter, e.g. a chip such as ADUC847 embedded in MCU and memory) for programming to realize the compensation algorithm, but the solution is very costly and technically complex.
Disclosure of Invention
An object of the present invention is to provide an IF chip and a digital compensation method thereof that solve at least any one of the above-mentioned problems.
A further object of the present invention is to realize an IF chip with low cost and high linearity.
It is a further object of the present invention to save memory cells of an IF chip.
Specifically, the present invention provides an IF chip having a digital compensation function, the IF chip including:
the analog processing module is configured to acquire a measured current input into the IF chip and perform frequency conversion on the measured current to obtain an initial frequency pulse signal;
the digital processing module is configured to generate a corresponding compensation control signal according to the initial frequency pulse signal;
the compensation current source is configured to adjust the magnitude of compensation current output by the compensation current source according to the compensation control signal, so that the compensation current and the measured current are superposed to obtain superposed current; and is
And the analog processing module is also configured to perform frequency conversion on the superposed current to obtain an output frequency pulse signal.
Optionally, the analog processing module comprises:
the analog integrator is configured to integrate the measured current and the superposed current respectively to obtain an initial current integral signal and a superposed current integral signal;
the analog controller is configured to perform frequency conversion on the initial current integration signal to obtain an initial frequency pulse signal; and carrying out frequency conversion on the superposed current integral signal to obtain an output frequency pulse signal.
Optionally, the digital processing module comprises:
the digital compensator is connected with the analog controller and is configured to determine a corresponding frequency compensation value according to the initial frequency pulse signal;
and the digital controller is connected with the digital compensator and is configured to generate a corresponding compensation control signal according to the frequency compensation value.
Optionally, the digital processing module further comprises: the on-chip memory is connected with the digital compensator and is configured to store error calibration values of a plurality of set acquisition points; the digital compensator is further configured to perform a linear difference calculation using the error calibration value to obtain a frequency compensation value.
Optionally, the on-chip memory is further configured to store an expected frequency value of a set acquisition point;
and the digital compensator is also configured to determine the frequency calibration value corresponding to each error calibration value by utilizing the linear relation of the frequency calibration value and the zero point, and the frequency calibration value is used as a parameter required by linear difference calculation.
Optionally, the on-chip memory is an electronic fuse memory.
Optionally, the compensation current source comprises:
a first current source for outputting a forward current; the second current source is used for outputting negative current; the first regulating switch is connected between the first current source and the analog processing module;
the second regulating switch is connected between the second current source and the analog processing module; and is
And the digital processing module is also configured to provide a compensation control signal to the first regulating switch or the second regulating switch so as to change the size of the compensation current by adjusting the switching ratio of the first regulating switch or the second regulating switch.
Optionally, the absolute values of the current amplitudes output by the first current source and the second current source are equal; and is
The first regulating switch and the second regulating switch are configured to output compensation currents with equal absolute values at the same switching ratio.
According to another aspect of the present invention, there is also provided a digital compensation method of an IF chip, the digital compensation method of the IF chip including:
acquiring a measured current input into the IF chip, and performing frequency conversion on the measured current to obtain an initial frequency pulse signal;
generating a corresponding compensation control signal according to the initial frequency pulse signal;
adjusting the magnitude of compensation current according to the compensation control signal, wherein the compensation current is used for being superposed with the measured current to obtain superposed current; and is
And carrying out frequency conversion on the superposed current to obtain an output frequency pulse signal.
Optionally, the step of generating a corresponding compensation control signal according to the initial frequency pulse signal includes:
acquiring a prestored multipoint error calibration value and a point expected frequency value;
determining a frequency calibration value corresponding to each error calibration value by utilizing the linear relation of the frequency calibration values and the zero point fitting;
performing linear difference calculation on the initial frequency pulse signal according to the frequency calibration value and the corresponding error calibration value to obtain a frequency compensation value;
and generating a corresponding compensation control signal according to the frequency compensation value.
The IF chip with the digital compensation function and the digital compensation method thereof output the compensation current corresponding to the measured current by adopting the digital compensation method, and eliminate the frequency conversion error by overlapping the compensation current and the measured current. The compensation mode improves the compensation precision, does not influence the bandwidth of the originally output frequency signal, and has wider application range.
Furthermore, the IF chip with the digital compensation function and the digital compensation method thereof determine a frequency compensation value by using a linear difference algorithm and further adjust the magnitude of the compensation current output by the compensation current source. The method only needs to store a multi-point error calibration value and a point expected frequency value in the on-chip memory, the required storage capacity is small, the calculation is simple and reliable, and the requirements can be met by using an electronic fuse memory (eFuse), so that the IF conversion of a single chip is realized, the reliability is improved, and the cost is greatly reduced.
The above and other objects, advantages and features of the present invention will become more apparent to those skilled in the art from the following detailed description of specific embodiments thereof, taken in conjunction with the accompanying drawings.
Drawings
Some specific embodiments of the invention will be described in detail hereinafter, by way of illustration and not limitation, with reference to the accompanying drawings. The same reference numbers in the drawings identify the same or similar elements or components. Those skilled in the art will appreciate that the drawings are not necessarily drawn to scale. In the drawings:
FIG. 1 is a schematic block diagram of an IF chip with digital compensation according to one embodiment of the present invention;
FIG. 2 is a circuit schematic of an IF chip with digital compensation according to one embodiment of the present invention;
FIG. 3 is a schematic diagram of a digital compensation method of an IF chip according to one embodiment of the present invention; and
fig. 4 is a trend line of measured frequency values of current collection points in a digital compensation method of an IF chip according to an embodiment of the present invention.
Detailed Description
Fig. 1 is a schematic block diagram of an IF chip 10 according to an embodiment of the present invention, and fig. 2 is a circuit schematic diagram of the IF chip 10 according to an embodiment of the present invention. The IF chip 10 may generally include: analog processing module 110, digital processing module 120, and compensation current source 130. In addition, as is known by those skilled in the art, the IF chip 10 should further have input/output components such as a current input port and a frequency signal output port, but in order not to obscure the improvement point of the present embodiment, the present embodiment does not describe additional components such as the input/output components.
The analog processing module 110 is configured to obtain a measured current input to the IF chip 10 and frequency-convert the measured current into an initial frequency pulse signal. The analog processing module 110 performs the conversion from the current signal to the frequency signal, and the conversion error is inevitable. In order to guarantee the linearity requirements of the conversion. The IF conversion needs error compensation, the most mode adopted in the prior art is digital algorithm compensation, and the mode has high requirement on computing capacity, so that the implementation cost and complexity are high, the reliability is low, the use of certain application occasions is limited, and the flexibility is poor. In the present embodiment, the error compensation is realized by means of current compensation, which solves the above problems of the prior art.
After the measured current and the compensation current are superimposed, the analog processing module 110 is configured to perform frequency conversion on the superimposed current to obtain an output frequency pulse signal. Because the compensation current compensates the error, the linearity and the precision of the output frequency pulse signal are ensured.
The analog processing module 110 may include: an analog integrator 111 and an analog controller 112. The analog integrator 111 is configured to integrate the measured current and the superimposed current, respectively, to obtain an initial current integrated signal and a superimposed current integrated signal. The analog integrator 111 integrates the current by storing the charge.
The analog controller 112 performs frequency conversion on the initial current integration signal to obtain an initial frequency pulse signal. The analog controller 112 also performs frequency conversion on the superimposed current integration signal to obtain an output frequency pulse signal. The analog controller 112 converts the integration result of the analog integrator 111 into a corresponding pulse signal, and the pulse frequency directly reflects the magnitude of the current.
The digital processing module 120 is configured to generate a corresponding compensation control signal according to the initial frequency pulse signal. The embodiment provides a significant improvement to the compensation process of the digital processing module 120. Digital processing module 120 may include: digital compensator 121, digital controller 122, on-chip memory 123.
The digital compensator 121 is connected to the analog controller 112 and configured to determine a corresponding frequency compensation value according to the initial frequency pulse signal. The digital compensator 121 determines a frequency error corresponding to the current input current by using the initial frequency pulse signal, and eliminates the frequency error by using the frequency compensation value. The digital controller 122 is connected to the digital compensator 121 and configured to generate a corresponding compensation control signal according to the frequency compensation value.
On-chip memory 123 is coupled to digital compensator 121 and is configured to store error calibration values for a plurality of set acquisition points. The digital compensator 121 may perform a linear difference calculation using the error calibration to obtain a frequency compensation value.
In some embodiments, the on-chip memory 123 may also store a desired frequency value for a set acquisition point. The digital compensator 121 determines the frequency calibration value corresponding to each error calibration value by using the linear relationship fit by the frequency calibration value and the zero point, and the frequency calibration value is used as a parameter required by the linear difference calculation. The specific algorithm of the digital compensator 121 is described in detail later on with respect to the description of the digital compensation method of the IF chip 10 of the present embodiment.
The compensation process uses only a small on-chip memory 123, and in this embodiment the on-chip memory 123 may use a non-volatile memory such as an electronic fuse memory (eFuse) or a Flash memory (Flash). In some embodiments, the eFuses may be fully satisfactory. eFuses are used as special memory space inside the chip and are connected to each other via fuse, and the fuse is blown unidirectionally and irrecoverable. Therefore, the value of the eFuse can only be written once, and the reliability is extremely high. The IF chip 10 of the present embodiment uses efuses, and does not use an external memory, thereby achieving a true single-chip IF converter. Thus, the reliability is improved, and the cost is greatly reduced.
And the compensation current source 130 is configured to adjust the magnitude of the compensation current output by itself according to the compensation control signal, so that the compensation current is superposed with the measured current to obtain a superposed current.
The compensation current source 130 may include: a first current source 131, a second current source 134, a first adjusting switch 132, and a second adjusting switch 133. The first current source 131 is used for outputting a forward current; the first adjusting switch 132 is connected between the first current source 131 and the analog processing module 110. The first current source 131 and the first adjusting switch 132 are used to increase the current value, and the magnitude of the increase in the current value can be adjusted by adjusting the switching ratio of the first adjusting switch 132. The second current source 134 is used for outputting negative current; the second adjustment switch 133 is connected between the second current source 134 and the analog processing module 110. The second current source 134 and the second adjusting switch 133 are used to reduce the current value, and the magnitude of the reduction of the current value can be adjusted by adjusting the switching ratio of the second adjusting switch 133. The output currents of the first current source 131 and the second current source 134 only need to satisfy the error compensation, and thus the amplitude can be set very small.
The first current source 131, the first adjusting switch 132, the second current source 134, and the second adjusting switch 133 may be mirror images of each other, and the absolute values of the amplitudes of the currents output by the first current source 131 and the second current source 134 are equal; and the first adjusting switch 132 and the second adjusting switch 133 are configured such that absolute values of the compensating currents output at the same switching ratio are equal. Thereby facilitating the digital processing module 120 to determine the on-off ratio of the compensation control signal.
The digital processing module 120 provides the compensation control signal to the first adjustment switch 132 or the second adjustment switch 133 to change the magnitude of the compensation current by adjusting the switching ratio of the first adjustment switch 132 or the second adjustment switch 133. I.e. the error is a negative error, when the error needs to be compensated by increasing the current, the digital processing module 120 provides a compensation control signal to the first adjustment switch 132, the magnitude of the compensation current depends on the on-off ratio of the compensation control signal, and when the first adjustment switch 132 is fully turned on, the compensation current is equal to the maximum output current of the first current source 131. When the error is a positive error and the error needs to be compensated by reducing the current, the digital processing module 120 provides a compensation control signal to the second adjustment switch 133, the magnitude of the compensation current depends on the on-off ratio of the compensation control signal, and when the second adjustment switch 133 is fully turned on, the compensation current is equal to the maximum output current of the second current source 134.
The first adjustment switch 132 or the second adjustment switch 133 is alternatively turned on, and is not turned on at the same time.
In the IF chip 10 with digital compensation function of the present embodiment, the digital processing module 120 calculates an error value by linear interpolation within a period of time, and then feeds the error back to the compensation current source 130 at the front end of the analog processing module 110, and adjusts the magnitude of the compensation current by adjusting the switching ratio of the adjustment switch, so as to achieve the purpose of compensation, and thus the analog output frequency is continuously stable. The timing switch period has high precision and small error.
The present embodiment also provides a digital compensation method of the IF chip 10, which can be performed by the IF chip 10 having the digital compensation function of the above-described embodiment, wherein a part due to the calculation can be specifically completed by the digital processing module 120. Fig. 3 is a schematic diagram of a digital compensation method of the IF chip 10 according to an embodiment of the present invention, and the digital compensation method of the IF chip 10 may generally include:
step S302, obtaining a measured current input into the IF chip 10, and performing frequency conversion on the measured current to obtain an initial frequency pulse signal;
step S304, generating a corresponding compensation control signal according to the initial frequency pulse signal;
step S306, adjusting the magnitude of compensation current according to the compensation control signal, wherein the compensation current is used for being superposed with the measured current to obtain superposed current;
step S308, the superposed current is subjected to frequency conversion to obtain an output frequency pulse signal.
Step S304 mainly involves a specific calculation process of digital compensation, which may include obtaining a pre-stored multi-point error calibration value and a point expected frequency value; determining a frequency calibration value corresponding to each error calibration value by utilizing the linear relation of the frequency calibration values and the zero point fitting; performing linear difference calculation on the initial frequency pulse signal according to the frequency calibration value and the corresponding error calibration value to obtain a frequency compensation value; and generating a corresponding compensation control signal according to the frequency compensation value.
The above calculation process is described in detail below with reference to examples. For example, for an IF chip 10 requiring an input current from-16 mA to +16mA, an output frequency ranging from negative 256k to positive 256k corresponds. Selecting 0mA, 0.1mA, 0.2mA, 0.3mA, 0.4mA, 0.5mA, 0.6mA, 0.8mA, 1mA, 1.5mA, 2mA and 3mA as current collection points, carrying out frequency conversion on the current collection points under the condition of no digital compensation to obtain 12 actual measurement frequency values, wherein the obtained test results are shown in a table 1:
TABLE 1
The actually measured frequency value in the table is the frequency of the output frequency pulse signal, i.e. the number of pulses per second. Fig. 4 is a trend line of measured frequency values of current collection points in a digital compensation method of the IF chip 10 according to an embodiment of the present invention. Ideally, the measured frequency values of the current collection points should lie on an inclined line, however, due to non-linearity caused by various reasons, the measurement points in fig. 4 do not lie on a straight line.
And performing linear fitting on the actually measured frequency values of the plurality of current acquisition points to obtain a fitting straight line. The measured frequency values are fitted to a fitted straight line, for example by a linear fitting method which may optionally use a least squares method, the final fit in the above example being the equation: y is 16.9 x-0.0933. The goal of the digital compensation is that the actual measurement results after the digital compensation can coincide with the fitted straight line.
The specific fitting process may be: the input measured current is recorded as i (n), the analog processing module 110 performs frequency conversion on the measured current to obtain an initial frequency pulse signal output as f (n), and a theoretical value on a fitting straight line is recorded as fc (n). Then the error at point n is err (n) ═ f (n) -fc (n). After a number of tests, it can be assumed that the error is linear between the nth current sampling point and the (n +1) th current sampling point. That is, when the measured current I (n) is between I (n) and I (n +1), the error err (t) corresponding to the measured current I (n) satisfies:
Err(t)＝(Err(n+1)-Err(n))*(F(t)-F(n))/(F(n+1)-F(n))
where Err (n +1) is the error at the n +1 current sampling point, and Err (n) is the error at the n current sampling point. F (t) is the frequency of the tested current I (n) to obtain the initial frequency pulse signal, F (n +1) is the frequency value of the initial frequency pulse signal of the n +1 current sampling point, and F (n) is the frequency value of the initial frequency pulse signal of the n current sampling point.
Therefore, in this embodiment, the digital processing module 120 may obtain the error of the frequency output signal corresponding to i (n) through the linear difference. The error calibration value err (n) is written in advance as boundary value data of the compensation current subinterval into the on-chip memory 123 such as an eFuse. The digital compensator 121 determines the boundary of the acquisition point according to the magnitude of the measured current signal, and since the magnitude of the measured current signal i (n) corresponds to F (t), that is, the ranges (F (n) and F (n +1)) of the acquisition point can be determined according to the numerical range of F (t), the frequency compensation value err (t) can be calculated by using the above formula, thereby improving the linearity. For example, the error err (n) is obtained in advance from the actually measured data f (n), where n is 0,1,2, 18, and the frequency compensation value can be calculated by the above formula of the error err (t) by determining the range of the acquisition point to which i (n) belongs (i.e., the numerical range in which f (t) is located).
To further save storage capacity, in the present embodiment, the on-chip memory 123 may only store a multi-point error calibration value (err (n), n ═ 0,1, 2.., 18) and a point expected frequency value. Since the fitting straight line is zero-crossing, the fitting straight line can be fitted through a point of the expected frequency value and the zero point. For example, the desired frequency value may be a pre-stored value of F (1) for a current of 0.1 ma. Using the linear relationship of the fitting straight line of the zero-crossing points, F (n) ═ Tn × F (1) at each point can be calculated, where Tn is a multiple of the current at the point n with respect to 0.1ma, that is, Tn ═ I (n)/I (1) ═ F (n)/F (1), that is, the slope of the fitting straight line.
Compared with the method for storing the expected frequency values of a plurality of acquisition points, the method for calculating the expected frequency value of each acquisition point by using one point expected frequency value reduces the cost of the on-chip memory 123.
The error err (t) obtained by the digital compensator 121 is sent to the digital controller 122, and the generated compensation control signal may be a switching signal. When the switch is normally open, i.e., at a value of 1, the compensated frequency values are denoted as Fcomp _ max, which are written into efuse. Therefore, when the required compensation frequency is err (t), the output pulse duty ratio is err (t)/Fcomp _ max. Finally, the digital compensator 121 generates a corresponding compensation frequency according to the magnitude of the input current I, and finally feeds back the compensation frequency to the analog compensation current source 130 to generate compensation currents with different duty ratios, and the first current source 131 outputting a positive current and the second current source 134 outputting a negative current are selectively adjusted to increase or decrease the superimposed current accordingly. The compensation current source is controlled by the pulse switch signal, the compensation currents corresponding to different duty ratio switch signals are different, and finally linear output of the output frequency pulse signal is achieved.
In the IF chip 10 and the digital compensation method thereof of the present embodiment, a compensation current corresponding to a measured current is output by using the digital compensation method, and a frequency conversion error is eliminated by overlapping the compensation current with the measured current. The compensation mode improves the compensation precision, does not influence the bandwidth of the originally output frequency signal, and has wider application range. The on-chip storage space occupies little, and the cost is low, so that the linearity performance of the IF chip 10 is greatly improved, and the reliability is improved.
Thus, it should be appreciated by those skilled in the art that while a number of exemplary embodiments of the invention have been illustrated and described in detail herein, many other variations or modifications consistent with the principles of the invention may be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the invention. Accordingly, the scope of the invention should be understood and interpreted to cover all such other variations or modifications.
Claims (10)
1. An IF chip having a digital compensation function, comprising:
the analog processing module is configured to acquire a measured current input into the IF chip and perform frequency conversion on the measured current to obtain an initial frequency pulse signal;
a digital processing module configured to generate a corresponding compensation control signal according to the initial frequency pulse signal;
the compensation current source is configured to adjust the magnitude of compensation current output by the compensation current source according to the compensation control signal, so that the compensation current is superposed with the measured current to obtain superposed current; and is
The analog processing module is further configured to perform frequency conversion on the superposed current to obtain an output frequency pulse signal.
2. The IF chip with digital compensation function according to claim 1, wherein the analog processing module includes:
the analog integrator is configured to integrate the measured current and the superposed current respectively to obtain an initial current integral signal and a superposed current integral signal;
the analog controller is configured to perform frequency conversion on the initial current integration signal to obtain an initial frequency pulse signal; and carrying out frequency conversion on the superposed current integral signal to obtain the output frequency pulse signal.
3. The IF chip with digital compensation function according to claim 1, wherein the digital processing module includes:
the digital compensator is connected with the analog controller and is configured to determine a corresponding frequency compensation value according to the initial frequency pulse signal;
and the digital controller is connected with the digital compensator and is configured to generate the corresponding compensation control signal according to the frequency compensation value.
4. The IF chip with digital compensation function of claim 3, wherein the digital processing module further comprises:
the on-chip memory is connected with the digital compensator and is configured to store error calibration values of a plurality of set acquisition points; and is
The digital compensator is further configured to perform a linear difference calculation using the error calibration value to obtain the frequency compensation value.
5. The IF chip with digital compensation function according to claim 4, wherein
The on-chip memory is further configured to store an expected frequency value of a set acquisition point;
the digital compensator is further configured to determine a frequency calibration value corresponding to each error calibration value by using a linear relationship fit by the frequency calibration values and a zero point, and the frequency calibration value is used as a parameter required by the linear difference value calculation.
6. The IF chip with digital compensation function according to claim 3 or 4, wherein
The on-chip memory is an electronic fuse memory.
7. The IF chip with digital compensation function according to claim 1, wherein the compensation current source includes:
a first current source for outputting a forward current;
the second current source is used for outputting negative current;
the first adjusting switch is connected between the first current source and the analog processing module;
the second regulating switch is connected between the second current source and the analog processing module; and is
The digital processing module is further configured to provide the compensation control signal to the first regulation switch or the second regulation switch to change the magnitude of the compensation current by adjusting a switching ratio of the first regulation switch or the second regulation switch.
8. The IF chip with digital compensation function according to claim 7, wherein
The absolute values of the current amplitudes output by the first current source and the second current source are equal; and is
The first regulating switch and the second regulating switch are configured to output compensation currents with equal absolute values at the same switching ratio.
9. A method of digital compensation of an IF chip, comprising:
acquiring a measured current input into the IF chip, and performing frequency conversion on the measured current to obtain an initial frequency pulse signal;
generating a corresponding compensation control signal according to the initial frequency pulse signal;
adjusting the size of compensation current according to the compensation control signal, wherein the compensation current is used for being superposed with the measured current to obtain superposed current; and is
And carrying out frequency conversion on the superposed current to obtain an output frequency pulse signal.
10. The digital compensation method of the IF chip as claimed in claim 9, wherein the step of generating a corresponding compensation control signal according to the initial frequency pulse signal comprises:
acquiring a prestored multipoint error calibration value and a point expected frequency value;
determining a frequency calibration value corresponding to each error calibration value by utilizing the linear relation of the frequency calibration values and zero point fitting;
performing linear difference calculation on the initial frequency pulse signal according to the frequency calibration value and the corresponding error calibration value to obtain the frequency compensation value;
and generating a corresponding compensation control signal according to the frequency compensation value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011299972.7A CN112350672B (en) | 2020-11-19 | 2020-11-19 | IF chip with digital compensation function and digital compensation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011299972.7A CN112350672B (en) | 2020-11-19 | 2020-11-19 | IF chip with digital compensation function and digital compensation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112350672A true CN112350672A (en) | 2021-02-09 |
| CN112350672B CN112350672B (en) | 2023-01-24 |
Family
ID=74363074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011299972.7A Active CN112350672B (en) | 2020-11-19 | 2020-11-19 | IF chip with digital compensation function and digital compensation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112350672B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001324519A (en) * | 2000-05-16 | 2001-11-22 | Yamaha Corp | Current measuring circuit and current quantity of electricity measuring circuit |
| US6748036B1 (en) * | 1997-12-18 | 2004-06-08 | Nec Corporation | Radio receiving method and apparatus |
| JP2006078402A (en) * | 2004-09-10 | 2006-03-23 | Fuji Electric Systems Co Ltd | Ultra-micro current/frequency converter |
| CN203732923U (en) * | 2014-01-24 | 2014-07-23 | 张宏 | Coal mine monitoring sub-station I/F conversion plate |
| CN104737027A (en) * | 2012-10-23 | 2015-06-24 | Abb技术有限公司 | Apparatus and method for transmitting an analog signal, andanalog signal multiplexer |
| CN106888022A (en) * | 2015-12-15 | 2017-06-23 | 航天科工惯性技术有限公司 | A kind of high-resolution current/frequency conversion circuit |
| CN108474840A (en) * | 2016-01-22 | 2018-08-31 | 德克萨斯仪器股份有限公司 | Digital compensation for the mismatch in radar system |
| CN109885121A (en) * | 2019-03-22 | 2019-06-14 | 西安微电子技术研究所 | A kind of current/frequency conversion circuit |
| CN110572157A (en) * | 2019-08-30 | 2019-12-13 | 中勍科技有限公司 | temperature compensation method for I/F conversion circuit board |
| CN110581708A (en) * | 2019-10-12 | 2019-12-17 | 中国人民解放军国防科技大学 | frequency-locked loop type full digital frequency synthesizer |
| CN111174810A (en) * | 2019-12-31 | 2020-05-19 | 中国船舶重工集团公司第七一七研究所 | High-precision IF conversion module applied to inertial navigation system |
| CN111551771A (en) * | 2020-04-02 | 2020-08-18 | 垣矽技术(青岛)有限公司 | IF chip and digital compensation method thereof |
-
2020
- 2020-11-19 CN CN202011299972.7A patent/CN112350672B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6748036B1 (en) * | 1997-12-18 | 2004-06-08 | Nec Corporation | Radio receiving method and apparatus |
| JP2001324519A (en) * | 2000-05-16 | 2001-11-22 | Yamaha Corp | Current measuring circuit and current quantity of electricity measuring circuit |
| JP2006078402A (en) * | 2004-09-10 | 2006-03-23 | Fuji Electric Systems Co Ltd | Ultra-micro current/frequency converter |
| CN104737027A (en) * | 2012-10-23 | 2015-06-24 | Abb技术有限公司 | Apparatus and method for transmitting an analog signal, andanalog signal multiplexer |
| CN203732923U (en) * | 2014-01-24 | 2014-07-23 | 张宏 | Coal mine monitoring sub-station I/F conversion plate |
| CN106888022A (en) * | 2015-12-15 | 2017-06-23 | 航天科工惯性技术有限公司 | A kind of high-resolution current/frequency conversion circuit |
| CN108474840A (en) * | 2016-01-22 | 2018-08-31 | 德克萨斯仪器股份有限公司 | Digital compensation for the mismatch in radar system |
| CN109885121A (en) * | 2019-03-22 | 2019-06-14 | 西安微电子技术研究所 | A kind of current/frequency conversion circuit |
| CN110572157A (en) * | 2019-08-30 | 2019-12-13 | 中勍科技有限公司 | temperature compensation method for I/F conversion circuit board |
| CN110581708A (en) * | 2019-10-12 | 2019-12-17 | 中国人民解放军国防科技大学 | frequency-locked loop type full digital frequency synthesizer |
| CN111174810A (en) * | 2019-12-31 | 2020-05-19 | 中国船舶重工集团公司第七一七研究所 | High-precision IF conversion module applied to inertial navigation system |
| CN111551771A (en) * | 2020-04-02 | 2020-08-18 | 垣矽技术(青岛)有限公司 | IF chip and digital compensation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112350672B (en) | 2023-01-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7030800B2 (en) | Analog-to-digital conversion apparatus and method | |
| US4947168A (en) | Subranging analog-to-digital converter with calibration | |
| CN100444073C (en) | Automatic correcting current circuit and method | |
| US5121119A (en) | Analog-to-digital conversion method and system with correction of analog gain and offset | |
| US4336526A (en) | Successive approximation analog-to-digital converter using non-binary series | |
| CN112751565B (en) | Self-calibration on-chip reference voltage module | |
| CN102075188A (en) | Digital static calibration circuit of digital-to-analog converter (DAC) | |
| CN112350672B (en) | IF chip with digital compensation function and digital compensation method thereof | |
| CN114189245A (en) | ADC calibration circuit, control method thereof and storage medium | |
| CN116149243B (en) | High-precision time sequence control method and device | |
| US4549165A (en) | Dynamic voltage reference apparatus for A/D converters | |
| CN107656572B (en) | Multi-path adjustable voltage source realized by digital-to-analog converter and control method thereof | |
| CN111240251A (en) | High-precision AD sampling correction method based on MCU | |
| JP2000151409A (en) | A/d converter and regulator for grade amplifier | |
| CN111551771A (en) | IF chip and digital compensation method thereof | |
| CN114614820A (en) | ADC error trimming method and system and error trimming device | |
| WO2022048276A1 (en) | Offset voltage correction circuit and offset voltage correction method | |
| CN114826206B (en) | Phase shifter phase calibration circuit and calibration method thereof | |
| JP2001339303A (en) | Analog/digital converter circuit | |
| CN116505947B (en) | Analog-to-digital converter calibration method, device, storage medium and chip | |
| US11558060B2 (en) | Ratiometric analog-to-digital conversion circuit | |
| US11671107B2 (en) | Analog-to-digital converter and method thereof | |
| CN117728838B (en) | Analog-to-digital conversion device and calibration method for ADC offset error | |
| CN220399527U (en) | Current sampling control device of servo motor | |
| CN111490786B (en) | Calibration method and device of digital-to-analog converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |