CN114189245A - ADC calibration circuit, control method thereof and storage medium - Google Patents
ADC calibration circuit, control method thereof and storage medium Download PDFInfo
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- CN114189245A CN114189245A CN202111555305.5A CN202111555305A CN114189245A CN 114189245 A CN114189245 A CN 114189245A CN 202111555305 A CN202111555305 A CN 202111555305A CN 114189245 A CN114189245 A CN 114189245A
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Abstract
The invention discloses an ADC calibration circuit, a control method thereof and a storage medium, wherein the circuit comprises a calibration sampling sub-circuit and a compensation sub-circuit; the calibration sampling sub-circuit comprises an analog-to-digital converter and is used for providing a first reference value, a second reference value and a value to be calibrated to the compensation sub-circuit through the analog-to-digital converter; the compensation sub-circuit is used for calibrating the value to be calibrated according to the first reference value and the second reference value to obtain the corresponding digital calibration value. The circuit provides a first reference value and a second reference value for calibration in a double fixed-point sampling mode, carries out calibration compensation on a value to be calibrated, effectively reduces the influence of offset error and gain error on the conversion precision of the ADC, effectively improves the conversion precision of the ADC, and has the advantages of easiness in realization and integration in circuit design and suitability for more complex application scenes.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to an ADC calibration circuit, a control method thereof, and a storage medium.
Background
An Analog-to-Digital Converter (ADC), referred to as an a/D Converter for short, is a circuit for converting an Analog signal into a Digital signal, and is generally integrated as a functional module in an SOC Chip (System on Chip) and widely applied to various application fields of the Chip. The analog input voltage and the digital output value of an ideal analog-to-digital converter have a fixed gain, i.e. they are linear. However, in practical applications, due to the influence of various factors such as process deviation, circuit limitation, environmental noise and the like, the analog-to-digital converter has several common defects such as offset error, gain error, linearity error and the like, and the conversion accuracy and the practical application of the analog-to-digital converter are seriously influenced.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, an object of the present invention is to provide an ADC calibration circuit, which effectively reduces the influence of offset error and gain error on the ADC conversion precision, effectively improves the ADC conversion precision, and has the advantages of being easily implemented and integrated in circuit design, and being suitable for more complex application scenarios.
A second objective of the present invention is to provide a control method for an ADC calibration circuit.
A third object of the invention is to propose a computer-readable storage medium.
In order to achieve the above object, an embodiment of the first aspect of the present invention provides an ADC calibration circuit, where the circuit includes: calibrating the sampling sub-circuit and the compensation sub-circuit; the calibration sampling sub-circuit comprises an analog-to-digital converter, and is used for providing a first reference value, a second reference value and a value to be calibrated to the compensation sub-circuit through the analog-to-digital converter; the compensation sub-circuit is used for calibrating the value to be calibrated according to the first reference value and the second reference value to obtain a corresponding digital calibration value.
According to the ADC calibration circuit provided by the embodiment of the invention, the first reference value and the second reference value for calibration are provided in a double fixed-point sampling mode, calibration compensation is carried out on the value to be calibrated, the influence of offset error and gain error on the conversion precision of the ADC is effectively reduced, the conversion precision of the ADC is effectively improved, and the ADC calibration circuit has the advantages of easiness in realization and integration in circuit design and suitability for more complex application scenes.
In addition, the ADC calibration circuit according to the above embodiment of the present invention may further have the following additional technical features:
according to an embodiment of the invention, the calibration sampling sub-circuit further comprises: the double-fixed-point generating unit comprises a first resistor, a second resistor, a third resistor and a fourth resistor which are connected in series, wherein one end of the first resistor, the second resistor, the third resistor and the fourth resistor which are connected in series are used for connecting a low external reference voltage, the other end of the first resistor, the second resistor, the third resistor and the fourth resistor are used for connecting a high external reference voltage, the first reference end of the analog-to-digital converter is used for connecting the low external reference voltage, and the second reference end of the analog-to-digital converter is used for connecting the high external reference voltage; a first input end of the channel selector is connected with a node between the first resistor and the second resistor, a second input end of the channel selector is connected with a node between the third resistor and the fourth resistor, a third input end of the channel selector is used for inputting a voltage to be sampled corresponding to the value to be calibrated, and an output end of the channel selector is connected with an input end of the analog-to-digital converter; a controller, connected to the control terminal of the channel selector, the control terminal of the analog-to-digital converter, and the control terminal of the calibration sub-circuit, respectively, the controller being configured to: when the first input end and the output end of the channel selector are controlled to be communicated, a first reference voltage is input into the analog-to-digital converter, the analog-to-digital converter is controlled to convert the first reference voltage into the first reference value, the calibration sub-circuit is controlled to store the first reference value, when the second input end and the output end of the channel selector are controlled to be communicated, a second reference voltage is input into the analog-to-digital converter, the analog-to-digital converter is controlled to convert the second reference voltage into the second reference value, the calibration sub-circuit is controlled to store the second reference value, when the third input end and the output end of the channel selector are controlled to be communicated, the voltage to be sampled is input into the analog-to-digital converter, the analog-to-digital converter is controlled to convert the voltage to be sampled into the value to be calibrated, and the calibration sub-circuit is controlled to perform calibration according to the first reference value, And the second reference value calibrates the value to be calibrated.
According to one embodiment of the invention, the compensation sub-circuit comprises: the input end of the first register is connected with the output end of the analog-to-digital converter, the control end of the first register is connected with the controller, and the first register is used for storing the first reference value; the input end of the second register is connected with the output end of the analog-to-digital converter, the control end of the second register is connected with the controller, and the second register is used for storing the second reference value; the first input end of the logic operation unit is connected with the output end of the first register, the second input end of the logic operation unit is connected with the output end of the second register, the third input end of the logic operation unit is connected with the output end of the analog-to-digital converter, and the logic operation unit is used for performing logic operation on the value to be calibrated according to the first reference value and the second reference value and outputting a corresponding digital calibration value.
According to an embodiment of the present invention, the logical operation unit is specifically configured to: and carrying out gain calibration and offset calibration on the value to be calibrated according to the first reference value and the second reference value.
According to an embodiment of the invention, the compensation sub-circuit further comprises: and the input end of the shaping unit is connected with the output end of the logical operation unit and is used for shaping the digital calibration value output by the logical operation unit.
According to an embodiment of the invention, the logical operation unit is configured to implement the following equation:
wherein c "represents the calibration digital value, a represents the first reference value, b represents the second reference value, c represents the value to be calibrated, n represents the conversion accuracy of the analog-to-digital converter,
which represents the gain of the calibration, is,
indicating a misalignment.
According to an embodiment of the present invention, the logical operation unit includes: the input end of the first multiplier is connected with the output end of the first register and is used for multiplying the first reference value by-1; the input end of the second multiplier is connected with the output end of the analog-to-digital converter and is used for multiplying the value to be calibrated by 2; the input end of the third multiplier is connected with the output end of the first multiplier, and the third multiplier is used for multiplying the output value of the first multiplier by 3; a first full adder, a first input end of which is connected to an output end of the first multiplier, a second input end of which is connected to an output end of the second register, and which is configured to add an output value of the first multiplier and the second reference value; a second full adder, a first input end of the second full adder being connected to the output end of the second register, a second input end of the second full adder being connected to the output end of the second multiplier, the second full adder being configured to add the second reference value and the output value of the second multiplier; a third full adder, a first input end of the third full adder being connected to an output end of the third multiplier, a second input end of the second full adder being connected to an output end of the second full adder, the third full adder being configured to add an output value of the third multiplier and an output value of the second full adder; a fourth multiplier, an input end of which is connected with an output end of the third full adder, and is used for summing an output value of the third full adder with 2n-2Performing multiplication operation; a divider, a first input end of the divider is connected with an output end of the first full adder, a second input end of the divider is connected with an output end of the fourth multiplier, and the divider is usedAnd performing division operation on the output value of the fourth multiplier and the output value of the first full adder.
According to an embodiment of the present invention, the first resistor, the second resistor, the third resistor, and the fourth resistor have equal resistance values.
In order to achieve the above object, a second aspect of the present invention provides a control method for an ADC calibration circuit, where the ADC calibration circuit includes a calibration sampling sub-circuit, and the calibration sampling sub-circuit includes an analog-to-digital converter, and the method includes: receiving a first reference value, a second reference value and a value to be calibrated, which are provided by the calibration sampling sub-circuit through the analog-to-digital converter; and calibrating the value to be calibrated according to the first reference value and the second reference value to obtain a corresponding digital calibration value.
To achieve the above object, a third aspect of the present invention provides a computer-readable storage medium, on which a computer program is stored, the computer program, when being executed by a processor, implementing the control method of the ADC calibration circuit according to the second aspect of the present invention.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a schematic diagram of an ADC calibration circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a linear transformation for gain calibration and offset calibration according to an embodiment of the present invention;
fig. 3 is a flowchart of a control method of the ADC calibration circuit according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The ADC calibration circuit, the control method thereof, and the storage medium according to the embodiments of the present invention will be described in detail with reference to fig. 1 to 3 and the detailed description.
Fig. 1 is a schematic diagram of an ADC calibration circuit according to an embodiment of the present invention. As shown in fig. 1, the ADC calibration circuit includes a calibration sampling sub-circuit and a compensation sub-circuit.
The calibration sampling sub-circuit comprises an analog-to-digital converter, and the calibration sampling sub-circuit is used for providing the first reference value, the second reference value and the value to be calibrated to the compensation sub-circuit through the analog-to-digital converter.
Specifically, the first reference value and the second reference value are reference values obtained by performing analog-to-digital conversion on two known reference voltages (a first reference voltage and a second reference voltage, where the first reference voltage is smaller than the second reference voltage) of the analog-to-digital converter, and are used as reference values of the value to be calibrated, so as to calibrate the value to be calibrated according to the first reference value and the second reference value.
In an embodiment of the present invention, as shown in fig. 1, the calibration sampling sub-circuit may further include a dual fixed point generation unit, a channel selector, and a controller.
As a specific implementation manner, as shown in fig. 1, the dual fixed point generating unit includes a first resistor, a second resistor, a third resistor, and a fourth resistor connected in series, where one end of the first resistor, the second resistor, the third resistor, and the fourth resistor connected in series is used to connect to a low external reference voltage, and the other end of the first resistor, the second resistor, the third resistor, and the fourth resistor is used to connect to a high external reference voltage, where a first reference terminal of the analog-to-digital converter is used to connect to the low external reference voltage, and a second reference terminal of the analog-to-digital converter is used to connect to the high external reference voltage.
Specifically, the first resistor, the second resistor, the third resistor and the fourth resistor in the double fixed-point generation unit play a role in voltage division, one end of the first resistor, the second resistor, the third resistor and the fourth resistor which are sequentially connected in series is connected with a low external reference Voltage (VREFL) connected into the analog-to-digital converter, and the other end of the first resistor, the second resistor, the third resistor and the fourth resistor is connected with a high external reference Voltage (VREFH) connected into the analog-to-digital converter, and is used for dividing the low external reference voltage and the high external reference voltage connected into the analog-to-digital converter to obtain reference voltages (the first reference voltage and the second reference voltage) used for calibration.
In the embodiment of the present invention, the first resistor, the second resistor, the third resistor, and the fourth resistor have the same resistance. The resistance values of the four resistors are selected according to specific application requirements, and can be designed to be 1K-10K ohms or other suitable values.
In the embodiment of the present invention, as shown in fig. 1, a first input terminal of the channel selector is connected to a node between the first resistor and the second resistor, a second input terminal of the channel selector is connected to a node between the third resistor and the fourth resistor, a third input terminal of the channel selector is used to input a voltage to be sampled corresponding to a value to be calibrated, and an output terminal of the channel selector is connected to an input terminal of the analog-to-digital converter.
Specifically, a first input terminal of the channel selector is connected to a node between the first resistor and the second resistor to obtain a first reference voltage. The second input end of the channel selector is connected with a node between the third resistor and the fourth resistor and used for obtaining a second reference voltage. The channel selector may comprise a plurality of third input terminals for accessing voltages to be sampled corresponding to the plurality of values to be calibrated. The output end of the channel selector is connected with the input end of the analog-to-digital converter and used for inputting a first reference voltage, a second reference voltage and a voltage to be sampled to the analog-to-digital converter.
For better effect, the first reference voltage input end and the second reference voltage input end can be connected to an internal input channel of the analog-digital converter so as to reduce the line delay and isolate external interference as much as possible.
It should be noted that the channel selector includes a plurality of input terminals, the input terminal connected to the node between the first resistor and the second resistor is not limited to be connected to the first input terminal of the channel selector, the input terminal connected to the node between the third resistor and the fourth resistor is not limited to be connected to the second input terminal of the channel selector, and the voltage to be sampled corresponding to the value to be calibrated is not limited to be input through the third input terminal of the channel selector. I.e. the input terminal connected to the voltage to be sampled corresponding to the node between the first and second resistance, the node between the third and fourth resistance and the value to be calibrated, may be any input terminal of the channel selector.
In an embodiment of the present invention, as shown in fig. 1, a controller is connected to the control terminal of the channel selector, the control terminal of the analog-to-digital converter, and the control terminal of the calibration sub-circuit, respectively, and the controller is configured to: when the first input end of the control channel selector is communicated with the output end, a first reference voltage is input into the analog-to-digital converter, the analog-to-digital converter is controlled to convert the first reference voltage into a first reference value, the calibration sub-circuit is controlled to store the first reference value, when the second input end of the control channel selector is communicated with the output end, a second reference voltage is input into the analog-to-digital converter, the analog-to-digital converter is controlled to convert the second reference voltage into a second reference value, the calibration sub-circuit is controlled to store the second reference value, when the third input end of the control channel selector is communicated with the output end, a voltage to be sampled is input into the analog-to-digital converter, the analog-to-digital converter is controlled to convert the voltage to be sampled into a value to be calibrated, and the calibration sub-circuit is controlled to calibrate the value to be calibrated according to the first reference value and the second reference value.
In an embodiment of the present invention, the analog-to-digital converter includes ports of a conversion trigger (trig), a conversion end (done), a conversion output (Q), and the like, and corresponding functions.
In an embodiment of the invention, the controller supports functions such as external calibration trigger (trig) and calibration end (done).
Specifically, the controller receives an external calibration trigger, and after the controller detects an effective edge of the calibration trigger, the controller sequentially selects a channel connected with a first reference voltage and a second reference voltage as an effective input channel of the ADC, the first reference voltage and the second reference voltage are sequentially input to the analog-to-digital converter, and the analog-to-digital converter sequentially performs analog-to-digital conversion on the first reference voltage and the second reference voltage, so that the analog-to-digital converter outputs a first reference value a corresponding to the first reference voltage and a second reference value b corresponding to the second reference voltage. More specifically, the controller is further configured to control the compensation sub-circuit to store the first reference value a and the second reference value b, so that when the ADC calibration circuit is used to calibrate a plurality of voltages to be sampled, only one calibration needs to be performed initially. After the first reference value a and the second reference value b are generated, the controller controls a third input end of the channel selector to input the voltage to be sampled, the analog-to-digital converter completes analog-to-digital conversion of the voltage to be sampled, and outputs a value c to be calibrated corresponding to the voltage to be sampled.
The compensation sub-circuit is used for calibrating the value to be calibrated according to the first reference value and the second reference value to obtain the corresponding digital calibration value.
Specifically, the compensation sub-circuit performs calibration compensation on the input value c to be calibrated (raw data output by the ADC) according to the stored first reference value a and second reference value b to output a digital calibration value after the value c to be calibrated (calibration data output by the ADC calibration circuit).
In an embodiment of the present invention, as shown in fig. 1, the compensation sub-circuit may include a first register, a second register, and a logical operation unit. The input end of the first register is connected with the output end of the analog-to-digital converter, the control end of the first register is connected with the controller, and the first register is used for storing a first reference value; the input end of the second register is connected with the output end of the analog-to-digital converter, the control end of the second register is connected with the controller, and the second register is used for storing a second reference value; and the logic operation unit is used for performing logic operation on the calibration value to be calibrated according to the first reference value and the second reference value and outputting a corresponding digital calibration value.
Specifically, the controller controls the first register to store a first reference value a and controls the second register to store a second reference value b. And controlling the value c to be calibrated to be input into the logical operation unit, and carrying out calibration compensation on the value c to be calibrated according to the internal logical operation rule according to the received first reference value a and the second reference value b by the logical operation unit.
In the embodiment of the present invention, as shown in fig. 1, the compensation sub-circuit further includes a shaping unit, and an input end of the shaping unit is connected to an output end of the logical operation unit, and is configured to perform a shaping operation on the digital calibration value output by the logical operation unit.
Specifically, the shaping unit performs shaping operation on the digital calibration value output by the logic operation unit, and outputs the digital calibration value of the voltage to be sampled.
In an embodiment of the present invention, the logic operation unit is specifically configured to: and carrying out gain calibration and offset calibration on the value to be calibrated according to the first reference value and the second reference value.
Specifically, the invention adopts a method of center section linear calibration, and performs gain calibration and offset calibration on the to-be-calibrated value c according to the first reference value a and the second reference value b, so as to cover most applications of the ADC and improve the conversion accuracy of the analog-to-digital converter.
It should be noted that, in the embodiment of the present invention, the low external reference voltage VREFL and the high external reference voltage VREFH of the ADC can be equivalent to 0 and VREF, the external analog input should be in the range of 0-VREF, and the digital output should be in the range of 0-2n, where n represents the conversion accuracy of the ADC.
It should be noted that, in the embodiment of the present invention, the first reference value a is 1/4VREF reference value, and the second reference value b is 3/4VREF reference value.
In an embodiment of the present invention, the logic operation unit is configured to implement the following equation:
where c "denotes a calibration digital value, a denotes a first reference value, b denotes a second reference value, c denotes a value to be calibrated, n denotes the conversion accuracy of the analog-to-digital converter,
which represents the gain of the calibration, is,
indicating a misalignment.
In the embodiment of the present invention, there are an offset error, a gain error, and a linearity error due to a commonly used analog-to-digital converter. The linearity error is mostly concentrated at two ends of the conversion range of the analog-to-digital converter, namely a near 0 section and a near reference voltage VREF section, and the linearity error at the middle part is smaller. The middle part is also a linear working interval recommended by the analog-to-digital converter. Therefore, a first reference value a and a second reference value b are provided by a dual fixed point generating unit and the two reference values a and b are used as sampling calibration reference values by corresponding the two reference values to an ideal point 2 of an ideal transformationn-2And 3 x 2n-2By performing a linear fit over the gain and offset, gain and offset errors of the intermediate stage conversion of the ADC are minimized.
Specifically, as shown in fig. 2, gain calibration and offset calibration of the logical operation unit are explained:
the actual conversion of the ADC to the ideal conversion goes through two processes. The first process is center translation, and the center point of the actual conversion straight line is (a + b)/2 corresponding to the center point 2 of the ideal conversionn-1The direction and magnitude of the central translation can be obtained by subtracting the two (2)n-1- (a + b)/2). The second process is to fit the translation line with the ideal conversion line by rotation and expansion with the center point as the center. After fitting, 1/4VREF reference value a and an ideal conversion point 2 should be ensuredn-2Coinciding with the ideal switching point 3 x 2, i.e. point a ", and the reference value b of VREF 3/4n-2Coinciding with point b ". Thus, for any ADC conversion point c, the point c "of the ideal conversion line should be fitted to, and from the proportional relationship:
namely:
wherein the content of the first and second substances,
in order to calibrate the gain, the gain is calibrated,
to calibrate out-of-tune.
In the embodiment of the present invention, the logic operation involved in the ADC compensation sub-circuit should be able to select a signed number operation with sufficient number of bits according to the maximum precision n of the ADC. Wherein the multiply-constant operation is implemented using a complement, a left-shift, and an add,
representing a signed full add operation where the number of bits is sufficient. The only division operation can be realized by adopting binary-based cyclic subtraction right shift, a certain clock period is consumed, the operation time of the overall compensation is far shorter than the conversion time of the ADC, and the conversion rate of the ADC is not influenced to a certain extent. And the final shaping circuit is used for shaping the operation result c' and taking the value exceeding 2n as 2n and taking the negative value as 0.
It should be noted that, a ' in fig. 2 represents a first reference value after the center point is out of adjustment calibrated, b ' a second reference value after the center point is out of adjustment calibrated, and c ' a value to be calibrated after the center point is out of adjustment calibrated.
As a specific embodiment, the logical operation unit may include a first multiplier, a second multiplier, a third multiplier, a first full adder, a second full adder, a third full adder, a fourth multiplier, and a divider. The input end of the first multiplier is connected with the output end of the first register and is used for multiplying the first reference value by-1; the input end of the second multiplier is connected with the output end of the analog-to-digital converter and is used for multiplying the value to be calibrated by 2; the input end of the third multiplier is connected with the output end of the first multiplier and is used for multiplying the output value of the first multiplier by 3; the first input end of the first full adder is connected with the output end of the first multiplier, the second input end of the first full adder is connected with the output end of the second register, and the first full adder is used for the first multiplierAdding the output value and the second reference value; the first input end of the second full adder is connected with the output end of the second register, the second input end of the second full adder is connected with the output end of the second multiplier, and the second full adder is used for adding the second reference value and the output value of the second multiplier; the first input end of the third full adder is connected with the output end of the third multiplier, the second input end of the second full adder is connected with the output end of the second full adder, and the third full adder is used for performing addition operation on the output value of the third multiplier and the output value of the second full adder; the input end of the fourth multiplier is connected with the output end of the third full adder and is used for summing the output value of the third full adder with 2n-2Performing multiplication operation; and the divider is used for dividing the output value of the fourth multiplier and the output value of the first full adder.
According to the ADC calibration circuit provided by the embodiment of the invention, two known reference voltages inside are sampled and converted to be used as reference bases in a hardware self-calibration mode, and real-time central calibration compensation is carried out on output data of the analog-to-digital converter through the compensation sub-circuit, so that the influence of offset errors and gain errors on the ADC conversion precision is effectively reduced. Specifically, by using a double fixed-point sampling and compensation mode, the gain error and the offset error of the central section of the ADC are effectively eliminated, and the conversion precision of the ADC is effectively improved. And the calibration and compensation are completed by the built-in internal hardware circuit, so that the recalibration can be carried out at any time, and the method is suitable for more complex application scenes. The ADC self-calibration and error compensation are completed through the hardware circuit, the resource overhead of off-chip hardware and execution software for the ADC calibration and error compensation is effectively reduced, and the effective conversion rate of the ADC is ensured. The double fixed-point generating unit can be realized by resistance voltage division, and the logic operation unit is designed by pure digital logic and is easy to realize and integrate in circuit design.
In the embodiment of the invention, the ADC self-calibration circuit provided by the embodiment of the invention can be integrated in a chip design.
The invention also provides a control method of the ADC calibration circuit.
The control method of the ADC calibration circuit is used for controlling the ADC calibration circuit, the ADC calibration circuit comprises a calibration sampling sub-circuit, and the calibration sampling sub-circuit comprises an analog-to-digital converter. The control method of the ADC calibration circuit comprises the following steps:
and S1, receiving the first reference value, the second reference value and the value to be calibrated, which are provided by the calibration sampling sub-circuit through the analog-to-digital converter.
And S2, calibrating the to-be-calibrated value according to the first reference value and the second reference value to obtain a corresponding digital calibration value.
It should be noted that, for other specific implementations of the control method of the ADC calibration circuit according to the embodiment of the present invention, reference may be made to the specific implementations of the ADC calibration circuit according to the above-mentioned embodiments of the present invention.
According to the control method of the ADC calibration circuit, the first reference value and the second reference value for calibration are provided in a double fixed-point sampling mode, calibration compensation is performed on the value to be calibrated, the influence of offset error and gain error on the ADC conversion precision is effectively reduced, and the ADC conversion precision is effectively improved.
The invention also provides a computer readable storage medium.
In this embodiment, a computer program is stored on a computer readable storage medium, and the computer program corresponds to the control method of the ADC calibration circuit, which when executed by a processor, implements the control method of the ADC calibration circuit as proposed in the second embodiment of the present invention.
It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, such as an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. An ADC calibration circuit, the circuit comprising: calibrating the sampling sub-circuit and the compensation sub-circuit;
the calibration sampling sub-circuit comprises an analog-to-digital converter, and is used for providing a first reference value, a second reference value and a value to be calibrated to the compensation sub-circuit through the analog-to-digital converter;
the compensation sub-circuit is used for calibrating the value to be calibrated according to the first reference value and the second reference value to obtain a corresponding digital calibration value.
2. The ADC calibration circuit of claim 1, wherein the calibration sampling sub-circuit further comprises:
the double-fixed-point generating unit comprises a first resistor, a second resistor, a third resistor and a fourth resistor which are connected in series, wherein one end of the first resistor, the second resistor, the third resistor and the fourth resistor which are connected in series are used for connecting a low external reference voltage, the other end of the first resistor, the second resistor, the third resistor and the fourth resistor are used for connecting a high external reference voltage, the first reference end of the analog-to-digital converter is used for connecting the low external reference voltage, and the second reference end of the analog-to-digital converter is used for connecting the high external reference voltage;
a first input end of the channel selector is connected with a node between the first resistor and the second resistor, a second input end of the channel selector is connected with a node between the third resistor and the fourth resistor, a third input end of the channel selector is used for inputting a voltage to be sampled corresponding to the value to be calibrated, and an output end of the channel selector is connected with an input end of the analog-to-digital converter;
a controller, connected to the control terminal of the channel selector, the control terminal of the analog-to-digital converter, and the control terminal of the calibration sub-circuit, respectively, the controller being configured to:
when the first input end of the channel selector is controlled to be communicated with the output end, a first reference voltage is input into the analog-to-digital converter, the analog-to-digital converter is controlled to convert the first reference voltage into a first reference value, and the calibration sub-circuit is controlled to store the first reference value,
when the second input end of the channel selector is controlled to be communicated with the output end, a second reference voltage is input into the analog-to-digital converter, the analog-to-digital converter is controlled to convert the second reference voltage into a second reference value, and the calibration sub-circuit is controlled to store the second reference value,
when the third input end of the channel selector is controlled to be communicated with the output end, the voltage to be sampled is input to the analog-to-digital converter, the analog-to-digital converter is controlled to convert the voltage to be sampled into the value to be calibrated, and the calibration sub-circuit is controlled to calibrate the value to be calibrated according to the first reference value and the second reference value.
3. The ADC calibration circuit of claim 2, wherein the compensation sub-circuit comprises:
the input end of the first register is connected with the output end of the analog-to-digital converter, the control end of the first register is connected with the controller, and the first register is used for storing the first reference value;
the input end of the second register is connected with the output end of the analog-to-digital converter, the control end of the second register is connected with the controller, and the second register is used for storing the second reference value;
the first input end of the logic operation unit is connected with the output end of the first register, the second input end of the logic operation unit is connected with the output end of the second register, the third input end of the logic operation unit is connected with the output end of the analog-to-digital converter, and the logic operation unit is used for performing logic operation on the value to be calibrated according to the first reference value and the second reference value and outputting a corresponding digital calibration value.
4. The ADC calibration circuit of claim 3, wherein the logic operation unit is specifically configured to:
and carrying out gain calibration and offset calibration on the value to be calibrated according to the first reference value and the second reference value.
5. The ADC calibration circuit of claim 4 wherein the compensation sub-circuit further comprises:
and the input end of the shaping unit is connected with the output end of the logical operation unit and is used for shaping the digital calibration value output by the logical operation unit.
6. The ADC calibration circuit of claim 4, wherein the logic operation unit is configured to implement the following equation:
wherein c "represents the calibration digital value, a represents the first reference value, b represents the second reference value, c represents the value to be calibrated, n represents the conversion accuracy of the analog-to-digital converter,
which represents the gain of the calibration, is,
indicating a misalignment.
7. The ADC calibration circuit of claim 6, wherein the logic operation unit comprises:
the input end of the first multiplier is connected with the output end of the first register and is used for multiplying the first reference value by-1;
the input end of the second multiplier is connected with the output end of the analog-to-digital converter and is used for multiplying the value to be calibrated by 2;
the input end of the third multiplier is connected with the output end of the first multiplier, and the third multiplier is used for multiplying the output value of the first multiplier by 3;
a first full adder, a first input end of which is connected to an output end of the first multiplier, a second input end of which is connected to an output end of the second register, and which is configured to add an output value of the first multiplier and the second reference value;
a second full adder, a first input end of the second full adder being connected to the output end of the second register, a second input end of the second full adder being connected to the output end of the second multiplier, the second full adder being configured to add the second reference value and the output value of the second multiplier;
a third full adder, a first input end of the third full adder being connected to an output end of the third multiplier, a second input end of the second full adder being connected to an output end of the second full adder, the third full adder being configured to add an output value of the third multiplier and an output value of the second full adder;
a fourth multiplier, an input terminal of which is connected with the third full additionThe output end of the adder is connected and used for adding the output value of the third full adder to 2n-2Performing multiplication operation;
and a first input end of the divider is connected with the output end of the first full adder, a second input end of the divider is connected with the output end of the fourth multiplier, and the divider is used for dividing the output value of the fourth multiplier and the output value of the first full adder.
8. The ADC calibration circuit of claim 2, wherein the first resistor, the second resistor, the third resistor and the fourth resistor have the same resistance.
9. A method of controlling an ADC calibration circuit, the ADC calibration circuit comprising a calibration sampling sub-circuit comprising an analog-to-digital converter, the method comprising:
receiving a first reference value, a second reference value and a value to be calibrated, which are provided by the calibration sampling sub-circuit through the analog-to-digital converter;
and calibrating the value to be calibrated according to the first reference value and the second reference value to obtain a corresponding digital calibration value.
10. A computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the method of controlling an ADC calibration circuit according to claim 9.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116743170A (en) * | 2023-08-16 | 2023-09-12 | 南京芯惠半导体有限公司 | Multichannel analog-to-digital converter and calibration method thereof |
| WO2024098852A1 (en) * | 2022-11-07 | 2024-05-16 | 长鑫存储技术有限公司 | Calibration circuit |
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- 2021-12-17 CN CN202111555305.5A patent/CN114189245A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024098852A1 (en) * | 2022-11-07 | 2024-05-16 | 长鑫存储技术有限公司 | Calibration circuit |
| CN116743170A (en) * | 2023-08-16 | 2023-09-12 | 南京芯惠半导体有限公司 | Multichannel analog-to-digital converter and calibration method thereof |
| CN116743170B (en) * | 2023-08-16 | 2023-10-13 | 南京芯惠半导体有限公司 | Multichannel analog-to-digital converter and calibration method thereof |
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