CN112347018A - FlexRay-CPCIe communication module based on single chip microcomputer and FPGA - Google Patents
FlexRay-CPCIe communication module based on single chip microcomputer and FPGA Download PDFInfo
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- CN112347018A CN112347018A CN202011253732.3A CN202011253732A CN112347018A CN 112347018 A CN112347018 A CN 112347018A CN 202011253732 A CN202011253732 A CN 202011253732A CN 112347018 A CN112347018 A CN 112347018A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Abstract
The invention discloses a FlexRay-CPCIe communication module based on a single chip microcomputer and an FPGA (field programmable gate array), wherein a FlexRay communication unit comprises the single chip microcomputer and a bus transceiver, the bus transceiver is controlled by a minimum system of the single chip microcomputer to realize data receiving and transmitting of a FlexRay bus, and a FlexRay communication protocol is executed by the single chip microcomputer; the FPGA minimum system is a control core of a CPCIe communication unit, realizes clock management and logic control of a communication module by designing an IP core and an integrated hard core in an FPGA chip, executes PCIe bus standard and realizes data exchange between a computer and the communication module; and the data exchange between the FlexRay communication unit and the CPCIe communication unit is realized through a local bus between the single chip microcomputer and the FPGA. The invention can be directly installed on the computer backboard with the CPCIe interface; and the data exchange between two communication protocols of the PCIe system bus and the FlexRay high-speed external bus is realized.
Description
Technical Field
The invention belongs to the technical field of network communication, and relates to a FlexRay-CPCIe communication module based on a single chip microcomputer and an FPGA (field programmable gate array), which is used for realizing data communication between a computer and a FlexRay high-speed external bus through a PCIe (peripheral component interface express) system bus.
Background
Bus communication is widely applied to various industrial control networks, mainly aims to solve the problem of communication among different electronic devices, and is particularly embodied in the fields of aerospace, automobile manufacturing, navigation, automatic control, process industry and the like. At present, the external bus communication technology with long application time and mature technical development comprises a CAN bus, a 1553B bus and the like, and has the characteristics of high reliability, high certainty, high fault tolerance and the like. However, with the continuous development of scientific technology, the increasing data volume and the higher real-time communication requirement have gradually challenged the conventional external bus communication technology, and a new generation of high-speed external bus technology FlexRay bus is beginning to be applied in the related field.
As a new generation high-speed serial external bus protocol, FlexRay has obvious advantages in the aspects of communication speed/reliability, flexibility and the like compared with the traditional bus. The FlexRay bus is only applied to vehicle-mounted bus communication networks of a few brands at present, and has a great application prospect. Compared with the data transmission rate of 1Mbps highest for the CAN bus and the 1553B bus, the data transmission rate of a single channel of the FlexRay bus supports 10Mbps highest, and the total transmission rate of the two channels CAN reach 20Mbps highest, so that the communication requirements of large data volume and high real-time performance CAN be met; the two channels can realize three working modes of single-channel working, double-channel working and redundant working. In addition, the FlexRay bus network has flexible topological structure and supports various structures such as point-to-point, bus type, active star type and the like. In the aspect of a communication mechanism, a FlexRay bus adopts cycle communication, a data frame is supported to 254 frames at most, and a receiving node can be ensured to predict the arrival time of a message in advance by reasonably configuring a communication cycle and the message length.
In a system bus communication network, a third generation I/O bus-PCIe bus gradually replaces a second generation I/O bus-PCI bus technology due to its characteristics of supporting serial differential transmission, flexible bandwidth, high transmission rate, and the like, and is widely applied to a computer backplane interface to implement data communication among a CPU, a memory, and other board cards. Compared with the common PCIe interface, the CPCIe interface is more widely applied to the fields of military industry, measurement and control, aerospace and the like due to the characteristics of strong electromagnetic compatibility, good oxidation resistance and the like. Because computers have the advantages of human-computer interactivity, strong system operability and the like, the computers are generally used as upper computers or network nodes to take charge of receiving and sending commands and collecting and monitoring data. The communication between the board cards or the board cards and the computer is realized by installing the board cards with different functions on a computer backboard with a CPCIe interface. When the computer needs to communicate with an external bus, a bus communication module based on a CPCIe interface is added in the case aiming at a specific external communication bus protocol.
However, the two communication protocols of the PCIe system bus and the FlexRay high-speed external bus are not compatible with each other, which restricts the application range of the FlexRay high-speed bus while the computer functions in the FlexRay bus communication network. Therefore, the FlexRay bus communication module based on the CPCIe is designed, the module can be freely installed in a CPCIe standard interface on a backboard of a computer case, a single chip microcomputer and an FPGA are adopted to respectively complete the transceiving control of two buses, the data communication between a computer and a FlexRay high-speed external bus through a PCIe system bus is realized, the development, simulation and test of a FlexRay bus network are further realized through an operating system based on the computer, and the convenience of the application of the FlexRay bus is improved.
Disclosure of Invention
Objects of the invention
The purpose of the invention is: aiming at the problem that two communication protocols of a PCIe system bus and a FlexRay high-speed external bus are incompatible with each other, a method for realizing a FlexRay-CPCIe communication module based on a single chip microcomputer and an FPGA is provided, and the functions of using a computer as an upper computer or a network node, communicating with the FlexRay bus, receiving and sending commands to the FlexRay high-speed bus, and acquiring and monitoring data are realized.
(II) technical scheme
In order to solve the technical problem, the invention provides a FlexRay-CPCIe communication module based on a single chip microcomputer and an FPGA, which comprises a FlexRay communication unit, a CPCIe communication unit and a power circuit unit. The communication module is characterized in that the FlexRay communication unit adopts a FlexRay bus node frame scheme consisting of a singlechip and a bus transceiver to realize data transmission between the communication module and an external FlexRay high-speed bus network; the bus transceiver is controlled by a minimum system of the singlechip to realize the data transceiving of a FlexRay bus, and a FlexRay communication protocol is executed by the singlechip; the FPGA minimum system is a control core of a CPCIe communication unit, realizes clock management and logic control of a communication module by designing an IP core and an integrated hard core in an FPGA chip, executes PCIe bus standard and realizes data exchange between a computer and the communication module; the data exchange between the FlexRay communication unit and the CPCIe communication unit is realized through a local bus between the single chip microcomputer and the FPGA; and the power circuit unit supplies power to each unit of the communication module. The communication module is arranged on a CPCIe back plate in a computer case, so that functions of developing and testing a FlexRay high-speed bus by using a computer operating system are realized.
The minimum system of the single chip microcomputer comprises a single chip microcomputer chip, a clock circuit, a reset circuit and a debugging interface circuit.
The single chip microcomputer chip is exemplified by an MPC5644A microcontroller of NXP corporation in the patent, but is not limited to different types of chips.
The bus transceiver chip is connected with the single chip microcomputer, and the bus transceiver chip in the patent takes TJA1080 as an example, but is not limited to chips of different types.
The FPGA minimum system comprises an FPGA chip, a clock circuit, a reset circuit and a debugging interface circuit.
The FPGA chip is exemplified by XC5VLX110T chips of Virtex-5 series from Xilinx corporation, but is not limited to chips of different types.
The FlexRay communication unit adopts a FlexRay module in the single chip microcomputer to realize a communication protocol.
The CPCIe communication unit is designed by adopting an FPGA chip internal integrated hardmac.
The CPCIe communication unit is connected with a CPCIe back plate in the computer case by adopting a CPCIe standard interface, so that data transmission between the communication module and the computer is realized.
The power supply circuit unit provides power supply requirements for the FlexRay communication unit and the CPCIe communication unit respectively.
(III) advantageous effects
The FlexRay-CPCIe communication module based on the single chip microcomputer and the FPGA adopts the single chip microcomputer and the FPGA to respectively control the FlexRay communication unit and the CPCIe communication unit. Data of the FlexRay bus are processed by the single chip microcomputer, then are exchanged with the FPGA through a local bus, and are sent to a computer through the CPCIe communication unit; meanwhile, commands issued by the computer are processed by the FPGA through the CPCIe communication unit and then are sent to a designated terminal on the bus through the singlechip-controlled FlexRay communication unit controlled by the local bus. The functions of receiving and sending commands to the FlexRay high-speed bus, and acquiring and monitoring data by using a computer as an upper computer or a network node are realized; the beneficial effects and advantages are as follows:
1. the communication module can be directly installed on a computer backboard with a CPCIe interface;
2. and the data exchange between two communication protocols of the PCIe system bus and the FlexRay high-speed external bus is realized.
3. The method realizes development, simulation and test of the FlexRay bus network by the computer-based operating system, and improves the convenience of the application of the FlexRay bus.
Drawings
FIG. 1 is a schematic diagram of a FlexRay-CPCIe communication module based on a single chip microcomputer and an FPGA;
FIG. 2 is a schematic diagram of a minimum system of a single chip microcomputer;
FIG. 3 is a schematic diagram of the FPGA minimal system of the present invention;
FIG. 4 is a schematic diagram of a CPCIe communication unit of the present invention;
fig. 5 a schematic diagram of a FlexRay communication unit according to the invention;
FIG. 6 is a schematic diagram of a local bus between the single chip microcomputer and the FPGA;
FIG. 7 is a functional diagram of the asynchronous FIFO logic of the present invention;
fig. 8 is a schematic diagram of a power module of the present invention.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
FIG. 1 is a schematic diagram of a FlexRay-CPCIe communication module based on a single chip microcomputer and an FPGA. The communication module includes a FlexRay communication unit, a CPCIe communication unit, and a power supply circuit unit. The FlexRay communication unit adopts a FlexRay bus node frame scheme consisting of a singlechip and a bus transceiver to realize data transmission between the communication module and an external FlexRay high-speed bus network; the bus transceiver is controlled by a minimum system of the singlechip to realize the data transceiving of a FlexRay bus, and a FlexRay communication protocol is executed by the singlechip; the FPGA minimum system is a control core of a CPCIe communication unit, realizes clock management and logic control of a communication module by designing an IP core and an integrated hard core in an FPGA chip, executes PCIe bus standard and realizes data exchange between a computer and the communication module; the data exchange between the FlexRay communication unit and the CPCIe communication unit is realized through a local bus between the single chip microcomputer and the FPGA; and the power circuit unit supplies power to each unit of the communication module. The communication module is arranged on a CPCIe back plate in a computer case, so that functions of developing and testing a FlexRay high-speed bus by using a computer operating system are realized.
Fig. 2 is a schematic diagram of the minimum system of the single chip microcomputer. The minimum system of the single chip microcomputer comprises a single chip microcomputer chip, a clock circuit, a reset circuit and a debugging interface circuit. The single chip microcomputer chip adopts an MPC5644A microcontroller of NXP company, is based on an e200z4 Power Architecture core structure and has 150MHz working frequency; 1 double-channel FlexRay interface, and completes the transplantation of FlexRay communication protocol inside; 1 EBI interface configurable for a local bus. The clock circuit adopts a high-precision external crystal oscillator; the configuration interface may satisfy a debug (JTAG) mode sum.
FIG. 3 is a schematic diagram of the minimum system of the FPGA of the present invention. The FPGA minimum system comprises an FPGA chip, a clock circuit, a configuration interface and a program storage circuit. The FPGA chip adopts an XC5VLX110T chip of Virtex-5 series of Xilinx company, and the chip has up to 680 user-defined I/O pin interfaces and a plurality of configuration modes, so that the design flexibility is improved; the 16 high-speed serial transceivers (GTP) and the PCIe module of the hard core endpoint can be directly used for receiving and transmitting PCIe data; the clock adopts a high-precision external crystal oscillator; in order to enhance the configuration efficiency of the FPGA chip, the configuration interface can simultaneously meet a debugging action group (JTAG) mode and a Bit Peripheral Interface (BPI) mode; the program storage chip adopts a StrataFlash chip.
Fig. 4 is a schematic diagram of a CPCIe communication unit of the present invention. The CPCIe communication unit realizes the PCIe communication of the communication module by utilizing a PCIe hard core and a high-speed data input/output interface (socket I/O) IP core which are integrated in the FPGA. The sending/receiving control and the configuration state check are written by verilog language, wherein the sending/receiving control is responsible for extracting and storing data of the data cache module, and the configuration state check is responsible for checking the state of the PCIe hard core configuration space. The PCIe integrated hard core is completely compatible with PCIe 1.1 version, and realizes the functions of a bus transaction layer, a data link layer and a physical layer protocol. After the data passes through the PCIe integrated hardmac, a high-speed serial transceiver (GTP) of a high-speed data input/output interface (socket I/O) is directly connected to the CPCIe standard connector, so that the PCIe data is transmitted and received.
Fig. 5 is a schematic diagram of a FlexRay bus communication unit according to the invention. The FlexRay bus communication unit adopts a FlexRay bus node framework scheme of a communication controller and bus drivers, and comprises the communication controller and the two bus drivers respectively. The communication controller chip is connected with the FPGA and adopts MFR 4310; the two bus driver chips are respectively connected with the communication control chip by adopting TJA 1080. The single chip microcomputer is connected with the bus driver through a data signal and a receiving/sending enabling signal.
Fig. 6 is a schematic diagram of a local bus between the single chip microcomputer and the FPGA. The single chip microcomputer is connected with the FPGA through an EBI interface of the MPC5644A and comprises clock signals, data signals, address signals and read/write enabling signals. When external FlexRay data are received, the write enable of the single chip microcomputer is effective, and the data are transmitted to the FPGA; when FlexRay data needs to be sent, the read enable of the single chip microcomputer is effective, and PCIe data processed by the FPGA are read.
FIG. 7 is a functional diagram of the asynchronous FIFO logic of the present invention. Due to the fact that clock rates of the FlexRay data transceiver module and the CPCIe data transceiver module are different, in order to avoid data loss, an asynchronous FIFO is adopted in the FPGA for caching data. The asynchronous FIFO mainly comprises a double-port RAM, a read/write address generator and an empty/full signal generator. And for the FlexRay data transceiver module and the CPCIe data transceiver module, the working modes of asynchronous FIFO are consistent. The transmission of the signal is controlled by a write clock and write enable (transmission enable), and when the non-full signal is valid, transmission data and an address are written into the RAM; the data and address are then sent to the corresponding communication protocol, controlled by the read clock and read enable (communication protocol receive enable). The receiving of the signal is controlled by a write clock and a write enable (communication protocol transmission enable), and when the non-full signal is effective, the received data and the address are written into the RAM; then controlled by the read clock and read enable (receive enable), extracts the data and address, and performs the subsequent operations.
Fig. 8 is a schematic diagram of a power module of the present invention. The power module adopts a multi-output DC/DC chip to provide a stable power supply for the communication module. The FPGA relates to 1.2V, 1.5V and 3.3V power supply, the single chip microcomputer supplies power for 1.2V and 3.3V, and the TJA1080 supplies power for 3.3V.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A FlexRay-CPCIe communication module based on a single chip microcomputer and an FPGA is characterized by comprising a FlexRay communication unit and a CPCIe communication unit, wherein the FlexRay communication unit adopts a FlexRay bus node frame scheme consisting of the single chip microcomputer and a bus transceiver to realize data transmission between the communication module and an external FlexRay bus network; the bus transceiver is controlled by a minimum system of the singlechip to realize the data transceiving of a FlexRay bus, and a FlexRay communication protocol is executed by the singlechip; the FPGA minimum system is a control core of a CPCIe communication unit, realizes clock management and logic control of a communication module by designing an IP core and an integrated hard core in an FPGA chip, executes PCIe bus standard and realizes data exchange between a computer and the communication module; and the data exchange between the FlexRay communication unit and the CPCIe communication unit is realized through a local bus between the single chip microcomputer and the FPGA.
2. The FlexRay-CPCIe communication module based on the single chip microcomputer and the FPGA of claim 1, further comprising: and the power supply circuit unit is used for supplying power to the FlexRay communication unit and the CPCIe communication unit.
3. The FlexRay-CPCIe communication module based on the single chip microcomputer and the FPGA as claimed in claim 2, wherein the communication module is installed on a CPCIe back plate in a computer case, and a computer operating system is used for developing and testing a FlexRay high-speed bus.
4. The FlexRay-CPCIe communication module based on the single chip microcomputer and the FPGA as claimed in claim 3, wherein the single chip microcomputer minimal system comprises a single chip microcomputer chip and a clock circuit, a reset circuit and a configuration interface which are connected with the single chip microcomputer chip; the single chip microcomputer chip adopts an MPC5644A microcontroller of NXP company, is based on an e200z4 Power Architecture core structure and has 150MHz working frequency; the configuration interface includes: 1 double-channel FlexRay interface, which completes the transplantation of FlexRay communication protocol; 1 EBI interface configurable for a local bus; the clock circuit adopts an external crystal oscillator.
5. The FlexRay-CPCIe communication module based on the single chip microcomputer and the FPGA as claimed in claim 4, wherein the FPGA minimum system comprises an FPGA chip and a clock circuit, a configuration interface and a program storage circuit which are connected with the FPGA chip; the FPGA chip adopts Virtex-5 series XC5VLX110T chip of Xilinx company, and the program storage circuit adopts StrataFlash chip.
6. The FlexRay-CPCIe communication module based on the single chip microcomputer and the FPGA as claimed in claim 5, wherein the CPCIe communication unit utilizes a PCIe hard core and a high-speed data input output interface IP core integrated in the FPGA to realize PCIe communication of the communication module.
7. The FlexRay-CPCIe communication module based on the single chip microcomputer and the FPGA as claimed in claim 6, wherein the FlexRay bus communication unit adopts a FlexRay bus node framework scheme of a communication controller and a bus driver, and includes a communication controller chip and two bus drivers, the communication controller chip is connected with the FPGA, the two bus driver chips are respectively connected with the communication control chip, and the single chip microcomputer and the bus driver are connected with the receive/transmit enable signal through a data signal.
8. The FlexRay-CPCIe communication module based on the single chip microcomputer and the FPGA as claimed in claim 7, wherein the single chip microcomputer and the FPGA are connected through an EBI interface of the MPC5644A, and the EBI interface comprises a clock signal, a data signal, an address signal and a read/write enable signal; when external FlexRay data are received, the write enable of the single chip microcomputer is effective, and the data are transmitted to the FPGA; when FlexRay data needs to be sent, the read enable of the single chip microcomputer is effective, and PCIe data processed by the FPGA are read.
9. The FlexRay-CPCIe communication module based on the single chip microcomputer and the FPGA of claim 8, wherein an asynchronous FIFO is used inside the FPGA for buffering data, the asynchronous FIFO includes a dual port RAM, a read/write address generator and an empty/full signal generator, and the working modes of the asynchronous FIFO are consistent for the FlexRay data transceiver module and the CPCIe data transceiver module.
10. The FlexRay-CPCIe communication module based on the single chip microcomputer and the FPGA of claim 9, wherein the power module provides a stable power supply for the communication module by using a multi-output DC/DC chip.
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2020
- 2020-11-11 CN CN202011253732.3A patent/CN112347018A/en active Pending
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| CN102360204A (en) * | 2011-08-04 | 2012-02-22 | 南京航空航天大学 | FlexRay-based distributed flight control computer communication system and control method thereof |
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