CN112335048A - 晶体管阵列 - Google Patents

晶体管阵列 Download PDF

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CN112335048A
CN112335048A CN201980043952.2A CN201980043952A CN112335048A CN 112335048 A CN112335048 A CN 112335048A CN 201980043952 A CN201980043952 A CN 201980043952A CN 112335048 A CN112335048 A CN 112335048A
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J·索卡特斯
H·万德克邱武
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Fleck Innabur Technology Co.,Ltd.
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FlexEnable Ltd
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Abstract

一种制造器件的技术，该器件包括限定晶体管阵列的各层的堆叠并且包含在各层级之间的一个或多个导电连接，其中该方法包括：形成源极‑漏极导体图案，该源极‑漏极导体图案限定源极导体阵列和漏极导体阵列，每个源极导体为晶体管阵列的相应晶体管集合提供寻址线，并且每个漏极导体与晶体管阵列的相应晶体管相关联；其中形成所述源极‑漏极导体图案包括：形成第一导体子图案，该第一导体子图案至少在寻址线的区域中包括导体材料，并且至少在其中源极和漏极导体最接近的区域中提供源极‑漏极导体图案的导电表面；在源极导体和漏极导体最接近的区域中掩蔽第一导体子图案；此后形成第二导体子图案，该第二导体子图案至少在寻址线的区域中也包括导体材料，并且在其中要形成与源极‑漏极导体图案的导电层间连接的一个或多个互连区域中提供源极‑漏极导体图案的导电表面；此后在源极导体和漏极导体最接近的区域中对第一导体子图案去掩蔽；以及在源极‑漏极导体图案上方原位对半导体沟道材料层构图。

Description

晶体管阵列
晶体管阵列可以由包括导体层、半导体层和绝缘体层的各层的堆叠来限定。
堆叠的一个重要部分是限定晶体管阵列的源极和漏极导体的源极-漏极导体图案，并且本申请的发明人已经进行了以下研究：(i)改善半导体沟道与源极/漏极导体之间的电荷载流子传输，以及(ii)改善源极-漏极导体图案与堆叠中一个或多个其它层级的导体之间的导电连接。
由此，提供了一种制造器件的方法，该器件包括限定晶体管阵列的各层的堆叠并且包含在各层级之间的一个或多个导电连接，其中该方法包括：形成源极-漏极导体图案，该源极-漏极导体图案限定源极导体阵列和漏极导体阵列，每个源极导体为晶体管阵列的相应晶体管集合提供寻址线，并且每个漏极导体与晶体管阵列的相应晶体管相关联；其中形成所述源极-漏极导体图案包括：形成第一导体子图案，该第一导体子图案至少在寻址线的区域中包括导体材料，并且至少在其中源极和漏极导体最接近的区域中提供源极-漏极导体图案的导电表面；在源极导体和漏极导体最接近的区域中掩蔽第一导体子图案；此后形成第二导体子图案，该第二导体子图案至少在寻址线的区域中也包括导体材料，并且在其中要形成与源极-漏极导体图案的导电层间连接的一个或多个互连区域中提供源极-漏极导体图案的导电表面；此后在源极导体和漏极导体最接近的区域中对第一导体子图案去掩蔽；以及在源极-漏极导体图案上方原位对半导体沟道材料层构图。
根据一个实施例，该方法还包括：在所述一个或多个互连区域中的源极-漏极导体图案上方形成一层或多层，以及对所述一层或多层构图以在所述一个或多个互连区域中暴露所述源极-漏极导体图案；并且其中第一导体子图案的材料在暴露于进行所述一层或多层的所述构图的条件下时表现出比第二导体子图案的材料更高的电导率降低。
根据一个实施例，第二导体子图案的材料在暴露于进行所述一层或多层的所述构图的条件下时基本上不表现出电导率降低。
根据一个实施例，所述条件包括从包含氧的气体产生的等离子体。
根据一个实施例，所述第二导体子图案至少在半导体沟道材料被保留的区域之外的其中第一导体图案包括导体材料的所有区域中包括导体材料。
根据一个实施例，掩蔽第一导体子图案包括在第一导体子图案上原位对抗蚀剂层构图以在区域阵列中形成抗蚀剂岛阵列，并且其中对半导体沟道材料层构图包括形成半导体沟道材料阵列，每个半导体沟道岛基本上以所述区域阵列的相应区域为中心，并且包括相应抗蚀剂岛的形状的放大版本。
根据一个实施例，掩蔽第一导体子图案包括在第一导体子图案上原位对抗蚀剂层构图，并且其中该方法还包括使用相同的光掩模来对所述抗蚀剂层构图和对半导体沟道材料层构图。
下面仅通过示例的方式，参考附图详细描述本发明的实施例，其中：
图1至图6图示了根据本发明的示例实施例的技术的处理流程，其中图1b、图2b、图3b和图4b分别是沿着图1a、图2a、图3a和图4a中的虚线A-A的截面。
为了简明起见，附图集中于薄膜晶体管(TFT)/多像素阵列中的单个晶体管区域/单个像素。产品器件通常将包含大量这样的晶体管区域/像素。
下面描述的实施例是用于顶栅晶体管阵列的示例，但是该技术也适用于其它类型的晶体管阵列。
出于本文档的目的，术语“源极导体”是指驱动器芯片端子和半导体沟道之间电气串联的导体，并且术语“漏极导体”是指经由半导体沟道与驱动器芯片端子电气串联的导体。
半导体沟道材料可以包括一种或多种有机半导体材料(诸如，例如有机聚合物半导体)和/或一种或多种无机半导体材料。
下面描述的实施例使用银合金作为源极-漏极导体图案的一部分。银合金的相对高的功函数(work-function)非常适合于发明人进行的研究工作中使用的特定半导体沟道材料，但是其它导体材料(也包括具有相对低的功函数的导体材料)可能更适合于不同的半导体沟道材料。
下面描述的实施例将导电金属氧化物(铟锡氧化物(ITO))用于源极-漏极导体图案的另一部分，该导电金属氧化物对于用于对本发明人进行的研究工作中使用的特定半导体沟道材料的层构图的蚀刻剂具有足够低的相对蚀刻速率。可以使用其它导体材料，并且其它导体材料可能更适合与其它半导体沟道材料结合使用。
第一步涉及通过气相沉积处理在基板2的工作表面上形成银合金(例如，包含0.5％铟的银合金)的覆盖层(blanket layer)。在这个示例中，基板2包括有机聚合物支撑膜(自支撑塑料膜，例如，聚萘二甲酸乙二醇酯(PEN))、在产品器件中提供遮光功能的构图的导体层以及在表面处的绝缘、平面化层。基板2被临时固定到诸如玻璃板之类的更刚性的载体(未示出)以用于处理基板2(包括下面描述的处理步骤)，并且在处理完成之后被从载体释放。
在沉积银合金层之前，可以沉积一层或多层，诸如用于改善银合金对工件的附着力的一层或多层金属/合金层，从而创建子层的堆叠，这些子层然后被一起构图。在下文中，术语“银合金层”用于表示在上表面具有银合金层的单层或两层或多层的堆叠。然后通过光刻和蚀刻(例如，使用磷酸、乙酸和硝酸的混合物)对银合金层进行构图，以产生银合金子图案6。
接下来，在工件的工作表面上涂覆光致抗蚀剂材料的覆盖层，并且以影响光致抗蚀剂材料的溶解度变化的波长将光致抗蚀剂层暴露于光致抗蚀剂层所需的图案的光学图像。在这个示例中，这是使用光掩模来完成的，该光掩模包括与光致抗蚀剂层所需的图案对应的透射和非透射区域的图案。在光致抗蚀剂层中如此形成潜影的溶解度图像之后，溶解度图像被显影以在银合金子图案6的各部分最接近的沟道区域中形成光致抗蚀剂材料的岛9。
接下来，通过气相沉积技术在工件的工作表面上方(例如，包括在光致抗蚀剂岛9上方)形成ITO的覆盖层，并且通过光刻和蚀刻(使用例如草酸)对其构图以形成ITO子图案11。ITO子图案11在光致抗蚀剂岛9之外的其中银合金子图案6包括导体材料的所有区域中包括ITO。如图3中所示，ITO子图案11在光致抗蚀剂岛9之外的任何地方都基本上与银合金子图案6匹配，但是ITO子图案11的每个导体元素比银合金图案6的对应导体元素稍微更宽(在工件的平面中具有稍微更大的维度)，以便确保在光致抗蚀剂岛9之外的银合金子图案6包括导体材料的所有区域中，银合金图案6由ITO图案11完全覆盖，即使在银合金子图案6和ITO子图案11之间的对准中存在一定程度的误差。
在该ITO构图之后，去除光致抗蚀剂岛9(例如，通过将工件暴露于光致抗蚀剂剥离剂)，以暴露其下方的银合金子图案6。
所得到的源极-漏极导体图案至少限定了(i)源极导体阵列，每个源极导体与相应的晶体管列相关联，并延伸超出阵列的边缘，以连接到驱动器芯片(未示出)的相应端子，以及(ii)漏极导体阵列，每个漏极导体与相应的晶体管相关联。每个源极导体包括延伸超出阵列的边缘以连接到驱动器芯片(未示出)的相应端子(未示出)的寻址线8d；以及用于每个晶体管的一个或多个源极导体指状物8a，该导体指状物8a从寻址线8d分支出。源极导体指状物8a是源极导体中最接近漏极导体的部分。漏极导体包括基本上平行于源极导体指状物8a(例如，与源极导体指状物8a指状交叉)延伸的一个或多个漏极导体指状物8b，该漏极导体指状物8b是漏极导体中最接近源极导体的部分。每个漏极导体还限定了连接到(一个或多个)漏极导体指状物8b的漏极焊盘8c。银合金子图案6在源极和漏极导体最接近的沟道区域中提供源极-漏极导体图案的上表面，并且ITO子图案11在寻址线8a和漏极焊盘8c的区域中提供源极-漏极导体图案的上表面。
通过使用相同的对准标记(未示出)来固定光掩模的位置实现ITO子图案11与银合金子图案6的良好对准，该光掩模在对ITO和银合金层构图的处理中用于对光致抗蚀剂构图。例如，对准标记可以由形成基板2的一部分的上述遮光的导体层限定。
半导体沟道材料(或其前体)的溶液膜被沉积(例如，通过旋涂)在工件上方。在此之前，可以在银合金子图案6的暴露表面上形成改善银合金子图案6与半导体沟道材料之间的电荷传输的一层或多层，诸如，例如合适的有机材料的自组装单层。
在干燥等之后，对所得的半导体沟道材料10的层进行构图以创建半导体沟道材料的隔离岛13阵列，每个岛13为阵列的相应晶体管提供半导体沟道。在这个示例中，使用由包含氧的气体(例如，O2和SF6的气体混合物)产生的等离子体进行有机半导体沟道材料层的构图，这涉及等离子体物质与半导体沟道材料的暴露(未掩蔽)区域的化学反应。但是，本申请的发明人已经发现，由基本上由一种或多种稀有气体(例如，氩气)(并且基本上不包括氧气)组成的气体产生的等离子体也可以用于对有机聚合物半导体沟道材料进行构图。
ITO子导体图案11用于在通过等离子体蚀刻对半导体沟道材料层进行构图的处理期间保护银合金子图案6。
在这个示例中，半导体沟道材料的所得图案13基本上与用于掩蔽银合金子图案的部分的光致抗蚀剂材料的(现已去除的)掩蔽图案9匹配。图案的这种匹配可以通过包括以下的处理来实现：(i)用光致抗蚀剂材料的覆盖层涂覆半导体沟道材料层，并且将与掩蔽银合金子图案6的部分的处理中使用的投影到光致抗蚀剂层上的相同图像投影到光致抗蚀剂层上(这可以通过使用用于对光致抗蚀剂层构图的相同的光掩模，并使用相同的对准参考标记来固定光掩模的位置来完成)；(ii)显影在光致抗蚀剂层中所得的潜影的溶解度图像；以及(iii)将所得的光致抗蚀剂图案用作上述等离子体蚀刻的掩模。允许更大的处理(处理工具)公差的一种变型是使半导体沟道材料岛13稍微大于光致抗蚀剂岛9，使得即使在最大可想到程度的对准误差的情况下，半导体岛13仍然覆盖其中形成光致抗蚀剂岛9的全部区域(从而覆盖银合金子图案6的所有暴露部分)。这种变型涉及使用单独的光掩模来对半导体沟道材料层构图。用于半导体构图的光掩模在基本上以形成抗蚀剂岛9的区域为中心的区域中产生(与用于产生光致抗蚀剂岛9的光掩模)基本相同岛形状的较大图像。
工件的进一步处理继续依次形成：(例如，有机聚合物)栅极介电层(或栅极介电层的堆叠)14；构图的导体层(或导体层的堆叠)16，该导体层16至少限定栅极导体阵列，每个栅极导体与相应的晶体管行相关联，并且每个都延伸超出TFT阵列的边缘以电连接到驱动器芯片(未示出)的相应端子(未示出)；以及在构图的导体层上方的(例如，有机聚合物)绝缘体层(或绝缘体层的堆叠)18。每个晶体管都与栅极和源极导体的唯一组合相关联，从而可以独立于所有其它像素来控制每个像素。
由包含氧O2的气体(例如，O2和六氟化硫SF6的气体混合物)产生的等离子体用于在要形成导电层间连接的区域中创建穿过(一个或多个)绝缘体层18和(一个或多个)栅极介电层14的通孔20，该区域包括将向下形成与每个漏极导体的漏极焊盘8c的导电层间连接的区域。如上所述，ITO子图案11在要形成这种层间连接的区域中提供源极-漏极导体图案的上表面，从而通孔20使ITO子图案11的部分暴露而不暴露银合金子图案6。第一导体子图案的材料在暴露于进行所述一层或多层的所述构图的条件下时表现出比第二导体子图案的材料更高的电导率降低；第二导体子图案在暴露于进行所述一层或多层的所述构图的条件下时基本上不表现出电导率降低。
然后在工件上方形成另一个导体图案，该另一个导体图案限定像素导体阵列22，每个像素导体经由相应的通孔20连接到相应的漏极导体。
不希望受到以下理论的束缚：(i)ITO子图案被认为通过(a)防止在等离子体蚀刻半导体沟道材料层的处理期间银合金子图案6的电导率降级(断裂或氧化)；以及(b)在通过等离子蚀刻创建通孔20的处理期间更好地避免形成非导体(金属氧化物绝缘体)来改善产品器件的性能；以及(ii)在沉积ITO材料之前对银合金子图案的部分进行掩蔽被认为通过更好地避免在源极和漏极导体最接近的沟道区域中银合金子图案6的电荷注入表面的降级来改善产品器件的性能。
除了上面明确提到的任何修改之外，对于本领域技术人员显而易见的是，可以在本发明的范围内对所描述的实施例进行各种其它修改。
申请人在此单独公开了本文描述的每个单独的特征以及两个或更多个这样的特征的任意组合，其程度是使得能够根据本领域技术人员的共同一般知识基于本说明书整体来执行这些特征或组合，不论这些特征或特征组合是否解决本文公开的任何问题，并且不限制请求保护的范围。申请人指出，本发明的各方面可以包括任何这样的单独的特征或特征的组合。

Claims (7)

1.一种制造器件的方法，该器件包括限定晶体管阵列的各层的堆叠并且包含在各层级之间的一个或多个导电连接，其中所述方法包括：形成源极-漏极导体图案，该源极-漏极导体图案限定源极导体阵列和漏极导体阵列，每个源极导体为晶体管阵列的相应晶体管集合提供寻址线，并且每个漏极导体与晶体管阵列的相应晶体管相关联；其中形成所述源极-漏极导体图案包括：
形成第一导体子图案，该第一导体子图案至少在寻址线的区域中包括导体材料，并且至少在其中源极和漏极导体最接近的区域中提供源极-漏极导体图案的导电表面；
在源极导体和漏极导体最接近的区域中掩蔽第一导体子图案；
此后形成第二导体子图案，该第二导体子图案至少在寻址线的区域中也包括导体材料，并且在其中要形成与源极-漏极导体图案的导电层间连接的一个或多个互连区域中提供源极-漏极导体图案的导电表面；
此后在源极导体和漏极导体最接近的区域中对第一导体子图案去掩蔽；以及
在源极-漏极导体图案上方原位对半导体沟道材料层构图。
2.根据权利要求1所述的方法，还包括：在所述一个或多个互连区域中的源极-漏极导体图案上方形成一层或多层，以及对所述一层或多层构图以在所述一个或多个互连区域中暴露所述源极-漏极导体图案；并且其中第一导体子图案的材料在暴露于进行所述一层或多层的所述构图的条件下时表现出比第二导体子图案的材料更高的电导率降低。
3.根据权利要求2所述的方法，其中第二导体子图案的材料在暴露于进行所述一层或多层的所述构图的条件下时基本上不表现出电导率降低。
4.根据权利要求2或权利要求3所述的方法，其中所述条件包括从包含氧的气体产生的等离子体。
5.根据前述权利要求中的任一项所述的方法，其中所述第二导体子图案至少在半导体沟道材料被保留的区域之外的其中第一导体图案包括导体材料的所有区域中包括导体材料。
6.根据前述权利要求中的任一项所述的方法，其中：掩蔽第一导体子图案包括：在第一导体子图案上原位对抗蚀剂层构图以在区域阵列中形成抗蚀剂岛阵列，并且其中对半导体沟道材料层构图包括：形成半导体沟道材料阵列，每个半导体沟道岛基本上以所述区域阵列的相应区域为中心，并且包括相应抗蚀剂岛的形状的放大版本。
7.根据权利要求1至5中的任一项所述的方法，其中：掩蔽第一导体子图案包括：在第一导体子图案上原位对抗蚀剂层构图，并且其中该方法还包括：使用相同的光掩模来对所述抗蚀剂层构图和对半导体沟道材料层构图。
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