CN112310193A - 竖直化合物半导体结构及其制造方法 - Google Patents
竖直化合物半导体结构及其制造方法 Download PDFInfo
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- CN112310193A CN112310193A CN202010754825.8A CN202010754825A CN112310193A CN 112310193 A CN112310193 A CN 112310193A CN 202010754825 A CN202010754825 A CN 202010754825A CN 112310193 A CN112310193 A CN 112310193A
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Abstract
本发明涉及一种竖直化合物半导体结构(100),其具有:衬底(10),具有第一主表面(11)和相对的第二主表面(12);竖直通道开口(13),在第一主表面(11)与第二主表面(12)之间完全延伸穿过衬底(10);以及层堆叠(20),布置在竖直通道开口(13)内。层堆叠(20)包括布置在竖直通道开口(13)内的导电层(31)和布置在竖直通道开口(13)内的化合物半导体层(21)。化合物半导体层(21)包括布置在导电层(31)上并且电流连接到导电层(31)的化合物半导体层。此外,本发明涉及一种用于制造这种竖直化合物半导体结构(100)的方法。
Description
技术领域
本发明涉及一种具有至少一个竖直通道开口和集成在其中的层堆叠的竖直化合物半导体结构,该层堆叠包括至少一个化合物半导体层,并且涉及一种具有这种竖直化合物半导体结构的三维半导体器件以及用于制造这种竖直化合物半导体结构的方法。
背景技术
本发明可以特别有利地用于3D***集成领域。三维集成是通过平面技术制造的器件的竖直连接(机械和电的)。由于电路结构布置在水平的二维平面(也称为水平的主衬底平面)中,因此后者也称为二维或2D***。以常规平面技术制造并相互上下布置的至少两个二维***然后可以竖直连接以形成3D***。这里,竖直方向涉及相应2D***的上述水平二维平面,或者涉及以平面(水平)方式跨过相应衬底延伸的器件结构,例如集成电路或掺杂区,其中竖直方向基本上垂直于水平面。因此,3D***(竖直和水平)可以包括至少两个或更多个竖直地相互上下布置的2D***(水平)。
3D***主要分为两个主要组。在所谓的3D封装中,两个或更多个单独组件(例如芯片或管芯)竖直地相互上下堆叠,并集成在三维布置的封装中。该各个组件通过竖直通孔相互连接。这里,各个芯片的电路未集成在单个公共电路中。各个芯片的电路仍然经由电信号在芯片外部通信,就好像它们安装在印刷电路板上的不同外壳中一样。然而,在所谓的IC(IC=集成电路)中,公共电路的若干组件竖直地相互上下布置,并通过竖直通孔连接到单个公共电路。这意味着3D IC表现得像单个IC。在3D IC中,所有芯片级的所有组件可以相互通信,这取决于所有芯片级的所有组件是如何设计的,竖直设计以及水平设计两者。
出于本公开的目的,如果讨论了三维***集成、3D***或三维半导体器件等,则其总是包括上述两个主要组两者。
其中,三维集成微电子***的优点尤其是,与平面技术中常规制造的二维***相比,使用相同的设计规则可以获得更高的封装密度和开关速度。这些较高的开关速度一方面是由于各个器件或电路之间的导电路径较短,另一方面是由于选择了并行信息处理。
当在可自由选择的位置(在硅的情况下:TSV-硅通孔)处实现穿过衬底的高度集成竖直接触的连接技术时,***的性能增加达到最佳。
其中,专利EP 1171912 B1(通过背接触进行电子器件竖直集成的方法)尤其描述了具有可自由选择的硅通孔的3D集成的现有技术,即所谓的3D IC技术(3D集成手册,第1卷)。
在3D IC集成中,在工艺期间在相应器件中制造硅通孔。在完成所谓的生产线前段制程工艺之后,但是在所谓的生产线后段制程(BEOL)工艺之前,制造TSV是一种很有前途的方法。不利的是,该构思以及其他类似构思要求TSV工艺与半导体制造工艺兼容。
根据现有技术,在平面器件结构之间的不同衬底或衬底平面中实现了竖直集成。在横向方向上,这导致在最小空间内的高集成密度。然而,除了衬底通孔的横向尺寸之外,器件结构及其布线的横向延伸基本上限制了三维集成器件的可获得的集成密度。
发明内容
因此,本发明的一个目的是与常规3D***相比显著增加集成密度,同时基本上保持横向和纵向尺寸。
为了解决该目的,提出了具有根据权利要求1所述的特征的竖直化合物半导体结构以及具有根据权利要求14所述的特征的用于制造竖直化合物半导体结构的方法。在相应从属权利要求中陈述了实施例和其他有利方面。
本发明的竖直化合物半导体结构包括具有第一主表面和相对的第二主表面的衬底。该衬底可以包括例如硅、玻璃或石英。在衬底中设置有在第一主表面与第二主表面之间完全延伸穿过衬底的竖直通道开口。竖直层堆叠布置在该竖直通道开口内。层堆叠在竖直通道开口内竖直延伸。层堆叠包括:导电层,布置在竖直通道开口内并且沿着竖直通道开口的延伸方向布置;以及化合物半导体层,布置在竖直通道开口内并且沿着竖直通道开口的延伸方向布置。化合物半导体层包括布置在导电层上并且电流连接到导电层的化合物半导体。因此,与常规***相比,可以有利地并且显著地增加集成密度。在常规的3D***中,其上布置有平面器件结构的至少两个二维***相互上下堆叠,并且通过竖直通孔相互连接。这里,竖直通孔专门用于二维***的平面器件结构的相互电流连接以及可能的机械连接。然而,在本发明的装置中,作为常规平面器件结构的备选或补充,竖直通孔中可用的空间被附加且最有效地用于在其中集成一个或若干个本文中本发明的竖直器件结构。这里,特别有利的是,具有至少一种化合物半导体的半导体器件结构可以集成在竖直通孔(通道开口)中。这里,在可以生成竖直通孔的通道开口中生成上述竖直层堆叠。层堆叠包括可以从外部接触的导电层。这可以优选为金属化层。此外,层堆叠包括化合物半导体层,该化合物半导体层包括优选地直接且正好布置在导电层上并且电流连接到导电层的化合物半导体。在现有技术中,这种半导体器件结构主要以硅技术制造,即,不使用化合物半导体,而是使用元素半导体。在硅的情况下,目前最多可以在金属化层上沉积多晶硅,因为要生成单晶硅,必须在工艺控制期间进行高于硅熔化温度的加热,然而这将导致破坏底层,例如金属化层。然而,在本发明的具有化合物半导体的层堆叠的生成中,导电层(例如金属化层)保持完整。可以从外部接触导电层,并且因此导电层可以跨过其整个表面将电荷载流子发射到化合物半导体层,使得化合物半导体层被完全接触。利用该发明的层堆叠,可以生成竖直化合物半导体层结构,其布置或集成在通孔的竖直通道开口内,并且仍然可以被完全接触。基于这些情况,由于3D***现在不仅可以包括布置在平面中的器件结构,而且还可以包括竖直集成的器件结构,因此可以显著地增加3D***的集成密度。
根据实施例,化合物半导体层可以包括单晶化合物半导体。与多晶结构相比,单晶化合物半导体具有特别好的电特性。因此,在常规的基于硅的方法中,优先使用单晶硅。然而,如上所述,由于可用的工艺,至多多晶硅可以直接沉积在导电层上,并且特别是在金属化层上。本文所述的发明允许将单晶化合物半导体材料直接设置在导电层上。或多或少复杂的化学化合物的单晶体也是单晶化合物半导体材料的一部分。
根据另一实施例,化合物半导体层可以包括至少一种2D复合材料。该2D复合材料不得与本文也描述的2D***混合。2D材料(有时也称为单层或单层材料)是仅包括单个原子层的晶体材料。若干个这些单层可以相互上下堆叠。2D材料具有以单晶方式沉积或实现2D材料的特性。由于不寻常的特性,因此2D材料是广泛(基础)研究的主题。通常,2D材料可以被视为不同元素的二维同素异形体,或者也可以被视为具有共价键的不同元素的化合物,即所谓的2D复合材料。同素异形2D材料的已知代表是例如石墨烯。作为2D复合材料的非限制性和非穷举性示例,可以陈述石墨烯、硼氮化物、磷化锗和硫化钼(IV)。在下文中,将特别考虑不同元素的化合物(即2D复合材料),并且这里将特别考虑化合物半导体。2D材料在3D***中的高效集成仍然是一个极端的挑战,也是***整体性能和电路设计中的一个限制因素。
根据另一实施方式,化合物半导体层可以包括过渡金属二硫化物组中的至少一种材料。过渡金属二硫化物也称为TMD。TMD通常由三个原子平面构造,并且大多包括两种不同的原子种类,即一个金属和两个硫族化物。过渡金属二硫化物,也称为TMD单层,是MX2型的原子薄半导体,其中M指过渡金属原子(例如Mo、W等),并且X指a硫族化物原子(例如S、Se或Te)。这里,通常,一层M原子布置在两层X原子之间。这些布置是2D材料上级组的一部分。TMD单层,例如MoS2、WS2、MoSe2、WSe2、MoTe2,具有直接带隙,其表征为它们用作本发明化合物半导体层中的化合物半导体。
根据另一实施例,化合物半导体层可以包括二硫化钼MoS2。由于其电特性,二硫化钼特别很好地适合用作本发明的化合物半导体层中的化合物半导体。此外,MoS2单层的厚度仅为这就是MoS2特别很好地适合集成到竖直通道开口中的原因。
根据另一实施方式,化合物半导体层可以通过沉积布置在导电层上。这里,化合物半导体层可以直接沉积在导电层例如金属化层上。沉积化合物半导体材料为将化合物半导体层布置在导电层上提供了简单并且相对成本效益好的选择。
根据备选实施例,化合物半导体层可以通过化学转化由导电层的至少一部分形成。备选地或附加地,化合物半导体层可以通过化学转化由沉积在导电层上的另一层(例如,金属化层)的至少一部分形成。化学转化意指与上述沉积方法不同的新颖方法。在化学转化中,输出层的部分通过化学反应转化为化合物半导体层。导电层或另一层可以用作输出层。输出层优选是金属化层,并且特别是过渡金属,例如钼。可以通过合适的反应伙伴如硫将输出层转化。在这种化学转化中,化合物半导体层由包括TMD单层的2D材料形成,在这种情况下为MoS2。
根据另一实施例,层堆叠可以包括布置在竖直通道开口内并且沿着竖直通道开口的延伸方向布置的第二化合物半导体层,该第二化合物半导体层布置在化合物半导体层上并且与其电流连接。这里,第二化合物半导体层布置在化合物半导体层的与导电层相对的一侧上,使得化合物半导体层布置在导电层与第二化合物半导体层之间。通过这种布置,例如,可以在竖直通道开口内生成二极管结构。
根据另一实施例,第二化合物半导体层可以包括至少一种2D复合材料。因此,与上述(第一)化合物半导体层一样,第二化合物半导体层可以包括例如过渡金属二硫化物组中的至少一种材料,并且特别是MOS2。
根据另一些实施例,层堆叠可以包括布置在竖直通道开口内(并且沿着竖直通道开口的延伸方向布置)的第三化合物半导体层,该第三化合物半导体层布置在第二化合物半导体层上并且与其电流连接。这里,第三化合物半导体层布置在第二化合物半导体层的与化合物半导体层相对的一侧上,使得第二化合物半导体层布置在化合物半导体层与第三化合物半导体层之间。通过这种布置,例如,可以在竖直通道开口内生成晶体管结构。
根据另一实施例,第三化合物半导体层可以至少包括2D复合材料。因此,和上述(第一)化合物半导体层和/或第二化合物半导体层一样,第三化合物半导体层可以包括例如过渡金属二硫化物组中的至少一种材料,并且特别是MOS2。
根据另一实施例,层堆叠可以包括布置在竖直通道开口内并且沿着竖直通道开口的延伸方向布置的第二导电层,该第二导电层布置在第三化合物半导体层上并且与其电连接。这里,第二导电层布置在第三化合物半导体层的与第二化合物半导体层相对的一侧上,使得第三化合物半导体层布置在第二化合物半导体层与第二导电层之间。可以从外部接触该第二导电层,并且因此该第二导电层可以跨过其整个表面将电荷载流子发射到第三化合物半导体层,使得第三化合物半导体层完全接触。
可以利用竖直化合物半导体结构来制造三维电子半导体器件(3D***),其中,与衬底的第一主表面和/或第二主表面相对地布置有附加的分离的电子器件结构,该附加的分离的电子器件结构通过接触部分机械连接和/或电流连接到竖直化合物半导体结构并且特别是机械连接和/或电流连接到化合物半导体层。附加的分离的电子器件结构可以例如是在平面技术中制造的二维***或另一本发明的竖直化合物半导体结构。以这种方式制造的3D***可以是3D封装或3D IC。
此外,本发明涉及一种用于制造相应的竖直化合物半导体结构的方法。该方法包括:提供具有第一主表面和相对的第二主表面的衬底,以及构造在第一主表面与第二主表面之间完全延伸穿过衬底的竖直通道开口。根据本发明,在竖直通道开口内生成层堆叠。生成层堆叠的步骤包括:在竖直通道开口内并且沿着竖直通道开口的延伸方向布置导电层;以及在竖直通道开口内并且沿着竖直通道开口的延伸方向布置化合物半导体层,该化合物半导体层包括至少一种化合物半导体。这里,化合物半导体层布置在导电层上并且电流连接到导电层。关于该方法的优点,参考关于相应装置的以上陈述。
附图说明
一些实施例在下面附图中示例性地示出,并将在下面讨论。在附图中:
图1是根据实施例的竖直化合物半导体结构的示意性横截面图;
图2是示出了根据实施例的用于制造竖直化合物半导体结构的方法的各个方法步骤的示意性框图;
图3A是根据实施例的竖直化合物半导体结构的示意性横截面图;
图3B是图3A的竖直化合物半导体结构的顶视图;
图4是根据实施例的用于制造三维电子半导体元件的具有到分离的电子器件结构的连接结构(布线和控制)的竖直化合物半导体结构的示意性横截面图;以及
图5是根据另一实施例的用于制造三维电子半导体元件的具有到分离的电子器件结构的连接结构(布线和控制)的竖直化合物半导体结构的示意性横截面图。
具体实施方式
在下文中,将参考附图更详细地描述实施例,其中具有相同或类似功能的元件具有相同的附图标记。
框图中示出的方法步骤以及参考框图讨论的方法步骤也可以按照所示或所描述的顺序以任何其他方式执行。此外,与装置的特定特征相关的方法步骤可以与装置的该特征恰好互换,反之亦然。
图1示出了本发明的竖直化合物半导体结构100的示意性横截面图。竖直化合物半导体结构100包括具有主表面11和相对的第二主表面12的衬底10。
竖直通道开口13在第一主表面11与第二主表面12之间完全延伸穿过衬底10。层堆叠20布置在竖直通道开口13内。
层堆叠20包括导电层31。导电层31可以是例如金属化层,并且特别是包括过渡金属的层。导电层31布置在竖直通道开口13内。例如,导电层31可以布置(例如沉积)在竖直通道开口13的横向圆周壁上。例如衬底10不导电时,导电层31可以直接且正好布置在竖直通道开口13的壁上。可选地,例如当衬底10具有导电特性时,隔离层33(图3A)(例如电介质)可以设置在导电层31与竖直通道开口13的壁之间。导电层31可以沿着竖直通道开口13的延伸方向延伸。此外,导电层31可以部分地或如图所示完全布置在竖直通道开口13内。
此外,层堆叠20包括化合物半导体层21。化合物半导体层21布置在竖直通道开口13内。化合物半导体层21可以沿着竖直通道开口13的延伸方向延伸。化合物半导体层21可以部分地或如图所示完全布置在竖直通道开口13内。化合物半导体层21可以直接且正好布置在导电层31上。在径向方向上,化合物半导体层21可以布置成比导电层31更靠近竖直通道开口13的中心40。这意味着化合物半导体层21可以比导电层31更向内侧地布置在竖直通道开口13内。然而,这种布置反之亦然也是可能的,这意味着导电层31将比化合物半导体层21更向内侧地布置。
化合物半导体层21和导电层31可以具有相同的层厚度。然而,不同的层厚度是可能的。例如,化合物半导体层可以具有比导电层31低的层厚度。其中,这可能是尤其由于导电层31用于在很大程度上并且优选地完全与化合物半导体层21接触的事实。另一方面,化合物半导体层21可以优选地被配置为单晶2D材料,其仅包括一个或若干(例如,二至五个)单独的原子层,并且因此非常薄。
根据本发明,化合物半导体层21包括布置在导电层31上并且电流连接到导电层31的化合物半导体。根据定义,化合物半导体层将与元素半导体区分开。虽然元素半导体由单个元素例如硅组成,但是化合物半导体由若干元素组成。
除此之外,当化合物半导体为单晶时是有利的。然而,例如,元素半导体硅不能以单晶方式沉积在导电层上,因为为此必须在工艺期间将沉积温度增加至高于或超过硅的熔融温度,这实际上会导致损坏周围的构件和组件。
因此,根据实施例,化合物半导体层21可以包括所谓的2D材料。为了更准确地定义2D材料,参考上述一般说明部分中的段落。2D材料具有特性,并且因此具有可以以单晶方式将其布置在导电层31上的优点。这里,2D材料形成在分子水平上由单独的原子层(所谓的单层)组成的层。2D材料可以包括单个原子层,也可以将若干原子层组合为常见的2D复合材料。
有利地,化合物半导体层21可以包括过渡金属二硫化物组中的至少一种材料。化合物半导体层21可以包括例如2D复合材料,该2D复合材料具有过渡金属二硫化物组中的至少一种材料。过渡金属二硫化物是MX2型的原子薄半导体,其中M指过渡金属原子(例如Mo、W等),并且X指硫族化物原子(例如S、Se或Te)。这里,通常,一层M原子布置在两层X原子之间。例如,其中一部分是MoS2、WS2、MoSe2、WSe2、MoTe2,其很好地适合在化合物半导体层21中使用。
图2示出了用于制造本文所述的竖直化合物半导体结构100的本发明方法的框图。
在框201中,提供了具有第一主表面11和相对的第二主表面12的衬底10。
在框202中,在主表面11与第二主表面12之间完全延伸穿过衬底10的竖直通道开口13被构造进衬底10中。
在框203中,在竖直通道开口13内生成层堆叠20。
在框203a中,为了生成层堆叠20,在第一步骤中将导电层31布置在竖直通道开口13内。
在框203b中,为了生成层堆叠20,在第二步骤中将包括至少一种化合物半导体的化合物半导体层21布置在竖直通道开口13内,其中,化合物半导体层21布置在导电层31上并且电连接到导电层31。化合物半导体层21可以直接或正好布置在导电层31上。
当以所述顺序执行步骤203a和步骤203b时,这产生层堆叠20,其中导电层31布置在化合物半导体层21与衬底10之间。可选地,隔离层33(图3A)可以附加地布置在衬底10与导电层31之间。
步骤203a和步骤203b也可以反过来执行。在那种情况下,将产生层堆叠20,其中化合物半导体层21布置在导电层31与衬底10之间。可选地,附加地,隔离层33(图3A)可以布置在衬底10与化合物半导体层21之间。
通常,适用于本文所述的所有方法步骤也可以以不同于所述顺序的另一顺序执行。
创造性地,化合物半导体层21可以以两种不同的方式布置在导电层31上。在第一实施例中,化合物半导体层21可以沉积在导电层31上。用于沉积例如单晶2D材料的温度可以显著地低于用于沉积单晶硅的温度。从而,可以确保工艺兼容性。
在第二实施例中,化合物半导体层21可以通过化学转化形成。为此,导电层31的一部分可以通过合适的反应伙伴被转换或转化为化合物半导体层21。导电层31可以包括例如过渡金属(例如钼)组的材料。用于转化的合适的反应伙伴将是例如硫。硫与钼组合生成二硫化钼(IV)MoS2,其直接作为单晶2D复合材料存在,或在转化后作为单层存在。
备选地,代替转化导电层31的一部分,可以在导电层31上布置诸如金属的合适材料。这里,再次,过渡金属组的材料可以布置在导电层31上。利用合适的反应伙伴,例如硫,可以将该附加材料层转换或转化为化合物半导体层21。
与沉积相比,化学转化的优点在于,导电层31和化合物半导体层21的相应层厚度在化学转化中比在沉积中可以低得多。在沉积期间,化合物半导体层21作为附加材料沉积在导电层31上,即,层堆叠20的整体层厚度由导电层31的层厚度加上布置在其上的化合物半导体层21的层厚度组成。然而,在化学转化中,导电层31至少部分地转换或转化为化合物半导体层21。因此,这里,层堆叠21的整体层厚度仅由原始导电层31的层厚度组成。
图3A和图3B示出了竖直化合物半导体结构100的另一实施例。本文所示的竖直化合物半导体结构100包括具有若干层的层堆叠20。图3A示出了横截面图,并且图3B示出了顶视图。
在该实施例中,层堆叠20包括导电层31。例如衬底10具有不导电特性时,导电层31可以直接且正好布置在衬底10上。可选地,例如,当衬底10具有导电特性时,隔离层33(电介质)可以布置在衬底10与导电层31之间。
此外,衬底堆叠20可以包括第二化合物半导体层22,该第二化合物半导体层22布置在竖直通道开口13内并且沿竖直通道开口13的延伸方向22布置。第二化合物半导体层22可以布置在上述化合物半导体层21(在具有若干层的层堆叠20中也可以称为第一化合物半导体层21)上,并且可以与其电流连接。
这里,第二化合物半导体层22可以布置在第一化合物半导体层21的与导电层31相对的一侧上,使得第一化合物半导体层21布置在导电层31与第二化合物半导体层22之间。因此,第一化合物半导体层21可以在径向上比第二化合物半导体层22更向外侧地布置在竖直通道开口13内。此外,导电层31可以在径向上比第一化合物半导体层21和第二化合物半导体层22更向外侧地布置在竖直通道开口13内。第二化合物半导体层22可以直接或正好布置在第一化合物半导体层21上。
第二化合物半导体层22还可以包括以上参考第一化合物半导体层21所述的材料中的一种,例如,2D复合材料并且特别是过渡金属二硫化物组的材料,例如MOS2。如以上参考第一化合物半导体层21所述,第二化合物半导体层22也可以通过沉积或通过化学转化布置在第一化合物半导体层21上。为了化学转化,例如,可以在第一化合物半导体层21上预先沉积合适的附加材料,例如金属或过渡金属,然后可以通过化学转化将附加材料转换或转化为第二化合物半导体层22。
在图3A和图3B中,示出了另一些层。只要层堆叠20至少包括第一化合物半导体层21和第二化合物半导体层22,就可以将本发明的竖直化合物半导体结构100实现为布置在竖直通道开口13内的二极管结构。
此外,衬底堆叠20可以包括第三化合物半导体层23,该第三化合物半导体层23布置在竖直通道开口13内并且沿着竖直通道开口13的延伸方向布置。第三化合物半导体层23可以布置在上述第二化合物半导体层22上,并且可以与其电流连接。
这里,第三化合物半导体层23可以布置在第二化合物半导体层22的与第一化合物半导体层21相对的一侧上,使得第二化合物半导体层22布置在第一化合物半导体层21与第三化合物半导体层23之间。因此,第二化合物半导体层22可以在径向上比第三化合物半导体层23更向外侧地布置在竖直通道开口13内。此外,第一化合物半导体层21可以在径向上比第二化合物半导体层22以及第三化合物半导体层23更向外侧地布置在竖直通道开口13内。第三化合物半导体层23可以直接或正好布置在第二化合物半导体层22上。
第三化合物半导体层23还可以包括上述相对于第一化合物半导体层21的材料中的一种,例如,2D复合材料并且特别是过渡金属二硫化物组的材料,例如MOS2。如以上参考第一化合物半导体层21所述,第三化合物半导体层23也可以通过沉积或通过化学转化布置在第二化合物半导体层22上。为了化学转化,例如可以在第二化合物半导体层22上预先沉积合适的附加材料,例如金属或过渡金属,然后可以通过化学转化将附加材料转换或转化为第三化合物半导体层23。
只要层堆叠20包括图3A和图3B所示的化合物半导体层,即第一化合物半导体层21、第二化合物半导体层22以及第三化合物半导体层23,就可以将本发明的竖直化合物半导体层结构100实现为布置在竖直通道开口13内的晶体管结构。更准确地,这是一个竖直偶极晶体管。
从图3A和图3B中可以看出,导电层31和布置在其上的第一化合物半导体层21可以沿着基本上圆柱状的通道开口13的延伸方向延伸。因此,这适用于布置在竖直通道开口13内的所有层,例如上述第二化合物半导体层22和第三化合物半导体层23。
布置在竖直通道开口13内的一个或多个层21、22、23、31、32或整个层堆叠20可以沿竖直方向在衬底10的第一主表面11与衬底10的第二主表面12之间完全延伸。还可能的是,层堆叠20的一层或若干层沿竖直方向在衬底10的第一主表面11与衬底10的第二主表面12之间仅部分地延伸。
布置在竖直通道开口13内的层21、22、23、31、32中的每一层可以被配置为空心圆柱体的形式。因此,如在图3B所示的顶视图中所见,层堆叠20包括配置为空心圆柱体形状的若干层21、22、23、31、32,其可以沿径向方向彼此堆叠。
至少沿径向方向的层堆叠20的最外层(在该示例中为隔离层33)可以直接且正好布置在圆柱状竖直通道开口13的横向圆周壁上。然后,其他层可以沿径向方向相继向内跟随朝向通道开口13的中心40。
这意味着层堆叠20可以包括被配置为空心圆柱体形状的导电层31作为第一层。作为第二层,层堆叠20可以包括被配置为空心圆柱体形状的第一化合物半导体层21,该第一化合物半导体层21沿径向方向布置在被配置为空心圆柱体形状的导电层31内。作为第三层,层堆叠20可以包括被配置为空心圆柱体形状的第二化合物半导体层22,该第二化合物半导体层22沿径向方向布置在被配置为空心圆柱体形状的第一化合物半导体层21内。作为第四层,层堆叠20可以包括被配置为空心圆柱体形状的第三化合物半导体层23,该第三化合物半导体层23沿径向方向布置在被配置为空心圆柱体形状的第二化合物半导体层22内。
还可能的是,其他层(例如金属化层)被布置在各个层21、22、23、31、33之间。
因此,整个层堆叠20可以被配置为包括一层或若干层的空心圆柱体的形式,使得通道开口13的原始直径D(图3A)由于层堆叠20的层厚度(将沿径向方向测量)而减小。包括层堆叠20的通道开口13的经减小的直径由附图标记d指示。
因此,层堆叠20可以称为竖直层堆叠。层堆叠20包括可以沿径向方向彼此向内堆叠的若干层。这里,整个层堆叠20相对于竖直通道开口13沿轴向方向延伸,即,沿竖直通道开口13的延伸方向延伸。
如上所述,可以将本发明的竖直化合物半导体结构100实现为布置在竖直通道开口13内的二极管结构或晶体管结构。
图4示出了被配置为晶体管的本发明的竖直化合物半导体结构100的实施例。这可以是竖直双极型晶体管。该实施例基本上与以上参考图3A和图3B讨论的实施例相对应,这就是下面仅讨论差异的原因。
第一化合物半导体21、第二化合物半导体22和第三化合物半导体层23可以各自分别接触。在图4所示的实施例中,第二化合物半导体层22和第三化合物半导体层23可以例如通过直接连接的电导体42、43或引线直接接触。
第一化合物半导体层21可以例如经由导电层31间接地接触。在那种情况下,可以以非接触方式配置第一化合物半导体层21,即第一化合物半导体层21不具有直接接触或连接。然而,导电层31可以例如通过直接连接的电导体41直接接触。因此,导电层31接触并跨过大的表面优选地完全地向第一化合物半导体层21发射其电荷载流子。因此,导电层31也可以称为用于连接非接触化合物半导体层21的连接层。
彼此布置的三个化合物半导体层21、22、23可以形成三个交替的pn结以实现晶体管结构。取决于连接类型,例如,第一化合物半导体层21可以提供竖直双极型晶体管100的发射极层。第二化合物半导体层22可以提供竖直双极型晶体管100的基极层。第三化合物半导体层23可以提供竖直双极型晶体管100的集电极层。发射极层和集电极层也可以互换。通常,发射极层将具有比基极层更高的电荷载流子密度,并且基极层又将具有比集电极层更高的电荷载流子密度。
在图4中,被配置为晶体管结构的本发明的竖直化合物半导体结构100被示为3D***1000的一部分。为此,本发明的竖直化合物半导体层结构100沿竖直方向连接到附加的分离的电子器件结构101。这里,竖直通道开口13可以用作竖直通孔,以便电流连接布置在3D半导体器件1000中的器件结构100、101。
如图所示,附加的分离的电子器件结构101可以与衬底10的第二主表面12相对地布置。备选地或附加地,附加的分离的电子器件结构101或另一(未示出)附加的分离的电子器件结构可以与衬底10的第一主表面11相对地布置。
在图4中,示例性地与衬底10的第二主表面12相对布置的附加的分离的电子器件结构101本身可以是本文所述的本发明的竖直化合物半导体结构100。备选地,附加的分离的电子器件结构101可以是如图4所示的以平面技术制造的2D***。附加的分离的电子器件结构101可以包括例如IC,该IC又与本发明的竖直化合物半导体结构100的电路结构合作以形成3D IC。备选地,附加的分离的电子器件结构101可以包括分离的器件,例如与本发明的竖直化合物半导体结构100一起形成3D封装的芯片。
本发明的竖直化合物半导体结构100和附加的分离的电子器件结构101可以通过接触部分110彼此电流连接以及也可能的机械连接。该连接例如可以通过所谓的金属间化合物(IMC)连接方法来实现。接触部分110可以包括例如一个或若干个金属焊盘111a。附加的分离的电子器件结构101本身也可以包括一个或若干个金属焊盘111b。接触焊盘112可以布置在金属焊盘111a、111b之间,以将金属焊盘111a、111b彼此电流连接和/或机械连接。金属焊盘111a、111b可以例如包括铜,并且接触焊盘112可以包括例如铜和/或锡。
如图4所示,附加的分离的电子器件结构101可以包括例如具有集成金属化层114的衬底113。金属化层114可以通过接触部分110电流连接到本发明的竖直化合物半导体结构100并且特别是电流连接到化合物半导体层21。
在图4所示的实施例中,接触部分110布置在衬底10的第二主表面12与附加的分离的电子器件结构101之间。备选地或附加地,可以通过合适的接触部分110将附加的分离的电子器件结构101或另一附加的分离的电子器件结构(未示出)与衬底10的第一主表面11相对地布置。在那种情况下,本发明的竖直化合物半导体结构100将布置在两个附加的分离的电子器件结构之间,使得作为结果形成了三维电子半导体器件1000(例如3D IC或3D封装)。
图5示出了作为三维电子半导体器件1000的一部分的本发明的竖直化合物半导体结构100的另一实施例。该实施例基本上与以上参考图4讨论的实施例相对应,这就是下面仅讨论差异的原因。
在图5所示的实施例中,层堆叠20包括第二导电层32。该第二导电层32布置在竖直通道开口13内并且沿竖直通道开口13的延伸方向布置。针对该第二导电层32,以上参照图3A和图3B中讨论的层说明的所有内容相应地适用。
第二导电层32可以布置在第三化合物半导体层23上并且与其电流连接。第二导电层32可以布置在第三化合物半导体层23的与第二化合物半导体层22相对的一侧上,并且可以形成径向内层。这意味着第二导电层32可以形成层堆叠20的最内层,即,沿径向方向最靠近通道开口13的中心40的层。因此,在该布置中,第二导电层32可以布置在第三化合物半导体层23的与第二化合物半导体层22相对的一侧上,使得第三化合物半导体层23布置在第二化合物半导体层22与第二导电层32之间。
第二导电层32允许第三化合物半导体层23的完全接触。因此,第二导电层32也可以称为用于连接第三化合物半导体层23的连接层。
这意味着第一化合物半导体层21以及第二化合物半导体层22仍将例如通过电导体41、42直接接触。然而,第三化合物半导体层23将不直接接触。备选地,第二导电层32可以例如通过电导体44直接接触,并且第三化合物半导体层23可以又经由第二导电层32间接接触。
以上陈述适用于具有图5所示的三个化合物半导体层21、22、23的晶体管结构的情况。只要将本发明的化合物半导体结构100配置为包括两个化合物半导体层21、22的二极管结构,则所有以上陈述相应地适用,其中第二化合物半导体层22将代替上述第三化合物半导体层23。这意味着第二导电层32可以相应地布置在第二化合物半导体层22上。
第二导电层32可以分别直接且正好布置在第二化合物半导体层22上和第三化合物半导体层23上。
尽管已经在本发明的竖直化合物半导体结构100的上下文中描述了以上方面,但是应当清楚的是,这些方面也表示对用于制造本发明的竖直化合物半导体结构100的相应方法的描述,使得装置的块或器件也可以被认为是相应的方法步骤或方法步骤的特征。类似地,在方法步骤的上下文中或作为方法步骤描述的方面也表示对相应装置的相应块或细节或者特征的描述。
在下文中,换言之,将再次简要概述本发明:
本发明尤其涉及一种用于制造三维电子***1000并且特别是三维集成电路的方法。三维集成意味着器件的竖直连接(机械和电的)。其中,三维集成电子***1000的优点是与二维***(平面技术)相比可以获得更高的封装密度和开关速度(由于较短的传导路径)。
本发明的方法实现了一个衬底10的衬底通孔13中的竖直化合物半导体21、22、23与另一衬底的器件101的三维连接,因此允许三维集成器件***1000的集成密度的显著增加。相对于衬底10,衬底通孔13可以是电绝缘通孔(TSV-衬底通孔)。
本发明尤其涉及一种用于制造三维电子***1000的方法,其中,首先,在衬底10中生成具有相对于衬底10是电绝缘的可选层33的竖直通道开口13。然后,可以在通道开口13的竖直侧壁中生成导电层31。这之后可以生成以导电方式连接到导电层31的第一半导体层22,以及生成以导电方式连接到第一半导体层21的第二半导体层22和生成以导电方式连接到第二半导体层22的第三半导体层23,其中,半导体层21、22、23中的至少一个被配置为化合物半导体。
可以经由结构110实现导电连接和(在不限制一般性的情况下)机械连接到底部衬底/器件101,并且这里,在不限制一般性的情况下,可以通过金属间化合物(IMC)连接方法来生成导电连接和机械连接。
因此,本发明的方法实现了一个衬底10的衬底通孔13中的竖直化合物半导体100与另一衬底的器件101的三维连接,并且因此允许高度密集的集成器件***1000。
根据本发明的一个方面,提出了一种用于连接至少两个电子组件的方法,该方法包括:
提供衬底10,
生成穿过衬底10的竖直通道开口13,
在竖直通道开口13的竖直侧壁上生成相对于衬底10是电绝缘的层33,
在电绝缘层33上生成导电层31,
生成以导电方式连接到导电层31的第一半导体层21,
生成以导电方式连接到第一半导体层21的第二半导体层22,
生成以导电方式连接到第二半导体层22的第三半导体层23,以及
生成装置110,用于将层堆叠20以导电方式连接到至少一个器件结构101,
其中,半导体层21、22或23中的至少一个被配置为化合物半导体层。
根据另一方面,通过沉积生成化合物半导体层21、22、23中的至少一个。
根据另一方面,通过化学反应局部地生成化合物半导体层21、22、23中的至少一个。
根据另一方面,附加地,生成以导电方式连接到第三半导体层23的导电层32。
此外,提出了一种竖直化合物半导体结构100,在下文中也称为微电子连接器件,其包括:
衬底10,
穿过衬底10的竖直通道开口13,
在竖直通道开口13的竖直侧壁上的层33,其相对于衬底10是电绝缘的,
电绝缘层33上的导电层31,
以导电方式连接到导电层31的第一半导体层21,
以导电方式连接到第一半导体层21的第二半导体层22,
以导电方式连接到第二半导体层22的第三半导体层23,
装置110,用于以导电方式将层堆叠20连接到至少一个器件结构101,
其中,半导体层21、22、23中的至少一个被配置为化合物半导体层。
上述实施例对于本发明的原理仅是说明性的。应当理解的是,本文所述的布置和细节的修改和变形对于本领域其他技术人员将是显而易见的。因此,旨在仅由所附专利权利要求的范围而不由通过描述和解释本文的实施例的方式给出的具体细节来限制本发明。
Claims (26)
1.一种竖直化合物半导体结构(100),包括:
衬底(10),具有第一主表面(11)和相对的第二主表面(12),
竖直通道开口(13),在所述第一主表面(11)与所述第二主表面(12)之间完全延伸穿过所述衬底(10),
层堆叠(20),布置在所述竖直通道开口(13)内,
其中,所述层堆叠(20)包括布置在所述竖直通道开口(13)内的导电层(31)和布置在所述竖直通道开口(13)内的化合物半导体层(21),
其中,所述化合物半导体层(21)包括布置在所述导电层(31)上并且电流连接到所述导电层(31)的化合物半导体。
2.根据权利要求1所述的竖直化合物半导体结构(100),
其中,所述化合物半导体层(21)包括单晶化合物半导体。
3.根据权利要求1所述的竖直化合物半导体结构(100),
其中,所述化合物半导体层(21)包括至少一种2D复合材料。
4.根据权利要求1所述的竖直化合物半导体结构(100),
其中,所述化合物半导体层(21)包括过渡金属组和硫族化物组中的至少一种元素组合。
5.根据权利要求1所述的竖直化合物半导体结构(100),
其中,所述导电层(31)在所述竖直通道开口(13)内直接且正好布置在所述衬底(10)上,或者
其中,隔离层(33)在所述竖直通道开口(13)内布置在所述衬底(10)与所述导电层(31)之间。
6.根据权利要求1所述的竖直化合物半导体结构(100),
其中,所述化合物半导体层(21)通过沉积布置在所述导电层(31)上。
7.根据权利要求1所述的竖直化合物半导体结构(100),
其中,所述化合物半导体层(21)由所述导电层(31)的至少一部分通过化学转化形成。
8.根据权利要求1所述的竖直化合物半导体结构(100),
其中,所述层堆叠(20)包括布置在所述竖直通道开口(13)内的第二化合物半导体层(22),所述第二化合物半导体层(22)布置在所述化合物半导体层(21)上并与其电流连接,
其中,所述第二化合物半导体层(22)布置在所述化合物半导体层(21)的与所述导电层(31)相对的一侧上,使得所述化合物半导体层(21)布置在所述导电层(31)与所述第二化合物半导体层(22)之间。
9.根据权利要求8所述的竖直化合物半导体结构(100),
其中,所述第二化合物半导体层(22)包括至少一种2D复合材料。
10.根据权利要求8所述的竖直化合物半导体结构(100),
其中,所述层堆叠(20)包括布置在所述竖直通道开口(13)内的第三化合物半导体层(23),所述第三化合物半导体层(23)布置在所述第二化合物半导体层(22)上并与其电流连接,
其中,所述第三化合物半导体层(23)布置在所述第二化合物半导体层(22)的与所述化合物半导体层(21)相对的一侧上,使得所述第二化合物半导体层(22)布置在所述化合物半导体层(21)与所述第三化合物半导体层(23)之间。
11.根据权利要求10所述的竖直化合物半导体结构(100),
其中,所述第三化合物半导体层(23)包括至少一种2D复合材料。
12.根据权利要求10所述的竖直化合物半导体结构(100),
其中,所述层堆叠(20)包括布置在所述竖直通道开口(13)内的第二导电层(32),所述第二导电层(32)布置在所述第三化合物半导体层(23)上并与其电流连接,
其中,所述第二导电层(32)布置在所述第三化合物半导体层(23)的与所述第二化合物半导体层(22)相对的一侧上,使得所述第三化合物半导体层(23)布置在所述第二化合物半导体层(22)与所述第二导电层(23)之间。
13.三维电子半导体器件(1000),包括至少一个根据权利要求1所述的竖直化合物半导体结构(100),
其中,附加的分离的电子器件结构(101)与所述衬底(10)的所述第一主表面(11)和/或所述第二主表面(12)相对地布置,所述附加的分离的电子器件结构(101)通过接触部分(110)机械连接和/或电流连接到所述竖直化合物半导体结构(100)。
14.一种用于制造竖直化合物半导体结构(100)的方法,所述方法包括:
提供(201)具有第一主表面(11)和相对的第二主表面(12)的衬底(10),
构造(202)在所述第一主表面(11)与所述第二主表面(12)之间完全延伸穿过所述衬底(10)的竖直通道开口(13),
在所述竖直通道开口(13)内生成(203)层堆叠(20),生成所述层堆叠(20)的步骤包括:
在所述竖直通道开口(13)内布置(203a)导电层(31),以及
在所述竖直通道开口(13)内布置(203b)化合物半导体层(21),
其中,所述化合物半导体层(21)布置在所述导电层(31)上并且电流连接到所述导电层(31)。
15.根据权利要求14所述的方法,
其中,布置所述化合物半导体层(21)的步骤(203b)包括将单晶化合物半导体布置在所述导电层(31)上。
16.根据权利要求14所述的方法,
其中,布置所述化合物半导体层(21)的步骤(203b)包括将至少一种2D复合材料布置在所述导电层(31)上。
17.根据权利要求14所述的方法,
其中,布置所述化合物半导体层(21)的步骤(203b)包括将过渡金属组和硫族化物组中的至少一种元素组合布置在所述导电层(31)上。
18.根据权利要求14所述的方法,
其中,所述导电层(31)在所述竖直通道开口(13)内直接且正好布置在所述衬底(10)上,或者
其中,隔离层(33)在所述竖直通道开口(13)内布置在所述衬底(10)与所述导电层(31)之间。
19.根据权利要求14所述的方法,
其中,布置所述化合物半导体层(22)的步骤(203b)包括通过应用沉积方法将所述化合物半导体层(21)沉积在所述导电层(31)上。
20.根据权利要求14所述的方法,
其中,所述化合物半导体层(21)由所述导电层(31)的至少一部分通过化学转化形成。
21.根据权利要求14所述的方法,
其中,生成所述层堆叠(20)的步骤(203)还包括:
在所述竖直通道开口(13)内布置第二化合物半导体层(22),其中,所述第二化合物半导体层(22)布置在所述化合物半导体层(21)上并与其电流连接,以及
其中,所述第二化合物半导体层(22)布置在所述化合物半导体层(21)的与所述导电层(31)相对的一侧上,使得所述化合物半导体层(21)布置在所述导电层(31)与所述第二化合物半导体层(22)之间。
22.根据权利要求21所述的方法,
其中,所述第二化合物半导体层(22)包括至少一种2D复合材料。
23.根据权利要求21所述的方法,
其中,生成所述层堆叠(20)的步骤(203)还包括:
在所述竖直通道开口(13)内布置第三化合物半导体层(23),其中,所述第三化合物半导体层(23)布置在所述第二化合物半导体层(22)上并与其电流连接,以及
其中,所述第三化合物半导体层(23)布置在所述第二化合物半导体层(22)的与所述第一化合物半导体层(21)相对的一侧上,使得所述第二化合物半导体层(22)布置在所述化合物半导体层(21)与所述第三化合物半导体层(23)之间。
24.根据权利要求23所述的方法,
其中,所述第三化合物半导体层(23)包括至少一种2D复合材料。
25.根据权利要求23所述的方法,
其中,生成所述层堆叠(20)的步骤(203)还包括:
在所述竖直通道开口(13)内布置所述第二导电层(32),其中,所述第二导电层(32)布置在所述第三化合物半导体层(23)上并与其电流连接,以及
其中,所述第二导电层(32)布置在所述第三化合物半导体层(23)的与所述第二化合物半导体层(22)相对的一侧上,使得所述第三化合物半导体层(23)布置在所述第二化合物半导体层(22)与第二导电层(32)之间。
26.根据权利要求14所述的方法,
其中,所述衬底(10)通过布置在所述衬底(10)的第一主表面(11)上的接触部分(110)电流连接和/或机械连接到附加的分离的电子器件结构(101),其中,所述附加的分离的电子器件结构(101)与所述第一主表面(11)相对地布置,和/或
其中,所述衬底(10)电流连接和/或机械连接到所述附加的分离的电子器件结构(101)或者通过布置在第二主表面(12)上的接触部分电流连接和/或机械连接到另一附加的分离的电子器件结构,其中,所述另一附加的分离的电子器件结构与所述第二主表面(12)相对地布置,
以生成三维电子半导体器件(1000)。
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