CN103714026A - Memorizer access method and device supporting original-address data exchange - Google Patents
Memorizer access method and device supporting original-address data exchange Download PDFInfo
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Abstract
The invention discloses a memorizer access method and device supporting original-address data exchange. According to the method, read/write mode registers of processor cores are all set as data exchange modes, data are read from local memorizers and stored in sending FIFO, data exchange requests are applied from networkonchip arbitration, if requests are agreed and data channel using right is distributed, the data in the sending FIFO are output to a receiving data unpacking unit of the second processor core and a receiving data unpacking unit of the first processor core, the data are unpacked and stored in receiving FIFO, the data in the local memorizers are read by a reading controller and stored in the sending FIFO, and finally the data in the receiving FIFO are written into the local memorizers of the processor cores through a writing controller. According to the memorizer access method and device supporting the original-address data exchange, temporary buffers do not need to be developed, data exchange operation between cores can be carried out in original data storage addresses, the performance of a processor and the utilizing rate of the memorizer are improved, and the memorizer access method and device supporting the original-address data exchange have the advantages of being good in performance, low in power consumption, high in utilizing rate and high in processing speed.
Description
Technical field
The present invention relates to multi-core microprocessor field, relate in particular to a kind of memory access method and device of supporting former address exchanges data.
Background technology
Polycaryon processor generally includes the interface of internet, external memory storage and other chips on a plurality of same or different processing cores, sheet, and wherein on-chip interconnection network is used bus, cross bar switch network or network-on-chip that each processor core and interface are connected and are communicated by letter conventionally.Each processor core generally comprises program storage, fetching and instruction decoding unit, performance element, local data memory and local internuclear memory access apparatus and (or is direct memory access controller, DMA).Local DMA is connected with the instruction decoding unit of processor, local data-carrier store and on-chip interconnection network.Instruction decoding unit completes the decoding of instruction, and the decode results such as size of carrying out which kind of command operating (reading or write operation), source data address, destination data address and moving data are sent to DMA device by configuration bus.DMA device is accepted the operational order that decoding unit is sent, and is responsible for the data-carrier store of other processor cores on local data memory and sheet, and the accessing operation of data between processor external memory storage.Each processor core is processed from transferring a small block data in the middle of external memory storage, the data that may need other processor cores to produce in processing procedure, and it carries out data-moving operation by local DMA device.Traditional DMA generally has two passages, a write access and a read channel.Moving in process of data, above-mentioned two passages can not transmit simultaneously, therefore in carrying out multicomputer system during internuclear exchanges data, first in the middle of the local storage of processor core A and processor core B, open up respectively the interim memory buffer of the size such as, when A produces the desired data of B, processor core A starts local DMA device corresponding data is passed in the middle of the interim memory buffer of processor core B by on-chip interconnection network.When if processor core B has also produced the needed data of processor core A, processor core B must wait for that processor core A could start data transmission after complete by its local DMA device, corresponding data to be transferred to by on-chip interconnection network in the middle of the interim memory buffer of processor core A.Performance large, that reduced processor is carried out, is postponed in sort processor core A and the serial of B exchanges data, causes on-chip memory utilization factor to reduce simultaneously, has increased the power consumption of processor.
Summary of the invention
The technical problem to be solved in the present invention is just: for the technical matters of prior art existence, the invention provides memory access method and the device of the support former address exchanges data that a kind of performance is good, low in energy consumption, utilization factor is high, processing speed is fast.
For solving the problems of the technologies described above, the present invention by the following technical solutions:
A memory access method of supporting former address exchanges data, comprises the following steps:
1) the local read-write mode register of first processor core and the second processor core is set to data exchange mode, by data read-write control device reading out data from the local storage of first processor core and the second processor core of first processor core and the second processor core, and data are stored into respectively in the transmission FIFO of first processor core and the second processor core.The transmission data packaged unit of first processor core and the second processor core is reading out data from the transmission FIFO of described first processor core and the second processor core respectively, and respectively according to the read-write mode register of first processor core and the second processor core, the value of destination address register to on-chip interconnection network arbitration unit application first processor core to the second processor core, the second processor core is to the data channel of first processor core;
2) when described on-chip interconnection network arbitration unit is received at the same time described first processor core and the second processor core and is carried out the channel request of data exchange mode, distribute respectively first processor core to the data channel of the second processor core to first processor core, distribute the second processor core to the data channel of first processor core to the second processor core;
3) the local DMA device of described first processor core and the second processor core is accepted data unwrapper unit by what export to the second processor core and first processor core by data channel after the data packing in the transmission FIFO of the core of first processor described in step 1) and the second processor core respectively, by described reception data unwrapper unit, described packet is unpacked and stored in the reception FIFO of first processor core and the second processor core;
4) by the local DMA device of core of the core of first processor described in step 3) and the second processor core, respectively the data of sending and receiving are read and write to control, described data read-write control device is preferential to read operation, by Read Controller, read the data of local storage, and data are stored into and sent in FIFO;
5) in the local storage of described first processor core and the second processor core, write address is less than while reading address, writing controller start by the data in the reception FIFO described in step 3) write respectively described first processor core and the second processor core local storage in the middle of, complete former address exchanges data.
Further improvement as the memory access method of support of the present invention former address exchanges data:
Described step 2) in, described transmission data packaged unit is the data channel to first processor core described in the application of on-chip interconnection network arbitration unit to the second processor core according to the destination address of data and read-write mode, if obtain the right to use of passage, by described transmission data packaged unit, first read-write mode information, source address information, destination address information and transmission byte number information are formed to data packet head and send to the second processor core, followed by sending data to again described the second processor core.
In described step 3), described reception data unwrapper unit is stored in the read-write mode information of described packet, destination address information and reception byte number information respectively and receives reading and writing data mode register, receives data destination address register and receive in the middle of byte number register, then receives and data are unpacked and stored in the middle of described reception FIFO.
Technical solution of the present invention also provides a kind of memory access apparatus of supporting former address exchanges data, comprises data read-write control device, sends FIFO, receives FIFO, sends data packaged unit and receives data unwrapper unit;
Described data read-write control device comprises read-write mode register, source address register, destination address register, transmission byte number register, Read Controller, writing controller and address comparison and selection parts, described data read-write control device according to the order of first-in first-out from reading out data in the middle of described reception FIFO and send the data to described local storage;
Described transmission FIFO is connected with described data read-write control device, transmission data packaged unit, receives from the data of described local storage output;
Described reception FIFO is connected with described reception data unwrapper unit, data read-write control device, receives from the data of described data unwrapper unit output;
Described transmission data packaged unit comprises a data packing state machine and a transmission data counter, described transmission data packaged unit is connected with on-chip interconnection network with described transmission FIFO, data read-write control device, described transmission data packaged unit by the order of first-in first-out from sending read data in the middle of FIFO;
Described reception data unwrapper unit comprises that receiving byte number register, reception data destination register, reception data WriteMode register, reception data counter and data unpacks state machine, described reception data unwrapper unit and reception FIFO, data read-write control device, and on-chip interconnection network is connected, and the packet receiving is unpacked.
Further improvement as the memory access apparatus of support of the present invention former address exchanges data:
Data bus bit wide between described memory access apparatus and local storage is that the data bus bit wide that W at least doubles described memory access apparatus and on-chip interconnection network is w byte.
Described read-write mode register is connected with reception data unwrapper unit with configuration bus, Read Controller and the transmission data packaged unit of outside input, described read-write mode register is accepted described configuration bus and from the strange land that receives data unwrapper unit, is read the assign operation of configuration bus, and the data value of register is outputed to described Read Controller and sent data packaged unit by signal wire, also accept the clear operation of described Read Controller simultaneously;
Described source address register is connected with configuration bus, Read Controller, transmission data packaged unit and the reception data unwrapper unit of outside input, described source address register is accepted configuration bus and from the strange land that receives data unwrapper unit, is read the assign operation of configuration bus, and the data value of register is outputed to Read Controller and sent data packaged unit by signal wire.
Described destination address register is connected with configuration bus, transmission data packaged unit and the reception data unwrapper unit of outside input, described destination address register is accepted configuration bus and from the strange land that receives data unwrapper unit, is read the assign operation of configuration bus, and the data value of register is directly outputed to and sent data packaged unit by signal wire;
Described transmission byte number register is connected with configuration bus, Read Controller, transmission data packaged unit and the reception data unwrapper unit of outside input, described transmission byte number register is accepted configuration bus and from the strange land that receives data unwrapper unit, is read the assign operation of configuration bus, and the data value of register is outputed to Read Controller and sent data packaged unit by signal wire.
Described Read Controller comprises read states machine, read counter and reads address adder, be connected with address selection parts and writing controller with described read-write mode register, source address register, transmission byte number register, address comparison, the described address adder of reading is added the value of the value of described read counter and source address register to obtain reading address, and will described in read address and output to address relatively and address selection parts, the read access that described Read Controller carries out local storage according to the pattern of read-write mode register operates;
Described writing controller comprises to be write state machine, writes counter and write address totalizer, be connected with address selection parts and Read Controller with read-write mode register, reception FIFO, reception data unwrapper unit, address comparison, described write address totalizer is added the reception data destination address from described reception data unwrapper unit input to obtain write address with the value of writing counter, and the value of described write address is outputed to address relatively and address selection parts;
Described address is relatively connected with read-write mode register with described Read Controller, writing controller, reception data unwrapper unit with address selection parts, receive the writing address signal of reading address signal and writing controller output of described Read Controller output, to reading address and write address compares, and comparative result is returned to described writing controller, simultaneously according to the value of the reception data WriteMode from described reception data unwrapper unit output and read-write mode register, to described, read address and write address operates.
Described transmission data packaged unit is connected with on-chip interconnection network and is connected, comprise a data packing state machine and a transmission data counter, by the order of first-in first-out from read data in the middle of described transmission FIFO, and the data that comprise a packet are sent to on-chip interconnection network, described packet comprises read-write mode, destination address, source address and four kinds of information of transmission byte number.
The value of described reception byte number register, reception data destination address register, reception reading and writing data mode register directly outputs to described data read-write control device by signal wire.
Compared with prior art, the invention has the advantages that:
1, the present invention directly supports two-way internuclear independent data to move, and has reduced data communication expense, thereby has improved the performance of processor.
2, the present invention, in the situation that not opening up extra buffer, directly carries out internuclear data exchange operation in former address data memory space, has not only reduced data communication expense between multinuclear, and has improved the utilization factor of storer.
3, the present invention, in the middle of internuclear data exchange operation, is kept synchronously carrying out to the data exchange operation between two processor cores by on-chip interconnection network arbitration unit, has further reduced extra data synchronization overhead.
Accompanying drawing explanation
Fig. 1 is the memory access method schematic flow sheet of the support former address exchanges data of the embodiment of the present invention.
Fig. 2 is the memory access apparatus of embodiment of the present invention position and the interface schematic diagram in the middle of polycaryon processor.
Fig. 3 is the memory access apparatus schematic diagram of the support former address exchanges data of the embodiment of the present invention.
Fig. 4 is the data read-write control device schematic diagram in the memory access apparatus of the embodiment of the present invention.
Fig. 5 is the state transition graph of inside read states machine of the DMA device of the embodiment of the present invention.
Fig. 6 is the state transition graph that state machine is write in the inside of the DMA device of the embodiment of the present invention.
Fig. 7 is the schematic diagram of transmission data packaged unit of the DMA device of the embodiment of the present invention.
Fig. 8 is the state transition graph of data packings state machine of the DMA device of the embodiment of the present invention.
Fig. 9 is the reception data packaged unit schematic diagram of the DMA device of the embodiment of the present invention.
Figure 10 is the state transition graph that the data of the DMA device of the embodiment of the present invention unpack state machine.
Figure 11 is the schematic diagram that the DMA device of the use embodiment of the present invention carries out exchanges data.
Marginal data: 1, data read-write control device; 2, send FIFO; 3, receive FIFO; 4, send data packaged unit; 5, receive data unwrapper unit; 11, Read Controller; 12, writing controller; 13, read-write mode register; 14, source address register; 15, destination address register; 16, transmission byte number register; 17, address comparison and address selection parts; 41, data packing state machine; 42, send data counter; 51, receive byte number register; 52, receive data destination address register; 53, receive data source address register; 54, receive reading and writing data mode register; 55, data unpack state machine; 56, receive data counter; 111, read states machine; 112, read counter; 113, read address adder; 121, write state machine; 122, write counter; 123, write address totalizer.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 shows the access method steps flow chart that carries out former address exchanges data in the storer of the embodiment of the present invention.Wherein first processor core and the second processor core represent respectively any two in a plurality of processor cores.In the present embodiment, the quantity of processor core is four, and first processor core is processor core A, and the second processor core is processor core B.As shown in Figure 1, in the storer of the embodiment of the present invention, carry out the implementation step of access method of former address exchanges data as follows:
1) respectively the read-write mode register 13 of processor core A and processor core B is set to data exchange mode, by data read-write control device 1 reading out data from the local storage of processor core A and processor core B of processor core A and processor core B, and data are stored into respectively in the transmission FIFO 2 of processor core A and processor core B, the transmission data packaged unit 4 of processor core A and processor core B reading out data from transmission FIFO 2 separately, and to on-chip interconnection network arbitration unit request for data exchange request;
2), when the data exchange request of processor core A and processor core B is received in on-chip interconnection network arbitration simultaneously, agree to its data exchange request, and to processor core A and the processor core B while distribute data passage right to use.
3) the local DMA device of processor core A and processor core B is exported to respectively the reception data unwrapper unit 5 of processor core B and processor core A by the data that send in step 1) in FIFO2 by data channel, by receiving data unwrapper unit 5, receives and data are unpacked in the reception FIFO3 that stores respectively processor core B and processor core A into.
4) in step 3), the local DMA device of processor core A and processor core B is read and write control to the data of sending and receiving, the 1 priority processing read operation of data read-write control device, by Read Controller 11, read the data in local storage, and data are stored into and sent in FIFO2.
5) in the local storage of processor core A and processor core B, write address is less than while reading address, and writing controller 12 starts the data that receive in step 3) in FIFO3 to write respectively in the local storage of processor core A and processor core B, completes former address exchanges data.
In the present embodiment, transmission data packaged unit 4 is the data channel to on-chip interconnection network arbitration unit application processor core A to processor core B according to the destination address of data and read-write mode, if obtain the right to use of passage, by transmission data packaged unit 4, first read-write mode information, source address information, destination address information and transmission byte number information are formed to data packet head and send to processor core B, followed by sending data to again processor core B.
In the present embodiment, receive data unwrapper unit 5 and the read-write mode information of data packet head, destination address information and reception byte number information are stored in respectively receive reading and writing data mode register 54, receive data destination address register 15 and receive in the middle of byte number register 51, then receive and data packing is stored into and received in the middle of FIFO3.
Fig. 2 shows memory access apparatus embodiment of the present invention in four core processors.As seen from the figure, each processor core is connected by on-chip interconnection network, and each processor core comprises a program storage, fetching and decoding unit, a performance element, a data-carrier store and a memory access apparatus of the present invention.In the present embodiment, memory access apparatus is connected with instruction decoding unit, local storage and the on-chip interconnection network of processor core, receive the configuration information that instruction decoding unit sends, complete corresponding operation and to instruction decoding unit, return to a look-at-me afterwards.Data bus bit wide in the present invention between memory access apparatus and local storage is W byte, with the data bus bit wide of on-chip interconnection network be w byte, W=n*w wherein, n is more than or equal to 2 positive integer.Native processor is accessed and is moved the local memory data of other processor cores by memory access apparatus.
As shown in Figure 3, memory access apparatus of the present invention comprises data read-write control device 1, sends FIFO2, receives FIFO3, sends data packaged unit 4 and receives data unwrapper unit 5.Wherein data read-write control device 1 is connected with transmission FIFO2, reception FIFO3, transmission data packaged unit 4 and reception data unwrapper unit 5 respectively, control the read and write operation of data, and preferential enable read accessing operation, only have and be not activated or send FIFO2 when full, enable write accessing operation when read operation; Data read-write control device 1 from receiving in the middle of FIFO3 reading out data and sending the data to local storage, takies to timesharing port memory according to the order of first-in first-out when controlling read and write operation; Send FIFO2 and be connected with data read-write control device 1, transmission data packaged unit 4, its inputoutput data bit wide is W byte, receives from the data of local storage output; Reception FIFO3 and reception data unwrapper unit 5, data read-write control device 1 are connected, and its inputoutput data bit wide is W byte, receive from receiving the data of data unwrapper unit 5 outputs; Send data packaged unit 4 and send FIFO2, data read-write control device 1 and on-chip interconnection network are connected, the data bus bit wide that transmission data packaged unit 4 is connected with on-chip interconnection network is w byte, and the packet that sends to on-chip interconnection network comprises read-write mode, destination address, source address and transmission four kinds of information of byte number and other relevant informations; Reception data unwrapper unit 5 and reception FIFO3, data read-write control device 1, and on-chip interconnection network is connected, its operation is contrary with transmission data packaged unit 4, and the packet receiving is unpacked.
As shown in Figure 4, the data read-write control device 1 in memory access apparatus of the present invention comprises read-write mode register 13, source address register 14, destination address register 15, transmission byte number register 16, Read Controller 11, writing controller 12 and address comparison and address selection parts 17.When system reset enables when effective, all registers are endowed null value, and read states machine 111 enters idle condition.While having at the same time the read-write operation of pair local storage, preferential enable read operation.
In the present embodiment, read-write mode register 13 and the outside configuration bus of inputting, Read Controller 11, and transmission data packaged unit 4 is connected with reception data unwrapper unit 5, the assign operation that it is accepted configuration bus and reads configuration bus from the strange land that receives data unwrapper unit 5, its data value is outputed to Read Controller 11 and sent data packaged unit 4 by signal wire, read while write the clear operation that mode register 13 is also accepted Read Controller 11.By configuring different values, read-write mode register 13 has three kinds of patterns: local read data pattern, strange land read data pattern and data exchange mode;
In the present embodiment, source address register 14 and the outside configuration bus of inputting, Read Controller 11, sending data packaged unit 4 is connected with reception data unwrapper unit 5, accept configuration bus and from the strange land that receives data unwrapper unit 5, read the assignment of configuration bus, its data value is outputed to Read Controller 11 and sent data packaged unit 4 by signal wire;
In the present embodiment, destination address register 15 is connected with configuration bus, transmission data packaged unit 4 and the reception data unwrapper unit 5 of outside input, accept configuration bus and from the strange land that receives data unwrapper unit 5, read the assignment of configuration bus, and its data value is directly outputed to and sent data packaged unit 4 by signal wire;
In the present embodiment, transmission byte number register 16 is connected with configuration bus, Read Controller 11, transmission data packaged unit 4 and the reception data unwrapper unit 5 of outside input, accept configuration bus and from the strange land that receives data unwrapper unit 5, read the assignment of configuration bus, its data value is outputed to Read Controller 11 and sent data packaged unit 4 by signal wire; As shown in Figure 3, Read Controller 11 is connected with writing controller 12 with address selection parts 17 with read-write mode register 13, source address register 14, transmission byte number register 16, address comparison, carries out the read access operation of local storage according to the value of read-write mode register 13.
In the present embodiment, Read Controller 11 comprises read states machine 111, read counter 112 and read address adder 113, wherein read address adder 113 value of the value of source address register 14 and read counter 112 is added and obtains reading address, and output is read address to address comparison and address selection parts 17.Read states machine 111 is by reading idle condition, and read data state, runs through waiting status, has write waiting status one of four states and has formed, and its transfer process as shown in Figure 5.When system reset enables when effective, read states machine 111 enters reads idle condition, read counter 112 zero clearings, all output enable invalidating signals.Read states machine 111 is in reading idle pulley, if when the value of read-write mode register 13 is local reading mode or data exchange mode, read states machine 111 enters read data state, puts busy the enabling of read states machine 111 and effectively, exports and read address, and read counter 112 adds W.Read states machine 111 is in read data state, if send, FIFO2 is non-full enables invalidly, suspends read operation, puts all output enables invalid.When the value of read counter 112 equals to transmit the value of byte number register 16, read operation completes, and the enable signal of all outputs is invalid.If be now local reading mode, or data exchange mode, and writing data completes and enables effectively, the next clock period enters and runs through waiting status, read states machine 111 is in running through waiting status, if data have been packed, enables when effective, and the next clock period proceeds to reads idle condition, read counter 112 zero clearings, all output enables are invalid; If be now data exchange mode, and data have been packed and are enabled effectively, to enter and write waiting status.Read states machine 111 is in having write waiting status, if write data, completes and enables when effective, and read states machine 111 enters reads idle condition, and read counter 112 is clear 0, and all output enables are invalid;
In the present embodiment, writing controller 12 is connected with address selection parts 17 and Read Controller 11 with read-write mode register 13, reception FIFO3, reception data unwrapper unit 5, address comparison, according to carrying out write operation from receiving the value of the reception data WriteMode signal of data unwrapper unit 5 outputs.Writing controller 12 comprises writes state machine 121, write counter 122 and write address totalizer 123, wherein write address totalizer 123 will be added and obtain write address with the value of writing counter 122 from receiving the value of the reception data destination address signal of data unwrapper unit 5 outputs, and write address is outputed to address relatively and address selection parts 17.Write state machine 121 and form by writing idle condition and writing data mode, its transfer process as shown in Figure 6.When system reset enables when effective, write state machine 121 and enter and write idle condition, write counter 122 zero clearings, all output enable invalidating signals.Write state machine 121 in writing idle condition, if receive FIFO3 non-NULL, enable effectively, next cycle enters and writes data mode, if now read states machine 111 hurries and enables invalidly, writes counter 122 and adds W, and write address output, carries out memory write operation.Write state machine 121 in writing data mode, if receive FIFO3 non-NULL, enable invalid or busy the enabling of read states machine 111 and effectively, suspend write operation, all output enable invalidating signals.When receiving that FIFO3 non-NULL enables effectively and busy the enabling of read states machine 111 when invalid, continued write operation.Until write the value of counter 122, equal when receiving the reception data word joint number of data unwrapper unit 5 outputs, to enter and write idle condition, put and write data and complete and enable effectively, to write counter 122 zero clearings, other output enable invalidating signals; As shown in Figure 4, address is relatively connected with read-write mode register 13 with Read Controller 11, writing controller 12, reception data unwrapper unit 5 with address selection parts 17, complete reading the comparison and selection output function of address and write address, and comparative result is returned to writing controller 12.Simultaneously according to from receiving the data unwrapper unit 5 reception data WriteModes of input and the value of read-write mode register 13 to reading address and write address operates.When read states machine 111 is busy enable invalid, the value of read-write mode register 13 and to receive data WriteMode be all data exchange mode, and write address is less than in the situation of reading address, selection write address also outputs to external memory address bus interface; When read states machine 111 is busy, enable invalidly, and when receiving data WriteMode and being local read data pattern, select write address also to output to external memory address bus interface.All the other situations operate according to the busy enable signal of read states machine 111.If read states machine 111 is busy, enabling effectively, select output to read address to memory address bus port, is 0 otherwise put memory address bus.
As shown in Figure 7, the transmission data packaged unit 4 in memory access apparatus of the present invention and transmission FIFO2, data read-write control device 1 and on-chip interconnection network are connected, and it comprises a data packing state machine 41 and a transmission data counter 42.The data bus bit wide that transmission data packaged unit 4 is connected with on-chip interconnection network is w byte, the data that send to on-chip interconnection network comprise a data packet head and immediately following data thereafter, wherein data packet head comprises read-write mode, destination address, source address and four kinds of information of transmission byte number.
In the present embodiment, data packing state machine 41, by idle, bus application, sends packet header and sends data one of four states, and its state conversion as shown in Figure 8.When system reset enables when effective, data packing state machine 41 enters idle condition, and all output enables are invalid, send data counter 42 zero clearings.Data packing state machine 41 is in idle condition, when if the read-write mode register 13 in the middle of data read-write control device 1 is local read data, exchanges data or strange land read data pattern, data packing state machine 41 enters bus application status, puts Packet Generation request signal effective.Data packing state machine 41 is in bus application status, if Packet Generation enable signal is effective, enter the packet header state that sends, start to send header packet information: the information in the middle of the transmission byte number register 16 in reading out data read-write controller 1, destination address register 15, source address register 14 and read-write mode register 13 is packed, send to and send in packet bus, and enable to send packet useful signal.Data packings state machine 41, in sending packet state, if the value of read-write mode register 13 is strange land read data pattern, proceeds to idle condition when sending packet information after, puts data and has packed and enable effectively, and other output enables are invalid; When if the value of read-write mode register 13 is local read data or data exchange mode, after sending packet information, proceed to transmission data mode, if now sending FIFO2 is non-NULL, read so the data that send FIFO2, data are split into the small data of a plurality of w bytes by address order from small to large and send in packet bus, w byte data of every transmission, sends data counter 42 and adds w.Until when sending the value of data counter 42 and equaling to transmit byte number, this secondary data pack, to put data and pack and enable effectively, other output enables are invalid, and state machine proceeds to idle condition, transmission data counter 42 clear 0.
As shown in Figure 9, reception data unwrapper unit 5 in memory access apparatus of the present invention is connected with on-chip interconnection network with reception FIFO3, data read-write control device 1, its principle of work is contrary with transmission data packaged unit 4, from bus, receive packet, and the information of data is unpacked, data-carrier store is in the middle of reception FIFO3.In the present embodiment, reception data unwrapper unit 5 comprises that receiving byte number register 51, reception data destination address register 52, reception data source address register 53, reception reading and writing data mode register 54, reception data counter 56 and data unpacks state machine 55.Wherein, the value of reception byte number register 51, reception data destination address register 52, reception reading and writing data mode register 54 directly outputs to data read-write control device 1 by signal wire.
In the present embodiment, data unpack state machine 55 and comprise the free time, agree to that packet receives request, reception packet header, reception data and wait and write five states, and its state conversion as shown in figure 10.When system reset enables when effective, data unpack state machine 55 and enter idle condition, receive data counter 56 zero clearings, all output enable invalidating signals.Data unpack state machine 55 in idle condition, if packet receives request effectively, and judgement receives the type of request.If strange land read request checks that the read-write mode signals of sending from data read-write control device 1 is now idle (whether equaling 0).If idle, enter and receive data packet head state, put packet and receive and enable effectively, otherwise put packet, receive and enable invalidly, wait for that the read operation of data read-write control device 1 completes; If receiving the type of request is local read data or data exchange mode, put packet reception and enable effectively, enter the data packet head state that receives.Data unpack state machine 55 in receiving data packet head state, start to receive and decoded data header packet information: if strange land read data request, the source address information packet being comprised, destination address information, transmission byte number information, and read-write mode information exchange is crossed destination address register 15, source address register 14, transmission byte number register 16 and read-write mode register 13 that configuration bus difference data writing read-write controller 1 is read in strange land, after writing, data unpack state machine 55 and turn as idle condition in the next clock period; If local read data pattern or data exchange mode, the destination address information packet being comprised, transmission byte number information, and read-write mode information writes respectively reception data destination address register 52, receives byte number register 51 and receives reading and writing data mode register 54, after writing, data unpack state machine 55 and enter reception data mode, start to receive data.W byte data of every reception, receives data counter 56 and adds w, until receive the value that the value of data counter 56 equals to receive byte number register 51, data unpack state machine 55 and enter and wait for and write completion status.Data unpack state machine 55 and write completion status in waiting for, if write data, complete and enable effectively, and data unpack state machine 55 and enter idle condition, and putting and receiving data calculator is 0, and all output enables are invalid.
Figure 11 shows and uses memory access apparatus of the present invention to carry out internuclear data exchange operation process.Memory access apparatus of the present invention is by the transmission FIFO2 of processor core A inside and the reception FIFO3 of processor core B inside, the transmission FIFO2 of the reception FIFO3 of processor core A inside and processor core B inside has stored respectively the data that data block B1 and a B3 part will be moved, in the local memory access device of processor core A and processor core B, on former address data memory space, directly carry out exchanges data, data read-write control device 1 is only less than and reads data to be write to local storage in the situation of address at write address, guaranteed each central data write-after-read of storer.So just can realize swap data transmitted in both directions, both accelerate data signaling rate, thereby improve processor performance, make again exchanges data be able to carry out on former address, improve storer utilization factor.
Below be only the preferred embodiment of the present invention, protection scope of the present invention is also not only confined to above-described embodiment, and all technical schemes belonging under thinking of the present invention all belong to protection scope of the present invention.It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principles of the present invention, should be considered as protection scope of the present invention.
Claims (10)
1. a memory access method of supporting former address exchanges data, is characterized in that, comprises the following steps:
1) the local read-write mode register (13) of first processor core and the second processor core is set to data exchange mode, by data read-write control device (1) reading out data from the local storage of first processor core and the second processor core of described first processor core and the second processor core, and data are stored respectively into the transmission FIFO(2 of first processor core and the second processor core) in, again by the transmission data packaged unit (4) of first processor core and the second processor core respectively from the transmission FIFO(2 of first processor core and the second processor core) reading out data, and respectively according to the read-write mode register (13) of first processor core and the second processor core, the value of destination address register (15) is to on-chip interconnection network arbitration unit application first processor core to the second processor core, the second processor core is to the data channel of first processor core,
2) when described on-chip interconnection network arbitration unit is received at the same time described first processor core and the second processor core and is carried out the channel request of data exchange mode, distribute respectively first processor core to the data channel of the second processor core to first processor core, distribute the second processor core to the data channel of first processor core to the second processor core;
3) the local DMA device of described first processor core and the second processor core is respectively by the transmission FIFO(2 of the core of first processor described in step 1) and the second processor core) in data packings after by data channel, export to the reception data unwrapper unit (5) of the second processor core and first processor core, by described reception data unwrapper unit (5), described packet is unpacked and is stored into the reception FIFO(3 of first processor core and the second processor core) in;
4) by the local DMA device of the core of first processor described in step 3) and the second processor core, respectively the data of sending and receiving are read and write to control, data read-write control device (1) is preferential to read operation, the data of reading local storage by Read Controller (11), and data are stored into and send FIFO(2) in;
5) in the local storage of described first processor core and the second processor core, write address is less than while reading address, writing controller (12) starts to receive FIFO(3 by described in step 3)) in data write respectively described first processor core and the second processor core local storage in the middle of, complete former address exchanges data.
2. the memory access method of support according to claim 1 former address exchanges data, it is characterized in that: described step 2), the transmission data packaged unit (4) of described first processor core is the data channel to first processor core described in the application of on-chip interconnection network arbitration unit to the second processor core according to the destination address of data and read-write mode, when described upper internet arbitration receives the data exchange request that first processor core and the second processor core send at the same time, to distribute respectively idle data channel to first processor core and the second processor core, if obtain the right to use of passage, by described transmission data packaged unit (4) first by read-write mode information, source address information, destination address information and transmission byte number information form data packet head and send to the second processor core, followed by sending again other data to described the second processor core.
3. the memory access method of support according to claim 2 former address exchanges data, it is characterized in that: in described step 3), described reception data unwrapper unit (5) is stored in the read-write mode information of described data packet head, destination address information and reception byte number information respectively and receives reading and writing data mode register (54), receives data destination address registers (52) and receive in the middle of byte number register (51), then receives and data are unpacked and store described reception FIFO(3 into) in the middle of.
4. a memory access apparatus of supporting former address exchanges data, is characterized in that: comprise data read-write control device (1), send FIFO(2), receive FIFO(3), send data packaged units (4) and receive data unwrapper unit (5);
Described data read-write control device (1) comprises read-write mode register (13), source address register (14), destination address register (15), transmission byte number register (16), Read Controller (11), writing controller (12) and address relatively and address selection parts (17), described data read-write control device (1) according to the order of first-in first-out from described reception FIFO(3) central reading out data send the data to described local storage;
Described transmission FIFO(2) be connected with described data read-write control device (1), transmission data packaged units (4), receive from the data of described local storage output;
Described reception FIFO(3) be connected with described reception data unwrapper unit (5), data read-write control device (1), receive from the data of described reception data unwrapper unit (5) output;
Described transmission data packaged unit (4) comprises a data packing state machine (41) and a transmission data counter (42), described transmission data packaged unit (4) and described transmission FIFO(2), data read-write control device (1) is connected with on-chip interconnection network, described transmission data packaged unit (4) by the order of first-in first-out from sending FIFO(2) in the middle of read data;
Described reception data unwrapper unit (5) comprises that receiving byte number register (51), reception data destination address registers (52), reception data source address register (53), reception reading and writing data mode register (54), reception data counter (56) and data unpacks state machine (55), described reception data unwrapper unit (5) and receive FIFO(3), data read-write control device (1) with and on-chip interconnection network be connected, the packet receiving is unpacked.
5. the memory access apparatus of support according to claim 4 former address exchanges data, is characterized in that: the data bus bit wide between described memory access apparatus and local storage is that the data bus bit wide that W at least doubles described memory access apparatus and on-chip interconnection network is w byte.
6. the memory access apparatus of support according to claim 4 former address exchanges data, is characterized in that:
Described read-write mode register (13) is connected with reception data unwrapper unit (5) with configuration bus, Read Controller (11) and the transmission data packaged units (4) of outside input, described read-write mode register (13) is accepted described configuration bus and from the strange land that receives data unwrapper unit (5), is read the assign operation of configuration bus, and the data value of described read-write mode register (13) is outputed to described Read Controller (11) and sent data packaged units (4) by signal wire, also accept the clear operation of described Read Controller (11) simultaneously;
Described source address register (14) is connected with configuration bus, Read Controller (11), transmission data packaged units (4) and the reception data unwrapper unit (5) of outside input, described source address register (14) is accepted configuration bus and from the strange land that receives data unwrapper unit (5), is read the assign operation of configuration bus, and the data value of described source address register (14) is outputed to Read Controller (11) and sent data packaged units (4) by signal wire.
7. the memory access apparatus of support according to claim 4 former address exchanges data, it is characterized in that: described destination address register (15) is connected with configuration bus, transmission data packaged units (4) and the reception data unwrapper unit (5) of outside input, described destination address register (15) is accepted configuration bus and from the strange land that receives data unwrapper unit (5), is read the assign operation of configuration bus, and the data value of described destination address register (15) is directly outputed to and sent data packaged units (4) by signal wire;
Described transmission byte number register (16) is connected with configuration bus, Read Controller (11), transmission data packaged units (4) and the reception data unwrapper unit (5) of outside input, described transmission byte number register (16) is accepted configuration bus and from the strange land that receives data unwrapper unit (5), is read the assign operation of configuration bus, and the data value of described transmission byte number register (16) is outputed to Read Controller (11) and sent data packaged units (4) by signal wire.
8. the memory access apparatus of support according to claim 4 former address exchanges data, it is characterized in that: described Read Controller (11) comprises read states machine (111), read counter (112) and read address adder (113), with described read-write mode register (13), source address register (14), transmission byte number register (16), address is relatively connected with address selection parts (17) and writing controller (12), the described address adder (113) of reading is added the value of the value of described read counter (112) and source address register (14) to obtain reading address, and will described in read address and output to address relatively and address selection parts (17), described Read Controller (11) carries out the read access operation of local storage according to the pattern of read-write mode register (13),
Described writing controller (12) comprises writes state machine (121), write counter (122) and write address totalizer (123), with read-write mode register (13), receive FIFO(3), receive data unwrapper unit (5), address is relatively connected with address selection parts (17) and Read Controller (11), described write address totalizer (123) is added the reception data destination address from described reception data unwrapper unit (5) input to obtain write address with the value of writing counter (122), and the value of described write address is outputed to address relatively and address selection parts (17),
Compare and address selection parts (17) and described Read Controller (11) described address, writing controller (12), receiving data unwrapper unit (5) is connected with read-write mode register (13), receive the writing address signal of reading address signal and writing controller (12) output of described Read Controller (11) output, to reading address and write address compares, and comparative result is returned to described writing controller (12), simultaneously according to the value of the reception data WriteMode information from described reception data unwrapper unit (5) output and read-write mode register (13), to described, read address and write address operates.
9. the memory access apparatus of support according to claim 4 former address exchanges data, it is characterized in that: described transmission data packaged unit (4) is connected with on-chip interconnection network and is connected, comprise a data packing state machine (41) and a transmission data counter (42), press the order of first-in first-out from described transmission FIFO(2) central read data, and will after the data packing of reading, sending to on-chip interconnection network, described packet comprises read-write mode, destination address, source address and four kinds of information of transmission byte number.
10. the memory access apparatus of support according to claim 4 former address exchanges data, is characterized in that: the value of described reception byte number register (51), reception data destination address registers (52), reception reading and writing data mode register (54) directly outputs to described data read-write control device (1) by signal wire.
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