CN112269654A - PCIE resource automatic splitting circuit and method - Google Patents
PCIE resource automatic splitting circuit and method Download PDFInfo
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- CN112269654A CN112269654A CN202010988089.2A CN202010988089A CN112269654A CN 112269654 A CN112269654 A CN 112269654A CN 202010988089 A CN202010988089 A CN 202010988089A CN 112269654 A CN112269654 A CN 112269654A
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000013507 mapping Methods 0.000 claims abstract description 14
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
The application discloses a PCIE resource automatic splitting circuit and a method, comprising the following steps: the system comprises an ASM2824 chip, a CPLD, a first SLIML connector and a second SLIML connector, wherein the first SLIML connector and the second SLIML connector correspond to a PCIE X8 channel of the ASM2824 chip respectively; the configuration signal interface of the ASM2824 chip is connected with the CPLD, and the CPLD is connected with the ID pins of the first SLIML connector and the second SLIML connector; the ID pins of the first SLIMLINE connector and the second SLIMLINE connector are used for being connected with the ID pins of the corresponding SLIMLINE connectors on the corresponding board cards respectively. According to the method and the device, the ID pin is set for the SLIMLINE connector, the CPLD can know the PCIE resource condition required by the current board card according to the ID pin on the SLIMLINE connector of the board card inserted into the mainboard, and the PCIE resource dividing mode of the ASM2824 chip is set according to the ID pin and the preset signal mapping relation, so that automatic PCIE resource division is completed.
Description
Technical Field
The invention relates to the field, in particular to a PCIE resource automatic splitting circuit and a method.
Background
The existing ASM2824 chip supports conversion from X8 PCIE to two X8 PCIE, the PCIE supports a PCIE3.0 protocol, and the strap on the chip configures the pin GPIO0, GPIO1, and GPIO2, which can configure the split mode of two downlink X8 PCIE, thereby implementing the PCIE resource expansion function.
The prior designs realize the configuration of PCIE resources by a pull-up resistor or an external jump cap, but the pull-up resistor can only realize the fixed PCIE splitting, the external jump cap can realize different splitting modes, but the upper cover of a case needs to be opened according to the actual configuration condition, and the jump cap is manually modified to realize different PCIE splitting.
To this end, a more flexible method for ASM2824 PCIE dynamic split is proposed herein.
Disclosure of Invention
In view of this, the present invention is to provide a circuit and a method for automatically splitting PCIE resources, which can more flexibly and automatically split the PCIE resources of the ASM 2824. The specific scheme is as follows:
a PCIE resource automatic splitting circuit comprises: the system comprises an ASM2824 chip, a CPLD, a first SLIML connector and a second SLIML connector, wherein the first SLIML connector and the second SLIML connector respectively correspond to a PCIE X8 channel of the ASM2824 chip;
the configuration signal interface of the ASM2824 chip is connected with the CPLD, and the CPLD is connected with the ID pins of the first SLIML connector and the second SLIML connector;
and the ID pins of the first SLIMLINE connector and the second SLIMLINE connector are respectively used for being connected with the ID pins of the corresponding SLIMLINE connectors on the corresponding board cards.
Optionally, the FLASH memory is connected with the ASM2824 chip through an SPI bus.
Optionally, the system further includes a pull-up resistor connected to the ID pins of the first SLIMLINE connector and the second SLIMLINE connector, respectively.
Optionally, the card also comprises an X8X 8Riser card;
the X8X 8Riser card includes a third SLIMLINE connector having an ID pin for connecting with the ID pin of the first SLIMLINE connector or the second SLIMLINE connector.
Optionally, the NVME-based network component further comprises an NVME backplane;
the NVME backplane includes a fourth SLIMLINE connector having an ID pin for connecting with the ID pin of the first SLIMLINE connector or the second SLIMLINE connector.
The invention also discloses a PCIE resource automatic splitting method, which is applied to the CPLD and comprises the following steps:
receiving an ID signal transmitted by an ID pin of a first SLIMLINE connector or a second SLIMLINE connector;
assigning a value to a configuration signal interface of an ASM2824 chip according to a preset signal mapping relation and an ID signal, so that the ASM2824 chip splits PCIE resources according to the assignment of the configuration signal interface;
the signal mapping relationship is a mapping relationship between the ID signal and the assignment of the configuration signal interface which is established in advance.
In the present invention, a PCIE resource automatic splitting circuit includes: the system comprises an ASM2824 chip, a CPLD, a first SLIML connector and a second SLIML connector, wherein the first SLIML connector and the second SLIML connector correspond to a PCIE X8 channel of the ASM2824 chip respectively; the configuration signal interface of the ASM2824 chip is connected with the CPLD, and the CPLD is connected with the ID pins of the first SLIML connector and the second SLIML connector; the ID pins of the first SLIMLINE connector and the second SLIMLINE connector are used for being connected with the ID pins of the corresponding SLIMLINE connectors on the corresponding board cards respectively.
According to the method, the SLIMLINE connector is provided with the ID pin, the CPLD can know the PCIE resource condition required by the current board card according to the ID pin on the SLIMLINE connector of the board card inserted into the mainboard, and the PCIE resource dividing mode of the ASM2824 chip is set according to the ID pin and the preset signal mapping relation, so that the automatic PCIE resource division is completed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a circuit diagram of an automatic PCIE resource splitting circuit disclosed in the embodiment of the present invention;
fig. 2 is a flowchart of a method for automatically splitting PCIE resources according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a PCIE resource automatic splitting circuit, which is shown in figure 1 and comprises: the system comprises an ASM2824 chip, a CPLD, a first SLIML connector and a second SLIML connector, wherein the first SLIML connector and the second SLIML connector correspond to a PCIE X8 channel of the ASM2824 chip respectively;
the configuration signal interface of the ASM2824 chip is connected with the CPLD, and the CPLD is connected with the ID pins of the first SLIML connector and the second SLIML connector;
the ID pins of the first SLIMLINE connector and the second SLIMLINE connector are used for being connected with the ID pins of the corresponding SLIMLINE connectors on the corresponding board cards respectively.
Specifically, a PCIE X8 channel of the ASM2824 chip is connected to the first SLIMLINE connector and the second SLIMLINE connector, so that the first SLIMLINE connector and the second SLIMLINE connector are connected to the corresponding board card, and a PCIE X8 channel is output.
Specifically, the first SLIMLINE connector and the second SLIMLINE connector are provided with ID pins and used for being connected with the ID pins on the SLIMLINE connectors of the corresponding board cards, so that the board cards can transmit the ID pins of the board cards to the CPLD through the ID pins of the first SLIMLINE connector and the ID pins of the second SLIMLINE connector. At this time, the PCIE resource division requirement of the board card may be combined with the ID pin, and a corresponding signal mapping relationship is established, so that the CPLD controls the PCIE resource division of the ASM2824 chip through the configuration signal interface of the ASM2824 chip according to the ID pin.
Specifically, for example, first SLIMLINE connector SLIMLINE0 and second SLIMLINE connector SLIMLINE1 may set two ID pins, respectively: s0_ ID0, S0_ ID1 and S1_ ID0, S1_ ID 1.
Specifically, the corresponding board card may include an X8X 8Riser card and an NVME backplane.
Specifically, the X8X 8Riser card may include a third SLIMLINE connector having an ID pin for connecting with the ID pin of the first SLIMLINE connector or the second SLIMLINE connector.
For example, the third SLIMLINE2 and two ID pins set therein: ID0 and ID1
Specifically, the NVME backplane may include a fourth SLIMLINE connector having an ID pin for connecting with the ID pin of the first SLIMLINE connector or the second SLIMLINE connector.
For example, the fourth SLIMLINE connector SLIMLINE3 also sets two ID pins: ID0 and ID 1.
Specifically, after the STBY is powered on the motherboard 1 where the ASM2824 is located, and the CPLD ready, the CPLD may determine which board is according to the states of S0_ ID1 and S0_ ID0 or S1_ ID1 and S1_ ID0, for example, if the IDs detected by S0_ ID1 and S0_ ID0 are 00, then the first SLIMLINE connector is currently connected to the X8Riser card, and if the states detected by S1_ ID1 and S1_ ID0 are 01, the first SLIMLINE connector is currently connected to the NVME backplane.
At this time, the CPLD assigns values to GPIO2, GPIO1 and GPIO0 configuring the signal interface according to states of S0_ ID1 and S0_ ID0 or S1_ ID1 and S1_ ID0, for example, if ID1 and ID0 are 00, GPIO2, GPIO1 and GPIO0 are assigned to 100, when the ASM2824 recognizes that the states of the three GPIOs are 100 when the power is turned on and powered on, then the split mode of the PCIE is X8 PCIE; when the CPLD recognizes that the IDs 1 and 0 are 01, the GPIO2, GPIO1 and GPIO0 are assigned to be 011, and when the power is turned on and the ASM2824 recognizes that the states of the three GPIOs are 011, the split mode of the PCIE is two X4 PCIEs. The automatic identification of the inserted board cards is realized, and PCIE division is automatically carried out.
Specifically, the specific PCIE split mode of ASM2824 can refer to a table of ASM2824 PCIE split mode.
Watch 1
Specifically, according to the ASM2824 PCIE splitting mode introduced in table one, after different boards preset respective ID pins to be included in the first SLIMLINE connector and the second SLIMLINE connector of the ASM2824 chip on the motherboard 1, the CPLD reads the ID pins, and configures assignment of signal interfaces (GPIO2, GPIO1, GPIO0) according to the signal mapping relationship recorded in table one, thereby implementing multiple automatic PCIE divisions of the ASM2824 chip.
It can be seen that, in the embodiment of the present invention, an ID pin is set for the SLIMLINE connector, and the CPLD can know the PCIE resource condition required by the current board card according to the ID pin on the SLIMLINE connector of the board card inserted into the motherboard 1, and set the PCIE resource division mode of the ASM2824 chip according to the ID pin and the preset signal mapping relationship, thereby completing automatic PCIE resource division.
Specifically, the ID pins of the first SLIMLINE connector and the second SLIMLINE connector are further connected with a pull-up resistor, which includes additional resistors R0 and R1 pulled up to the P3V3_ STBY power supply, where the resistors R0 and R1 may be set to 4.7K Ω, that is, the default IDs 1 and ID0 at the motherboard end are logic 11.
Specifically, the X8X 8Riser card is respectively added with resistors R4 and R5 to be pulled down to GND, where the resistors R4 and R5 can be set to 0 Ω, i.e., the X8X 8Riser card end default ID1 and ID0 are logic 00, and are connected with the main board end ID1 and ID0 through cables.
Specifically, the NVME backplane is respectively pulled up to P3V3_ STBY by an additional resistor R6 and pulled down to GND by a resistor R7, where the resistor R6 may be set to 4.7K Ω, and R7 may be set to 0 Ω, that is, default IDs 1 and ID0 of the NVME backplane end are logic 01, and correspond to the main board IDs 1 and ID0 through cable connection.
Specifically, the device also comprises a FLASH memory which is connected with the ASM2824 chip through an SPI bus, and the FLASH memory can provide a starting configuration file of the ASM 2824.
Specifically, the ASM2824 chip is also connected to the S2500 CPU through PCIE 3.0X 8 signals.
Correspondingly, the embodiment of the present invention further discloses a method for automatically splitting PCIE resources, as shown in fig. 2, which is applied to the CPLD described above, and includes:
s11: receiving an ID signal transmitted by an ID pin of a first SLIMLINE connector or a second SLIMLINE connector;
s12: assigning a value to a configuration signal interface of the ASM2824 chip according to a preset signal mapping relation and an ID signal, so that the ASM2824 chip splits PCIE resources according to the assignment of the configuration signal interface;
the signal mapping relationship is a mapping relationship between the pre-established ID signal and the assignment of the configuration signal interface.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The technical content provided by the present invention is described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the above description of the examples is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (6)
1. A PCIE resource automatic splitting circuit is characterized by comprising: the system comprises an ASM2824 chip, a CPLD, a first SLIML connector and a second SLIML connector, wherein the first SLIML connector and the second SLIML connector respectively correspond to a PCIE X8 channel of the ASM2824 chip;
the configuration signal interface of the ASM2824 chip is connected with the CPLD, and the CPLD is connected with the ID pins of the first SLIML connector and the second SLIML connector;
and the ID pins of the first SLIMLINE connector and the second SLIMLINE connector are respectively used for being connected with the ID pins of the corresponding SLIMLINE connectors on the corresponding board cards.
2. The automatic splitting circuit of PCIE resources of claim 1, further comprising a FLASH memory connected to the ASM2824 chip through an SPI bus.
3. The PCIE resource automatic splitting circuit of claim 2, further comprising pull-up resistors connected to ID pins of the first SLIMLINE connector and the second SLIMLINE connector, respectively.
4. The PCIE resource automatic splitting circuit of any one of claims 1 to 3, further comprising an X8X 8Riser card;
the X8X 8Riser card includes a third SLIMLINE connector having an ID pin for connecting with the ID pin of the first SLIMLINE connector or the second SLIMLINE connector.
5. The PCIE resource automatic splitting circuit of any one of claims 1 to 3, further comprising an NVME backplane;
the NVME backplane includes a fourth SLIMLINE connector having an ID pin for connecting with the ID pin of the first SLIMLINE connector or the second SLIMLINE connector.
6. An automatic splitting method for PCIE resources, applied to the CPLD according to any one of claims 1 to 5, includes:
receiving an ID signal transmitted by an ID pin of a first SLIMLINE connector or a second SLIMLINE connector;
assigning a value to a configuration signal interface of an ASM2824 chip according to a preset signal mapping relation and an ID signal, so that the ASM2824 chip splits PCIE resources according to the assignment of the configuration signal interface;
the signal mapping relationship is a mapping relationship between the ID signal and the assignment of the configuration signal interface which is established in advance.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010988089.2A CN112269654A (en) | 2020-09-18 | 2020-09-18 | PCIE resource automatic splitting circuit and method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010988089.2A CN112269654A (en) | 2020-09-18 | 2020-09-18 | PCIE resource automatic splitting circuit and method |
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| CN112269654A true CN112269654A (en) | 2021-01-26 |
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| US20090222609A1 (en) * | 2008-02-29 | 2009-09-03 | Inventec Corporation | Apparatus for automatically regulating system id of motherboard of server and server having the same |
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| CN107818062A (en) * | 2017-11-24 | 2018-03-20 | 郑州云海信息技术有限公司 | A kind of hard disk backboard and its design method of compatible SAS, SATA and NVME hard disk |
| CN209265434U (en) * | 2019-02-27 | 2019-08-16 | 苏州浪潮智能科技有限公司 | A kind of 8 disk position NVMe hard disk backboards with off-peak electrification function |
| CN210038633U (en) * | 2019-04-19 | 2020-02-07 | 苏州浪潮智能科技有限公司 | Flexibly configurable Riser card applied to GPU server |
| CN210639614U (en) * | 2019-11-08 | 2020-05-29 | 苏州浪潮智能科技有限公司 | NVME hard disk backboard system supporting various bandwidths |
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2020
- 2020-09-18 CN CN202010988089.2A patent/CN112269654A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090222609A1 (en) * | 2008-02-29 | 2009-09-03 | Inventec Corporation | Apparatus for automatically regulating system id of motherboard of server and server having the same |
| CN106959932A (en) * | 2017-04-14 | 2017-07-18 | 广东浪潮大数据研究有限公司 | A kind of Riser card methods for designing of automatic switchover PCIe signals |
| CN107818062A (en) * | 2017-11-24 | 2018-03-20 | 郑州云海信息技术有限公司 | A kind of hard disk backboard and its design method of compatible SAS, SATA and NVME hard disk |
| CN209265434U (en) * | 2019-02-27 | 2019-08-16 | 苏州浪潮智能科技有限公司 | A kind of 8 disk position NVMe hard disk backboards with off-peak electrification function |
| CN210038633U (en) * | 2019-04-19 | 2020-02-07 | 苏州浪潮智能科技有限公司 | Flexibly configurable Riser card applied to GPU server |
| CN210639614U (en) * | 2019-11-08 | 2020-05-29 | 苏州浪潮智能科技有限公司 | NVME hard disk backboard system supporting various bandwidths |
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