CN112231267B - B code timing method and device for domestic VPX architecture - Google Patents
B code timing method and device for domestic VPX architecture Download PDFInfo
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- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention relates to a B code time synchronization device of a home-made VPX framework, belonging to the technical field of home-made communication time synchronization. The B code timing device adopts a high-speed VPX bus, all components adopt a domestic design, and decoding and encoding of multi-path B codes can be realized; the strategy of soft separation of encoding and decoding is adopted, namely the encoding and the decoding are respectively responsible for two independent FPGAs, and a mutual check return path exists, so that the time synchronization precision of the B code can be effectively ensured. The decoding FPGA and the encoding FPGA can realize return time synchronization after decoding the received B code and decoding and checking after self encoding through the unified allocation of the CPU 2K 1000; by adopting a redundancy design, the time synchronization precision can reach 1 microsecond.
Description
Technical Field
The invention belongs to the technical field of home-made communication time synchronization, and particularly relates to a home-made B code time synchronization device with a VPX framework.
Background
At present, time synchronization, namely time synchronization, plays a very important role in many industry fields, such as aerospace systems, power electronics systems and the like, and the required time synchronization precision reaches microsecond level, so that the synchronous cooperative operation of the whole large system can be ensured. The B code is used as an international universal time code and has the characteristics of universality and standard property. However, most of the existing B-code time synchronization devices are low in precision and poor in working stability, and more importantly, the home-made design of components is not realized.
Disclosure of Invention
Technical problem to be solved
The technical problem to be solved by the invention is as follows: in order to solve the defects of the existing B code time synchronization precision and localization technology, in particular to the defects that the time synchronization precision is too low and localization cannot be realized, the invention realizes localization design of a B code time synchronization device on the basis of ensuring that the B code time synchronization precision reaches microsecond.
(II) technical scheme
In order to solve the technical problems, the invention provides a B code timing device of a domestic VPX framework, wherein the B code timing device adopts a structural framework of a double FPGA and a CPU, two FPGAs are respectively responsible for decoding logic and coding logic of a B code, and the two FPGAs are connected with a high-speed GTX interface through an RS422 interface; the CPU is responsible for managing the decoding and encoding processes of the B code, upper-layer software of the CPU is deployed in the CPU, and the CPU exchanges data with the two FPGA; the B code time synchronization device also comprises a first module which outputs 1 path of 2K1000 kilomega network through the RJ45 connector and can carry out configuration management and setting on the coding and decoding process of the B code; the device for time synchronization of the B code also comprises a second module which can output a 1-path 2K1000 management serial port through a DB9 connector and also can carry out configuration management and setting on the coding and decoding process of the B code;
the overall logic implementation of the B-code time synchronization device is divided into two parts, namely decoding and encoding:
decoding is realized by a first FPGA, after an input B code is converted into a TTL level, the B code enters a B code decoder of the first FPGA to perform decoding logic operation, then, time, month, day, minute and second information and second pulse signals which are calculated are sent to a time service register group of the first FPGA, the time service register group carries out first correction on the transmitted time information through an external high-precision temperature compensation crystal oscillator, then, the corrected time information is sent to upper-layer software of a CPU through a PCIE interface, and the time information after calculation can be displayed on a real-time monitoring interface of the upper-layer software. For the B code time information needing to be returned and checked, upper-layer software of the CPU informs a first FPGA through a PCIE interface in real time, and after the first FPGA obtains an instruction, the decoded time information is sent to a second FPGA through a high-speed GTX interface;
the coding is realized by the second FPGA, the source of the coding time is two places, one place is the time information which needs to be sent back after the first FPGA is decoded, and the other place is a real-time monitoring interface from upper-layer software of the CPU, and the time information which needs to be coded can be manually set to be a certain minute and a certain second at a certain time in a certain month and a certain day in a certain year; after receiving the time information, a code register of the second FPGA carries out trimming through an external temperature compensation crystal oscillator, then the coded information is sent to a B code coder of the second FPGA, and the B code coder codes the information of year, month, day, time, minute and second into time information of 1 frame per second consisting of 100 code elements according to a protocol of the B code and sends the time information to external equipment; after the B code encoder successfully encodes, in order to check to improve the time synchronization precision, the upper layer software of the CPU carries out scheduling, the encoded information is transmitted to the first FPGA through the 422 interface, the B code decoder of the first FPGA carries out decoding again on the received encoded information, and the second time verification is carried out to ensure that the time synchronization precision meets the requirements of the system.
Preferably, the two FPGAs are SMQ7K325T from Wien.
Preferably, the CPU is 2K1000 from Longxin, Beijing.
Preferably, the first module is the network PHY chip JSC88E1111 of the mid-power 32.
Preferably, the second module is a 232 transceiver SM3232 of the wiry corporation.
Preferably, the B code time synchronization device can realize the input and output of the multiple B codes 422.
Preferably, the two FPGAs are connected with the high-speed GTX interface through an RS422 interface.
Preferably, the CPU exchanges data with the two FPGAs through the PCIE bus.
The invention also provides a method for realizing B code time synchronization by using the device, which comprises the following steps:
step 1, the input B code enters a B code decoder of a first FPGA, and the B code decoder analyzes the B code into universal year, month, day, time, minute and second time information;
step 2, the B code decoder sends the resolved time information and the second pulse information to a time service register, the time service register carries out temperature compensation check on the time information, and then the time information is sent to a real-time monitoring interface of upper-layer software of a CPU through a PCIE interface to be displayed;
step 3, the time information needing to be returned and the time information of the upper layer software equipment are respectively sent to an encoding register group in the second FPGA through a GTX interface and a PCIE interface, the encoding register group carries out temperature compensation check on the time information again, and then the encoding information is sent to a B code encoder of the second FPGA;
step 4, the B code encoder encodes the general time information into 1 frame per second time information consisting of 100 code elements according to a B code protocol, and then transmits the time information to external equipment in a 422 mode;
step 5, for the B code information coded by the B code encoder, the upper layer software of the CPU needs to check the precision of the B code information, so that the upper layer software of the CPU informs the second FPGA to send the B code information to the B code decoder of the first FPGA through a special 422 interface;
step 6, decoding the received B code information by a B code decoder of the first FPGA, resolving the B code information into common time information, and checking and finishing the time information again;
and 7, configuring and managing the whole B code decoding and encoding process by upper-layer software of the CPU, and sequentially checking and finishing time information for 4 times so as to ensure that the time synchronization precision reaches microsecond level.
The invention also provides an application of the device in the technical field of domestic communication time setting.
(III) advantageous effects
The B code timing device adopts a high-speed VPX bus, all components adopt a domestic design, and decoding and encoding of multi-path B codes can be realized; the strategy of soft separation of encoding and decoding is adopted, namely the encoding and the decoding are respectively responsible for two independent FPGAs, and a mutual check return path exists, so that the time synchronization precision of the B code can be effectively ensured. The decoding FPGA and the encoding FPGA can realize return time synchronization after decoding the received B code and decoding and checking after self encoding through the unified allocation of the CPU 2K 1000; by adopting a redundancy design, the time synchronization precision can reach 1 microsecond.
Drawings
Fig. 1 is a schematic block diagram of a B-code time synchronization apparatus according to an embodiment of the present invention;
fig. 2 is a general logic block diagram of a B code pair based on the embodiment of the present invention.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
The method of the present invention is further described below with reference to the schematic block diagram of the apparatus for timing B code shown in fig. 1 and the general logic block diagram of timing B code shown in fig. 2.
As shown in fig. 1, the B code time synchronization device adopts a dual FPGA + CPU architecture, two FPGAs both adopt SMQ7K325T of the national wegian corporation and are respectively responsible for decoding logic and encoding logic of the B code, and the two FPGAs are connected with a high-speed GTX interface through an RS422 interface; the CPU selects 2K1000 of Beijing Loongson company to be responsible for managing the decoding and encoding processes of the B code, upper-layer protocol software is deployed in the 2K1000, and the CPU exchanges data with the two FPGAs through a high-speed PCIE bus; the B code time synchronization device also comprises a network PHY chip JSC88E1111 of the middle-power system 32, 1-channel 2K1000 kilomega network is output externally through an RJ45 connector, and the configuration management and the setting can be carried out on the coding and decoding process of the B code; the B code time synchronization device comprises a 232 transceiver SM3232 of the national Wien company, can output a 1-path 2K1000 management serial port through a DB9 connector, and can also carry out configuration management and setting on the coding and decoding processes of the B code; the device for time synchronization of the B code can realize the input and output of the multipath B code 422, the invention takes 32 paths as an example for illustration, and the specific route is not limited as long as the FPGA resource meets the condition.
As shown in fig. 2, the overall logic implementation of the B-code time-setting device is divided into two parts, decoding and encoding:
decoding is realized by a first FPGA, after an input B code is converted into a TTL level, the B code enters a B code decoder of the first FPGA to perform decoding logic operation, then, time, month, day, minute and second information and second pulse signals which are calculated are sent to a time service register group of the first FPGA, the time service register group carries out first correction on the transmitted time information through an external high-precision temperature compensation crystal oscillator, then, the corrected time information is sent to upper-layer software of a CPU through a PCIE interface, and the time information after calculation can be displayed on a real-time monitoring interface of the upper-layer software. For the B code time information needing to be returned and checked, upper-layer software of the CPU informs a first FPGA through a PCIE interface in real time, and after the first FPGA obtains an instruction, the decoded time information is sent to a second FPGA through a high-speed GTX interface;
the coding is realized by the second FPGA, the source of the coding time is two places, one place is the time information which needs to be sent back after the first FPGA is decoded, and the other place is a real-time monitoring interface from upper-layer software of the CPU, and the time information which needs to be coded can be manually set to be a certain minute and a certain second at a certain time in a certain month and a certain day in a certain year; after receiving the time information, a code register of the second FPGA carries out trimming through an external temperature compensation crystal oscillator, then the coded information is sent to a B code coder of the second FPGA, and the B code coder codes the information of year, month, day, time, minute and second into time information of 1 frame per second consisting of 100 code elements according to a protocol of the B code and sends the time information to external equipment; after the B code encoder successfully encodes, in order to check to improve the time synchronization precision, the upper layer software of the CPU carries out scheduling, the encoded information is transmitted to the first FPGA through the 422 interface, the B code decoder of the first FPGA carries out decoding again on the received encoded information, and the second time verification is carried out to ensure that the time synchronization precision meets the requirements of the system.
The specific steps of B code pair are as follows:
step 1, the input B code enters a B code decoder of a first FPGA, and the B code decoder analyzes the B code into universal year, month, day, time, minute and second time information;
step 2, the B code decoder sends the resolved time information and the second pulse information to a time service register, the time service register carries out temperature compensation check on the time information, and then the time information is sent to a real-time monitoring interface of upper-layer software of a CPU through a PCIE interface to be displayed;
step 3, the time information needing to be returned and the time information of the upper layer software equipment are respectively sent to an encoding register group in the second FPGA through a GTX interface and a PCIE interface, the encoding register group carries out temperature compensation check on the time information again, and then the encoding information is sent to a B code encoder of the second FPGA;
step 4, the B code encoder encodes the general time information into 1 frame per second time information consisting of 100 code elements according to a B code protocol, and then transmits the time information to external equipment in a 422 mode;
step 5, for the B code information coded by the B code encoder, the upper layer software of the CPU needs to check the precision of the B code information, so that the upper layer software of the CPU informs the second FPGA to send the B code information to the B code decoder of the first FPGA through a special 422 interface;
step 6, decoding the received B code information by a B code decoder of the first FPGA, resolving the B code information into common time information, and checking and finishing the time information again;
and 7, configuring and managing the whole B code decoding and encoding process by upper-layer software of the CPU, and sequentially checking and finishing time information for 4 times so as to ensure that the time synchronization precision reaches microsecond level.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A B code time synchronization device of a home-made VPX framework is characterized in that the B code time synchronization device adopts a structure framework of double FPGAs and a CPU, two FPGAs are respectively responsible for decoding logic and coding logic of the B code, and the two FPGAs are connected with a high-speed GTX interface through RS422 interfaces; the CPU is responsible for managing the decoding and encoding processes of the B code, upper-layer software of the CPU is deployed in the CPU, and the CPU exchanges data with the two FPGA; the B code time synchronization device also comprises a first module which outputs 1 path of 2K1000 kilomega network through the RJ45 connector and can carry out configuration management and setting on the coding and decoding process of the B code; the device for time synchronization of the B code also comprises a second module which can output a 1-path 2K1000 management serial port through a DB9 connector and also can carry out configuration management and setting on the coding and decoding process of the B code;
the overall logic implementation of the B-code time synchronization device is divided into two parts, namely decoding and encoding:
decoding is realized by a first FPGA, after an input B code is converted into a TTL level, the input B code enters a B code decoder of the first FPGA to perform decoding logic operation, then, the time, month, day, minute and second information and second pulse signals which are calculated are sent to a time service register group of the first FPGA, the time service register group carries out first correction on the transmitted time information through an external high-precision temperature compensation crystal oscillator, then, the corrected time information is sent to upper-layer software of a CPU through a PCIE interface, and the time information after calculation can be displayed on a real-time monitoring interface of the upper-layer software; for the B code time information needing loopback check, upper-layer software of a CPU (Central processing Unit) can inform a first FPGA (field programmable Gate array) in real time through a PCIE (peripheral component interface express) interface, and after the first FPGA obtains an instruction, the decoded time information is sent to a second FPGA through a high-speed GTX interface;
the coding is realized by the second FPGA, the source of the coding time is two places, one place is the time information which needs to be sent out in a loop after the first FPGA is decoded, and the other place is from a real-time monitoring interface of upper-layer software of the CPU, and the time information which needs to be coded can be manually set to be a certain minute and a certain second at a certain time in a certain month and a certain day in a certain year; after receiving the time information, a code register of the second FPGA carries out trimming through an external temperature compensation crystal oscillator, then the coded information is sent to a B code coder of the second FPGA, and the B code coder codes the information of year, month, day, time, minute and second into time information of 1 frame per second consisting of 100 code elements according to a protocol of the B code and sends the time information to external equipment; after the B code encoder successfully encodes, in order to check to improve the time synchronization precision, the upper layer software of the CPU carries out scheduling, the encoded information is transmitted to the first FPGA through the 422 interface, the B code decoder of the first FPGA carries out decoding again on the received encoded information, and the second time verification is carried out to ensure that the time synchronization precision meets the requirements of the system.
2. The apparatus of claim 1, wherein the two FPGAs are each selected from SMQ7K325T from wegian corporation.
3. The apparatus of claim 2, wherein the CPU is selected from 2K1000 available from longcore, beijing.
4. The apparatus of claim 3, wherein the first module is a network PHY chip JSC88E1111 of the mid-plane 32.
5. The apparatus of claim 4, wherein the second module is a 232 transceiver SM3232 from Wien.
6. The apparatus of claim 5 wherein the B code time synchronization means is capable of inputting and outputting multiple B codes 422.
7. The apparatus of claim 6, wherein the two FPGAs are connected via an RS422 interface and a high speed GTX interface.
8. The apparatus of claim 7, wherein the CPU exchanges data with the two FPGAs via a PCIE bus.
9. A method for synchronizing B code by using the apparatus of claim 8, comprising the steps of:
step 1, the input B code enters a B code decoder of a first FPGA, and the B code decoder analyzes the B code into universal year, month, day, time, minute and second time information;
step 2, the B code decoder sends the resolved time information and the second pulse information to a time service register, the time service register carries out temperature compensation check on the time information, and then the time information is sent to a real-time monitoring interface of upper-layer software of a CPU through a PCIE interface to be displayed;
step 3, the time information needing to be returned and the time information of the upper layer software equipment are respectively sent to an encoding register group in the second FPGA through a GTX interface and a PCIE interface, the encoding register group carries out temperature compensation check on the time information again, and then the encoding information is sent to a B code encoder of the second FPGA;
step 4, the B code encoder encodes the general time information into 1 frame per second time information consisting of 100 code elements according to a B code protocol, and then transmits the time information to external equipment in a 422 mode;
step 5, for the B code information coded by the B code encoder, the upper layer software of the CPU needs to check the precision of the B code information, so that the upper layer software of the CPU informs the second FPGA to send the B code information to the B code decoder of the first FPGA through a special 422 interface;
step 6, decoding the received B code information by a B code decoder of the first FPGA, resolving the B code information into common time information, and checking and finishing the time information again;
and 7, configuring and managing the whole B code decoding and encoding process by upper-layer software of the CPU, and sequentially checking and finishing time information for 4 times so as to ensure that the time synchronization precision reaches microsecond level.
10. A method in the field of homemade communication pairing, of a device according to any one of claims 1 to 8.
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| CN113805643A (en) * | 2021-10-18 | 2021-12-17 | 天津津航计算技术研究所 | Nationwide multi-bus multi-redundancy B code time synchronization device |
| CN114779931A (en) * | 2022-04-12 | 2022-07-22 | 兰州空间技术物理研究所 | Man-machine interaction platform for space navigation |
| CN116318167A (en) * | 2023-02-03 | 2023-06-23 | 国网四川省电力公司营销服务中心 | Device and method for converting direct current B code into pulse signal by double-channel signal hot standby input |
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| CN102508423A (en) * | 2011-11-21 | 2012-06-20 | 江苏西电南自智能电力设备有限公司 | IRIG-B (Inter-Range Instrumentation Group-B) time-setting method adopting enhanced capture module |
| CN105955398B (en) * | 2016-04-22 | 2019-05-17 | 南京国电南自维美德自动化有限公司 | A kind of system timing device and time synchronization method based on FPGA |
| CN205594496U (en) * | 2016-04-22 | 2016-09-21 | 南京国电南自美卓控制***有限公司 | System timing device based on FPGA |
| CN106788950A (en) * | 2016-11-28 | 2017-05-31 | 天津津航计算技术研究所 | The B yards of setting means based on VPX frameworks |
| CN106708169A (en) * | 2016-12-31 | 2017-05-24 | 中国舰船研究设计中心 | Multicomputer system time synchronization method based on VPX framework and device |
| CN108306722A (en) * | 2017-12-12 | 2018-07-20 | 天津津航计算技术研究所 | A kind of improved B code setting means based on VPX frameworks |
| CN208908445U (en) * | 2018-11-01 | 2019-05-28 | 北京华电众信技术股份有限公司 | B code clock synchronization equipment and substation equipment |
| CN109710565B (en) * | 2018-12-03 | 2023-07-14 | 天津津航计算技术研究所 | Logic realization system and method for VPX chassis B code time system |
| CN109614357A (en) * | 2018-12-06 | 2019-04-12 | 天津津航计算技术研究所 | It unites when a kind of VPX of high bandwidth multibus module |
| CN110161931A (en) * | 2019-06-08 | 2019-08-23 | 西安电子科技大学 | FPGA coding/decoding system and method based on GPS time service |
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