CN112185911A - 包含垂直集成电路的半导体组合件及其制造方法 - Google Patents
包含垂直集成电路的半导体组合件及其制造方法 Download PDFInfo
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- CN112185911A CN112185911A CN202010610562.3A CN202010610562A CN112185911A CN 112185911 A CN112185911 A CN 112185911A CN 202010610562 A CN202010610562 A CN 202010610562A CN 112185911 A CN112185911 A CN 112185911A
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Abstract
本申请案涉及包含垂直集成电路的半导体组合件及其制造方法。在一些实施例中,所述半导体组合件包括安装于逻辑装置之上的至少一个存储器装置及安置于所述存储器装置与所述逻辑装置之间的导热层、热绝缘体中介层或其组合。所述导热层包含经配置以跨水平平面传递热能的结构。所述热绝缘体中介层包含经配置以减少所述逻辑装置与所述存储器装置之间的热传递的结构。
Description
相关申请案的交叉参考
本申请案含有与由陈H.柳(Chan H.Yoo)、中野英一(Eiichi Nakano)及欧文R.费伊(Owen R.Fay)同时申请的题为“包含热电路的半导体组合件及其制造方法(SEMICONDUCTOR ASSEMBLIES INCLUDING THERMAL CIRCUITS AND METHODS OFMANUFACTURING THE SAME)”的美国专利申请案相关的标的,所述美国专利申请案经让渡给美光科技公司(Micron Technology,Inc.),通过代理档案号010829-9397.US00识别,且其全文以引用方式并入本文中。
技术领域
本发明涉及封装半导体组合件,例如存储器及处理器,且若干实施例涉及包含垂直集成电路的半导体组合件。
背景技术
半导体制造的当前趋势是制造具有用于计算机、手机、传呼机、个人数字助理及许多其它产品的更高密度组件的更小且更快装置。所有半导体装置都会产生热,且消散此热需要高性能装置的最佳及可靠操作。此外,随着速度及组件密度提高,热在许多产品中变成限制因素。举例来说,产生从80到100瓦特的高性能装置无法在额定电平下操作或会在消散足够热之后降级。因此,散热是用于制造微特征装置的重要设计因素。
图1A是常规半导体装置组合件100(“组合件100”)的俯视图,且图1B是沿着图1A的线1B-1B截取的图1A中展示的半导体装置组合件100的示意性横截面图。同时参考图1A及1B,组合件100包含经配置用于高性能操作的封装,例如3维图形处理及/或网络处理。如图1A及1B中说明,组合件100包含附接到衬底106(例如印刷电路板(PCB))的逻辑装置102及一组存储器装置104。逻辑装置102包含图形处理单元(GPU),且存储器装置104大体上包含高带宽存储器(HBM)装置。下文将描述关于HBM装置的细节。
组合件100包含安置于装置与衬底106之间的中介层108(例如硅中介层)。中介层108提供衬底102、逻辑装置102、存储器装置104或其组合之间的电界面路由。组合件100进一步包含安置于存储器装置104与中介层108之间的界面装置110。界面装置大体上包含经配置以促进对应存储器装置与其它装置(例如GPU)界接的硅裸片。
图1C说明常规存储器装置124(例如存储器装置104)的详细示意性横截面图。存储器装置124包含经配置以提供高性能存储器(例如随机存取存储器(RAM))界面的堆叠式封装。存储器装置124包含堆叠在一起的存储器裸片144及存储控制器142。裸片中的一或多者包含用于电耦合两个或两个以上裸片的穿硅通孔(TSV)。存储器装置124还包含包住一或多个裸片的囊封剂。
如图1A及1B中展示,存储器装置104及逻辑装置102彼此水平邻近且水平分离。换句话来说,存储器装置104及逻辑装置102并排布置,使得所述装置不重叠。存储器装置104及逻辑装置102在衬底106之上形成层。因为热通常向上行进,所以逻辑装置102及存储器装置104的水平布置会减少装置之间的热传递,例如从逻辑装置102到存储器装置104。当逻辑装置102是GPU时,其通常产生相对较大量的热能。因而,现存***通常不会在GPU之上堆叠任何热敏装置,例如存储器装置104。然而,水平布置会大幅增加组合件100的总占用面积。
发明内容
根据本申请案的一方面,提供一种半导体组合件。所述半导体组合件包括:逻辑装置;存储器装置,其安装于所述逻辑装置上方且与所述逻辑装置重叠;热管理层,其安置于所述逻辑装置与所述存储器装置之间,其中所述热管理层经配置以减少所述逻辑装置与所述存储器装置之间的垂直热能传递;及垂直延伸连接器,其电耦合所述存储器装置及所述逻辑装置,其中所述垂直延伸连接器跨所述热管理层垂直延伸。
根据本申请案的另一方面,提供一种半导体组合件。所述半导体组合件包括:衬底;图形处理单元(GPU),其安装于所述衬底上;存储器装置,其安装于逻辑装置上方且与所述逻辑装置重叠;热绝缘体中介层,其安置于所述GPU与所述存储器装置之间,且其中所述热管理层经配置以减少所述GPU与所述存储器装置之间的垂直热能传递;及垂直延伸连接器,其电耦合所述存储器装置及所述GPU,其中所述垂直延伸连接器跨所述热绝缘体中介层垂直延伸。
根据本申请案的又一方面,提供一种制造半导体封装的方法。所述方法包括:提供衬底;在所述衬底之上安装逻辑装置;在所述逻辑装置之上提供石墨烯层,其中:所述石墨烯层经配置以跨水平平面传递来自所述逻辑装置的热能,且所述石墨烯层包含孔;在所述石墨烯层之上附接热绝缘体中介层,其中所述热绝缘体中介层包含开口;及在所述热绝缘体中介层之上附接存储器装置且使所述存储器装置与所述逻辑装置重叠,其中附接所述存储器装置包含将垂直延伸连接器连接于所述存储器装置与所述逻辑装置之间,所述垂直延伸连接器垂直延伸穿过所述孔及所述开口。
附图说明
图1A是常规半导体装置组合件的俯视图。
图1B是沿着图1A的线1B-1B截取的图1A中展示的常规半导体装置组合件的示意性横截面图。
图1C是存储器装置的详细示意性横截面图。
图2A是根据本发明的实施例的沿着图2B的线2A-2A截取的半导体装置组合件的示意性横截面图。
图2B是根据本发明的实施例的沿着图2A的线2B-2B截取的图2A中展示的半导体装置组合件的示意性横截面图。
图3是说明根据本发明的实施例的制造半导体装置组合件的方法的流程图。
图4是包含根据本发明的实施例配置的半导体组合件的***的示意图。
具体实施方式
在以下描述中,论述众多特定细节以提供对本发明的实施例的详尽及使能描述。然而,相关领域的技术人员应认识到,可无需特定细节中的一或多者来实践本发明。在其它例子中,未展示或未详细描述通常与半导体装置相关联的众所周知结构或操作以避免使本发明的其它方面模糊。一般来说,应理解,除本文中揭示的那些特定实施例外的各种其它装置、***及方法也可在本发明的范围内。
根据本发明的半导体装置、封装及/或组合件的若干实施例可包含安装于逻辑装置(例如GPU)之上的一或多个存储器装置。垂直堆叠式结构可包含减少逻辑装置与存储器装置之间的热传递的热管理配置。
在一些实施例中,垂直堆叠式结构可包含逻辑装置上用于横向(例如水平)传递由逻辑装置产生的热的导热层(例如石墨烯结构)。散热器可经安装于逻辑装置之上且附接到导热层的***部分。因此,由逻辑装置产生的热可经由导热层路由到存储器装置周围且使用散热器来消散于存储器装置之上。
在一些实施例中,垂直堆叠式结构可包含逻辑装置与存储器装置之间的热绝缘中介层。热绝缘中介层可经配置以减少逻辑装置与存储器装置之间的热传递。在一或多个实施例中,热绝缘中介层可包含玻璃、陶瓷或其它热绝缘体。在一或多个实施例中,热绝缘中介层可包含经配置以进一步减少热传递的空腔。举例来说,空腔可维持用于减少热传递的真空条件。而且,空腔可经填充有可吸收热能的相变材料(PCM)。PCM可包含具有相对较高熔化热的基于吸收热能改变物理状态(经由(例如)融化、沸腾、凝固等)的物质。下文将描述关于热管理配置的细节。
根据所述技术的实施例,图2A是沿着图2B的线2A-2A截取的半导体装置组合件200(“组合件200”)的示意性横截面图,且图2B是沿着图2A的线2B-2B截取的图2A中展示的半导体装置组合件200的示意性横截面图。同时参考图2A及图2B,组合件200包含经配置用于高性能操作的封装,例如3维图形处理及/或网络处理。组合件200可包含安装于衬底206(例如印刷电路板(PCB))之上的逻辑装置202及一组存储器装置204。在一些实施例中,逻辑装置202可包含图形处理单元(GPU)。在一些实施例中,存储器装置204可包含高带宽存储器(HBM)装置。
如图2A中说明,组合件200可包含可安装于逻辑装置202之上的存储器装置204。存储器装置204可与逻辑装置202重叠,例如通过横向地位于逻辑装置202的***边界内。因此,组合件200的横向占用面积(即,图2B的图中的占用面积)可因消除横向邻近装置而小于图1A的常规组合件100的占用面积。组合件200还可包含电耦合存储器装置204与逻辑装置202的垂直电连接器208(例如接线及/或导电柱)。
组合件200可包含用于减少逻辑装置202与存储器装置204之间的热传递的热管理***。举例来说,组合件200的热管理***可包含附接到逻辑装置202的顶面的导热层210。在一些实施例中,导热层210可包含石墨烯结构,其包含沿着一或多个平面层布置(例如,沿着水平平面布置成六方晶格)的碳原子。因此,石墨烯结构可提供跨相对于逻辑装置202的上表面203的横向平面(例如,平行于逻辑装置202的上表面203的水平平面)的相对高效热能传递(例如,与金属材料相比)。在一或多个实施例中,石墨烯结构可使用粘合剂211附接到逻辑装置202。举例来说,石墨烯结构可包含一或多个凹入部或孔。在一些实施例中,粘合剂211(例如环氧树脂或热界面材料(TIM))可经施覆使得其填充孔且接触石墨烯结构上方及/或下方的结构(例如逻辑装置202、存储器装置204及/或中介层)。因此,当粘合剂材料固化(经由(例如)热、光及/或化学剂)时,石墨烯结构可至少部分由粘合剂211囊封且相对于垂直邻近结构附装。
组合件200的热管理***还可包含安装于逻辑装置202及存储器装置204之上的散热器212。散热器212可包含存储器装置204上方的散热部分(例如散热片)。散热部分可一体地连接到垂直延伸且附接到(经由(例如)TIM或其它导热粘合剂)散热器212的***部分的***管柱/壁。在一些实施例中,散热器212的***壁可直接附接(经由(例如)直接接触及/或TIM)到其***部分上的导热层210的顶面。在其它实施例中,散热器212的***壁可直接附接到导热层210的对应***表面。因而,来自逻辑装置202的热能优先流动通过散热器212的***部分且经由散热部分消散。因此,来自逻辑装置202的热可使用导热层210及散热器212导引到存储器装置204周围,借此减少逻辑装置202与存储器装置204之间的热传递(例如,从而抑制由逻辑装置202产生的热流动到存储器装置204)。
在一些实施例中,散热器212可包含至少部分由散热器212的***壁环绕/界定的开口213(例如,如图2B中展示)。举例来说,开口可允许空气跨逻辑装置202及/或存储器装置204流动以进一步移除热能。在其它实施例中,散热器212的***壁可沿着横向平面围绕/环绕存储器装置204。因此,散热器212与逻辑装置202及/或导热层210之间的接触量可增加。
作为热管理***的另一实例,组合件200可包含安置于逻辑装置202与存储器装置204的至少一部分之间的热绝缘中介层214。在一些实施例中,存储器装置204可直接附接到热绝缘中介层214,例如经由热绝缘粘合剂。在一些实施例中,热绝缘中介层214可在导热层210之上。
热绝缘中介层214可包含热绝缘体(例如玻璃或陶瓷材料),且经配置以阻断及减少逻辑装置202与存储器装置204之间的热传递。热绝缘中介层214可直接附加于存储器装置204之下,使得存储器装置204至少部分定位于热绝缘中介层214的***边缘内。换句话来说,热绝缘中介层214可向上延伸到或延伸超过存储器装置204的***边缘(例如,存储器装置204可完全在由热绝缘中介层214的横向***界定的边界内)。因此,热绝缘中介层214减少或消除逻辑装置202与存储器装置204之间的直接视线以阻断或至少阻碍(例如,减少)由逻辑装置202产生的热到达存储器装置204。
在一些实施例中,热绝缘中介层214可包含进一步减少热绝缘中介层214中或跨热绝缘中介层214的热能的吸收或传递的空腔216。举例来说,空腔216可处于真空条件下。而且,空腔216可经填充有绝缘气体及/或PCM。
热绝缘中介层214可包含开口215,垂直互连可穿过开口215以电连接垂直邻近结构。举例来说,电连接器208可定位于开口215内。在一些实施例中,热绝缘中介层214的开口215可直接在导热层210中的孔之上(例如,与孔水平重叠)。在其它实施例中,热绝缘中介层214的开口及导热层210中的孔可水平偏移以(例如)消除逻辑装置202与存储器装置204之间的任何垂直直接视线。因此,电连接器208可包含弯曲及/或可经对角对准以穿过热绝缘中介层214的开口及导热层210中的孔。
图3是说明根据本发明的实施例的制造半导体装置组合件的方法300的流程图。方法300可用于制造包含具有用于防止装置之间的热传递的热管理配置的一组堆叠式半导体装置的半导体装置组合件。举例来说,方法300可用于制造图2A的组合件200。
在框302,可提供衬底(例如图2A的衬底206)。举例来说,可提供PCB。在框304,可将逻辑装置(例如图2A的逻辑装置202)安装于衬底上。举例来说,GPU可基于使焊料回流及/或使安置于GPU与衬底之间的粘合剂固化来直接附接到衬底的顶面。
在框306,可在逻辑装置之上提供导热层(例如图2A的导热层210)。基于上述实例,可将石墨烯结构置放于GPU之上。可将导热粘合剂材料(例如环氧树脂及/或TIM)施覆于石墨烯结构的孔的下方、上方及/或其内。随后可固化粘合剂材料以将石墨烯结构附装到GPU。因此,石墨烯结构可通过导热粘合剂直接接触GPU且从GPU汲取热能。如上文描述,石墨烯结构可经配置以沿着平面(例如,水平地,如图2A中展示)传递热能。
在框308,可在导热层及逻辑装置之上提供热绝缘体中介层(例如图2A的热绝缘体中介层214)。如图2B中展示,热绝缘结构(例如玻璃、陶瓷等)可经置放于导热层之上。沿着方向(例如,在平行于逻辑装置202的顶面203的平面上),热绝缘体中介层可向上延伸到但不延伸超过导热层的***边缘。在一些实施例中,热绝缘结构可接触上述导热粘合剂。因此,如框310说明,各种结构(例如逻辑装置、石墨烯结构及/或热绝缘中介层)可相对于彼此附装。换句话来说,可固化导热粘合剂(经由(例如)化学剂、光、温度等),借此附装接触粘合剂的结构。
在框312,可在热绝缘体中介层及逻辑装置之上附接一或多个存储器装置(例如图2A的存储器装置204)。在一些实施例中,存储器装置可直接附接(经由(例如)粘合剂材料)到热绝缘体中介层。在一些实施例中,附接存储器装置可包含将存储器装置电耦合到逻辑装置。在框314,可将一或多个连接器(例如图2A的垂直延伸电连接器208)连接到存储器装置及/或逻辑装置。在一些实施例中,存储器装置及/或逻辑装置可经提供有附接到其的导体(例如接线及/或金属管柱)。导热层及/或热绝缘体中介层内可经提供有孔及/或开口。当置放/附接结构时,导体可经置放于孔及/或开口内。因此,热绝缘体中介层及/或导热层可沿着水平平面环绕导体。导体可延伸穿过孔/开口且跨导热层及/或热绝缘体中介层垂直延伸,且借此延伸于逻辑装置与存储器装置之间。导体可例如基于回流焊料连接到存储器装置及逻辑装置。
在一些实施例中,导热层及热绝缘体中介层中的开口/孔可对准。在其它实施例中,导热层及热绝缘体中介层中的开口/孔可经偏移使得孔/开口不同心或不彼此上下直接叠置,借此减少及/或消除存储器装置与逻辑装置之间的直接视线。导体可基于偏移至少部分沿着水平方向延伸。
在框316,可在逻辑装置202之上附接散热器/吸热器(例如图2A的散热器212)。散热器212可包含散热部分及垂直部分。散热器212可经置放使得散热部分在存储器装置204之上且垂直部分水平邻近存储器装置204的***侧。散热器212的垂直部分可垂直延伸经过/跨热绝缘体中介层214,且其可经附接到导热层。在一些实施例中,散热器212的垂直部分可附接(经由(例如)TIM)到导热层的顶面。在其它实施例中,散热器212的垂直部分可附接到导热层的对应***表面部分。
因此,上述热管理***减少及/或防止垂直堆叠式装置之间的热传递。因而,组合件200可包含安装于逻辑装置202(例如GPU)之上的存储器装置204(例如HBM装置),且无来自逻辑转置202的热影响存储器装置204,或反之亦然。因此,组合件200可提供比常规组合件(例如图1A的组合件100)减小的占用面积,同时减少逻辑装置202与存储器装置204之间的热传递。
上文参考图2A到3描述的半导体装置中的任一者可经并入到各种更大及/或更复杂***中的任何者中,其代表性实例是图4中示意性展示的***490。***490可包含半导体装置400(“装置400”)(例如半导体装置、封装及/或组合件)、电源492、驱动器494、处理器496及/或其它子***或组件498。装置400可包含大体上类似于上述那些装置的特征。所得***490可执行各种功能中的任何者,例如存储器存储、数据处理及/或其它合适功能。因此,代表性***490可包含(但不限于)手持式装置(例如移动电话、平板计算机、数字阅读器及数字音频播放器)、计算机及器具。***490的组件可容置于单个部件或分布于多个互连部件之上(例如,通过通信网络)。***490的组件还可包含远程装置及各种计算机可读媒体中的任何者。
本发明不希望是详尽的或将本发明限于本文中揭示的精确形式。尽管本文出于说明目的揭示了特定实施例,但相关领域的一般技术人员应认识到,可在不背离本发明的情况下进行各种等效修改。在一些案例中,未详细展示或描述众所周知的结构及功能以免不必要地使本发明的实施例的描述模糊。尽管方法步骤在本文中可按特定顺序呈现,但替代实施例可按不同顺序执行步骤。类似地,特定实施例的上下文中揭示的本发明的某些方面可组合或消除于其它实施例中。此外,虽然可能已在本发明的某些实施例的上下文中揭示与那些实施例相关联的优点,但其它实施例也可展现此类优点,且并非所有实施例都必然需要展现本文中揭示的此类优点或其它优点以落于本发明的范围内。因此,本发明及相关联技术可涵盖本文中未明确展示或描述的其它实施例,且本发明仅受所附权利要求书限制。
在本发明中,单数术语“一(a/an)”及“所述”包含复数指涉物,除非上下文另外明确指示。类似地,除非词“或”明确限于意味着两个或两个以上项的涉及列表中排除其它项的单个项,否则此列表中的“或”的使用应被解译为包含(a)列表中的任何单个项、(b)列表中的全部项或(c)列表中项的任何组合。另外,本文使用术语“包括”、“包含”及“具有”来意味着包含至少所述特征,使得不排除任何更大数目个相同特征及/或额外类型的其它特征。参考本文中的“一个实施例”、“实施例”、“一些实施例”或类似表达方式意味着结合实施例描述的特定特征、结构、操作或特性可包含于本发明的至少一个实施例中。因此,本文中出现此类片语或表达方式不一定都指代相同实施例。此外,各种特定特征、结构、操作或特性可以任何合适方式组合于一或多个实施例中。
Claims (20)
1.一种半导体组合件,其包括:
逻辑装置;
存储器装置,其安装于所述逻辑装置上方且与所述逻辑装置重叠;
热管理层,其安置于所述逻辑装置与所述存储器装置之间,其中所述热管理层经配置以减少所述逻辑装置与所述存储器装置之间的垂直热能传递;及
垂直延伸连接器,其电耦合所述存储器装置及所述逻辑装置,其中所述垂直延伸连接器跨所述热管理层垂直延伸。
2.根据权利要求1所述的半导体组合件,其中所述逻辑装置是图形处理单元GPU。
3.根据权利要求1所述的半导体组合件,其中所述存储器装置是高带宽存储器HBM装置。
4.根据权利要求1所述的半导体组合件,其中所述热管理层包含经配置以跨水平平面传递所述热能的导热层。
5.根据权利要求4所述的半导体组合件,其中所述导热层是石墨烯结构。
6.根据权利要求5所述的半导体组合件,其进一步包括安装于所述逻辑装置之上且耦合到所述石墨烯结构的***部分的散热器。
7.根据权利要求6所述的半导体组合件,其中所述散热器包含:
散热部分,其在所述存储器装置之上;及
***部分,其与所述散热部分成一体且朝向所述逻辑装置垂直延伸,其中所述***部分直接连接到所述石墨烯结构的所述***部分。
8.根据权利要求1所述的半导体组合件,其中所述热管理层包含经配置以减少所述逻辑装置与所述存储器装置之间的热传递的热绝缘体中介层。
9.根据权利要求8所述的半导体组合件,其中所述热绝缘体中介层包含玻璃。
10.根据权利要求8所述的半导体组合件,其中所述热绝缘体中介层包含陶瓷。
11.根据权利要求8所述的半导体组合件,其中所述热绝缘体中介层包含空腔。
12.根据权利要求11所述的半导体组合件,其中所述空腔经配置以维持所述空腔内的真空条件。
13.根据权利要求11所述的半导体组合件,其中所述热绝缘体中介层包含所述空腔内的气体。
14.根据权利要求11所述的半导体组合件,其中所述热绝缘体中介层包含所述空腔内的相变材料PCM。
15.一种半导体组合件,其包括:
衬底;
图形处理单元GPU,其安装于所述衬底上;
存储器装置,其安装于逻辑装置上方且与所述逻辑装置重叠;
热绝缘体中介层,其安置于所述GPU与所述存储器装置之间,且其中热管理层经配置以减少所述GPU与所述存储器装置之间的垂直热能传递;及
垂直延伸连接器,其电耦合所述存储器装置及所述GPU,其中所述垂直延伸连接器跨所述热绝缘体中介层垂直延伸。
16.根据权利要求15所述的半导体组合件,其进一步包括:
石墨烯层,其经配置以跨水平平面传递所述热能;及
散热器,其安装于所述GPU之上且耦合到所述石墨烯结构的***部分,所述散热器经配置以分散来自所述GPU的所述热能。
17.根据权利要求16所述的半导体组合件,其中:
所述热绝缘体中介层包含开口;
所述石墨烯层包含孔;且
所述垂直延伸连接器延伸穿过所述开口及所述孔。
18.根据权利要求17所述的半导体组合件,其中所述热绝缘体中介层的所述开口及所述石墨烯层的所述孔与穿过所述孔及所述开口两者的垂直线对准。
19.根据权利要求18所述的半导体组合件,其进一步包括所述孔中的至少部分囊封所述石墨烯层且将所述石墨烯层附装到所述GPU的聚合物粘合剂。
20.一种制造半导体封装的方法,所述方法包括:
提供衬底;
在所述衬底之上安装逻辑装置;
在所述逻辑装置之上提供石墨烯层,其中:
所述石墨烯层经配置以跨水平平面传递来自所述逻辑装置的热能,且
所述石墨烯层包含孔;
在所述石墨烯层之上附接热绝缘体中介层,其中所述热绝缘体中介层包含开口;及
在所述热绝缘体中介层之上附接存储器装置且使所述存储器装置与所述逻辑装置重叠,其中附接所述存储器装置包含将垂直延伸连接器连接于所述存储器装置与所述逻辑装置之间,所述垂直延伸连接器垂直延伸穿过所述孔及所述开口。
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US10872835B1 (en) * | 2019-07-03 | 2020-12-22 | Micron Technology, Inc. | Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same |
US20210104448A1 (en) * | 2019-10-08 | 2021-04-08 | Intel Corporation | Lateral heat removal for 3d stack thermal management |
CN112951991B (zh) * | 2021-02-22 | 2023-05-19 | 长江先进存储产业创新中心有限责任公司 | 相变存储器及其制备方法 |
KR20220162300A (ko) | 2021-06-01 | 2022-12-08 | 삼성전자주식회사 | 반도체 패키지 및 반도체 패키지의 제조방법 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101645453A (zh) * | 2008-08-06 | 2010-02-10 | 株式会社日立制作所 | 非易失性存储装置及其制造方法 |
CN102573279A (zh) * | 2010-11-17 | 2012-07-11 | 三星电子株式会社 | 半导体封装及其形成方法 |
US8704352B2 (en) * | 2009-01-08 | 2014-04-22 | Nae Hisano | Semiconductor device having a liquid cooling module |
CN103811436A (zh) * | 2012-11-09 | 2014-05-21 | 辉达公司 | 改进堆叠式封装结构中的逻辑芯片的热性能 |
CN103811356A (zh) * | 2012-11-09 | 2014-05-21 | 辉达公司 | 将cpu/gpu/逻辑芯片嵌入堆叠式封装结构的衬底的方法 |
CN103975428A (zh) * | 2011-11-14 | 2014-08-06 | 美光科技公司 | 具有增强型热管理的半导体裸片组合件、包含所述半导体裸片组合件的半导体装置及相关方法 |
CN105051891A (zh) * | 2013-03-27 | 2015-11-11 | 美光科技公司 | 包含导电底部填充材料的半导体装置及封装以及相关方法 |
US9287240B2 (en) * | 2013-12-13 | 2016-03-15 | Micron Technology, Inc. | Stacked semiconductor die assemblies with thermal spacers and associated systems and methods |
CN106463469A (zh) * | 2014-04-01 | 2017-02-22 | 美光科技公司 | 具有经分割逻辑的堆叠式半导体裸片组合件以及相关联***及方法 |
CN108074874A (zh) * | 2016-11-14 | 2018-05-25 | 原相科技股份有限公司 | 光学组件封装结构 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101390341B1 (ko) | 2007-11-15 | 2014-04-30 | 삼성전자주식회사 | 상변화 메모리 소자 |
US8203134B2 (en) | 2009-09-21 | 2012-06-19 | Micron Technology, Inc. | Memory devices with enhanced isolation of memory cells, systems including same and methods of forming same |
US9728481B2 (en) * | 2011-09-07 | 2017-08-08 | Nvidia Corporation | System with a high power chip and a low power chip having low interconnect parasitics |
WO2014185088A1 (ja) * | 2013-05-17 | 2014-11-20 | 富士通株式会社 | 半導体装置とその製造方法、及び電子機器 |
JP6196815B2 (ja) * | 2013-06-05 | 2017-09-13 | 新光電気工業株式会社 | 冷却装置及び半導体装置 |
JP6138603B2 (ja) * | 2013-06-24 | 2017-05-31 | 新光電気工業株式会社 | 冷却装置、冷却装置の製造方法及び半導体装置 |
US10714425B2 (en) * | 2016-09-13 | 2020-07-14 | Apple Inc. | Flexible system integration to improve thermal properties |
CN110621953B (zh) | 2017-05-08 | 2022-04-01 | 开文热工科技公司 | 热管理平面 |
KR102439761B1 (ko) * | 2017-12-22 | 2022-09-02 | 삼성전자주식회사 | 전자 장치 및 전자 장치의 제조 방법 |
KR102574453B1 (ko) * | 2018-09-03 | 2023-09-04 | 삼성전자 주식회사 | 우수한 열 방출 특성 및 전자기 차폐 특성을 갖는 반도체 패키지 |
US10872835B1 (en) * | 2019-07-03 | 2020-12-22 | Micron Technology, Inc. | Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same |
-
2019
- 2019-07-03 US US16/503,363 patent/US10872835B1/en active Active
-
2020
- 2020-06-30 CN CN202010610562.3A patent/CN112185911A/zh active Pending
- 2020-12-08 US US17/115,716 patent/US11664291B2/en active Active
-
2023
- 2023-05-22 US US18/200,173 patent/US20230307309A1/en active Pending
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101645453A (zh) * | 2008-08-06 | 2010-02-10 | 株式会社日立制作所 | 非易失性存储装置及其制造方法 |
US8704352B2 (en) * | 2009-01-08 | 2014-04-22 | Nae Hisano | Semiconductor device having a liquid cooling module |
CN102573279A (zh) * | 2010-11-17 | 2012-07-11 | 三星电子株式会社 | 半导体封装及其形成方法 |
CN103975428A (zh) * | 2011-11-14 | 2014-08-06 | 美光科技公司 | 具有增强型热管理的半导体裸片组合件、包含所述半导体裸片组合件的半导体装置及相关方法 |
CN103988296A (zh) * | 2011-11-14 | 2014-08-13 | 美光科技公司 | 具有多个热路径的堆叠半导体裸片组合件及相关联***和方法 |
CN103811436A (zh) * | 2012-11-09 | 2014-05-21 | 辉达公司 | 改进堆叠式封装结构中的逻辑芯片的热性能 |
CN103811356A (zh) * | 2012-11-09 | 2014-05-21 | 辉达公司 | 将cpu/gpu/逻辑芯片嵌入堆叠式封装结构的衬底的方法 |
CN105051891A (zh) * | 2013-03-27 | 2015-11-11 | 美光科技公司 | 包含导电底部填充材料的半导体装置及封装以及相关方法 |
US9287240B2 (en) * | 2013-12-13 | 2016-03-15 | Micron Technology, Inc. | Stacked semiconductor die assemblies with thermal spacers and associated systems and methods |
CN106463469A (zh) * | 2014-04-01 | 2017-02-22 | 美光科技公司 | 具有经分割逻辑的堆叠式半导体裸片组合件以及相关联***及方法 |
CN108074874A (zh) * | 2016-11-14 | 2018-05-25 | 原相科技股份有限公司 | 光学组件封装结构 |
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