CN112151369A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN112151369A
CN112151369A CN201910572512.8A CN201910572512A CN112151369A CN 112151369 A CN112151369 A CN 112151369A CN 201910572512 A CN201910572512 A CN 201910572512A CN 112151369 A CN112151369 A CN 112151369A
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substrate
layer
polysilicon
polysilicon film
forming
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潘璋
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/298—Semiconductor material, e.g. amorphous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer

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  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
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  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Weting (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate; forming a polysilicon film on the substrate; and removing the polysilicon film with partial thickness by adopting an etching process to form a polysilicon layer, wherein the etching liquid is a mixed liquid of hydrofluoric acid and an ozone solution, and the volume ratio of the hydrofluoric acid to the ozone solution is 1: 4-4: 1. The invention is helpful to improve the etching precision and can improve the flatness of the surface of the polycrystalline silicon layer.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
Polysilicon is a form of elemental silicon. When molten elemental silicon solidifies under undercooling conditions, the silicon atoms are arranged in the form of a diamond lattice into a plurality of crystal nuclei, which grow into grains with different crystal plane orientations, and these grains are combined, i.e., crystallized into polycrystalline silicon.
In the fabrication process of semiconductor structures, polysilicon materials may be used to form a hard mask layer or a masking layer. In order to make the thickness of the formed polysilicon layer meet the process requirements, the polysilicon material needs to be etched.
However, the existing etching process still needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a polysilicon film on the substrate; and removing the polysilicon film with partial thickness by adopting an etching process to form a polysilicon layer, wherein the etching liquid is a mixed liquid of hydrofluoric acid and an ozone solution, and the volume ratio of the hydrofluoric acid to the ozone solution is 1: 4-4: 1.
Optionally, HF and H in the hydrofluoric acid2The volume ratio of O is 1: 200.
Optionally, the percentage concentration of the ozone solution is 30 ppm.
Optionally, the base includes a substrate and a device layer, and the device layer covers the surface of the substrate; in the process of forming the polysilicon film, the polysilicon film is formed on the surface of the device layer.
Optionally, the process time of the etching process is less than 30min, and the process time is greater than or equal to 1 min.
Optionally, the temperature of the etching solution is 25 ℃ to 50 ℃.
Optionally, the thickness of the polysilicon layer is less than
Figure BDA0002111272290000011
Optionally, in the process of forming the polysilicon film, the polysilicon film has a thickness of
Figure BDA0002111272290000021
Figure BDA0002111272290000022
Correspondingly, the invention also provides a semiconductor structure formed by adopting the method, which comprises the following steps: a substrate; and the polycrystalline silicon layer is positioned on the substrate.
Optionally, the substrate includes a substrate and a device layer, the device layer covers the surface of the substrate, and the polysilicon layer covers the surface of the device layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the etching liquid is a mixed liquid of hydrofluoric acid and ozone solution. Wherein the ozone solution is used to oxidize a portion of the thickness of the polysilicon film to silicon dioxide. Hydrofluoric acid is used to react with silicon dioxide to form a reaction product that is soluble in water, thereby removing a portion of the thickness of the polysilicon film. The volume ratio of the hydrofluoric acid to the ozone solution is 1: 4-4: 1. On one hand, the volume ratio of the hydrofluoric acid is small, so that the etching rate is slow, the accuracy of the etching process is improved, and the flatness of the surface of the etched polycrystalline silicon layer can be improved. On the other hand, the etching process time is appropriate, and the phenomenon that the etching process consumes too long time is avoided.
Drawings
Fig. 1 to fig. 3 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
Analysis is now performed in conjunction with a method of forming a semiconductor structure, comprising: providing a substrate (not shown); forming a polysilicon film (not shown) on the substrate; oxidizing the polysilicon film with partial thickness to form a silicon oxide layer, and taking the polysilicon film with residual thickness as a polysilicon layer; and etching to remove the silicon oxide layer.
The oxidation treatment process and the etching process are carried out in steps, so that the process efficiency is low, and in addition, the process control difficulty is increased, so that the formation quality of the polycrystalline silicon layer is influenced.
The inventors have studied the method for forming the above semiconductor structure, and as a result of creative efforts, they have noticed that a polysilicon film of a partial thickness can be etched by etching with a mixed solution of hydrofluoric acid and an ozone solution. By controlling the volume ratio of the hydrofluoric acid to the ozone solution, the rate of the etching process can be controlled. When the volume ratio of the hydrofluoric acid to the ozone solution is 1: 4-4: 1, the etching process can be conveniently controlled to improve the etching precision, and in addition, the surface roughness of the polycrystalline silicon layer can be reduced, so that the forming quality of the polycrystalline silicon layer is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to fig. 3 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 1, a substrate 100 is provided.
In this embodiment, the base 100 includes a substrate 110 and a device layer 120, and the device layer 120 covers a surface of the substrate 110.
The substrate 110 is made of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the substrate 110 is made of silicon.
The material of the device layer 120 is silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the device layer 120 is silicon oxide.
The device layer 120 has transistors (not shown) or passive devices (not shown).
In this embodiment, the device layer 120 is formed by a chemical vapor deposition process. In other embodiments, the device layer may also be formed using an atomic layer deposition process or a physical vapor deposition process.
Referring to fig. 2, a polysilicon film 200 is formed on the substrate 100.
In this embodiment, a polysilicon film 200 is formed on the surface of the device layer 120.
The polysilicon film 200 covers the surface of the device layer 120, and the polysilicon film 200 can protect the surface of the device layer 120 and prevent the surface of the device layer 120 from being directly exposed to a subsequent process environment, so as to prevent the surface of the device layer 120 from being damaged or contaminated.
And removing the polysilicon film 200 with partial thickness by using an etching process, wherein the thickness of the polysilicon film 200 is kept at a fixed value if the polysilicon film is thickThe excessive thickness of the silicon film 200 may cause the excessive thickness of the polysilicon film 200 to be removed during the etching process, resulting in an excessively long etching process time. If the thickness of the polysilicon film 200 is too small, the polysilicon film 200 is easily etched and removed in the subsequent process of etching the polysilicon film 200, so that the surface of the device layer 120 is directly exposed to the subsequent process environment. In this embodiment, the thickness H1 of the polysilicon film 200 is
Figure BDA0002111272290000031
Referring to fig. 3, the polysilicon film 200 (refer to fig. 2) is partially removed by an etching process to form a polysilicon layer 300.
The polysilicon film 200 of a predetermined thickness is etched away so that the thickness of the formed polysilicon layer 300 meets the process requirements.
If the thickness of the polysilicon layer 300 is too large, the polysilicon layer 300 occupies too large space, which affects the subsequent processes; if the thickness of the polysilicon layer 300 is too small, the protection effect of the polysilicon layer 300 on the surface of the device layer 120 is affected. In this embodiment, the thickness H2 of the polysilicon layer 300 is less than
Figure BDA0002111272290000041
In this embodiment, in the etching process, the etching solution is a mixed solution of hydrofluoric acid and an ozone solution. The etching process comprises two stages, which are explained in detail below.
In the first stage: the ozone reacts with the material of the partial-thickness polysilicon film 200 to cause oxidation reaction, so that the partial-thickness polysilicon material is converted into silicon oxide. The chemical reaction formula is as follows:
Si+2O3+H2O→SiO2+2O2+H2O。
the second stage is as follows: hydrogen fluoride chemically reacts with the converted silicon oxide to produce H2SiF6And H2O，H2SiF6Dissolved in water. The chemical reaction formula is as follows:
SiO2+6HF→H2SiF6+2H2O。
the above two stages are cyclically performed until the thickness of the polysilicon film 200 removed by etching reaches a predetermined value. The overall chemical reaction formula is:
Si+2O3+6HF→2O2+H2SiF6+2H2O。
if HF and H in the hydrofluoric acid2The volume ratio of O is too large, which causes the hydrofluoric acid concentration to be too high, resulting in a violent chemical reaction in the second stage, which makes the etching rate too fast, and over-etching easily occurs, resulting in etching away the polysilicon film 200 with a thickness exceeding a predetermined value. In addition, too fast etching rate may affect the flatness of the surface of the polysilicon layer 300 after the etching process is finished. If HF and H in the hydrofluoric acid2The too small volume proportion of O leads to too low concentration of hydrofluoric acid, and the chemical reaction between hydrogen fluoride and the silicon oxide obtained by conversion is too slow, thus the etching process time is too long. In this embodiment, HF and H in the hydrofluoric acid2The volume ratio of O is 1: 200.
If the percentage concentration of the ozone solution is too high, the oxidation reaction rate is too fast, so that the material of the polysilicon film 200 exceeding the predetermined thickness undergoes the oxidation reaction, and the surface of the formed polysilicon film 300 has silicon oxide residues, which affects the subsequent processes. If the percentage concentration of the ozone solution is too low, the oxidation reaction rate is too slow, and the progress efficiency of the etching process is influenced. In this embodiment, HF and H in the hydrofluoric acid2The volume ratio of O is 1: 200.
If the volume ratio of the hydrofluoric acid to the ozone solution is too large, the concentration of the hydrogen fluoride in the mixed solution is too high, which causes a violent chemical reaction in the second stage, so that the etching rate is too fast, the accuracy of the etching process is affected, and the thickness of the formed polysilicon layer 300 is easily too small. In addition, the too fast etching rate may cause the surface of the formed polysilicon layer 300 to have a higher roughness, which may affect the subsequent processes. In this embodiment, the volume ratio of the hydrofluoric acid to the ozone solution is 1:4 to 4: 1.
If the etching process is too long, the polysilicon film 200 with a thickness exceeding the predetermined thickness is etched away, so that the thickness of the formed polysilicon layer 300 is too thin, which affects the protection effect of the polysilicon layer 300 on the surface of the device layer 120. If the process time of the etching process is too short, the polysilicon film 200 with the thickness lower than the predetermined thickness is etched and removed, so that the thickness of the formed polysilicon layer 300 is too thick, and the occupied space of the polysilicon layer 300 is too large, thereby causing difficulty in the subsequent process. In this embodiment, the process time of the etching process is less than 30min, and the process time is greater than or equal to 1 min.
If the temperature of the etching solution is too high, the chemical reactions in the two stages are too violent, over-etching is easy to occur, and the thickness of the formed polycrystalline silicon layer 300 is too thin; in addition, the surface of the formed polysilicon layer 300 is also rough, which reduces the formation quality of the polysilicon layer 300. If the temperature of the etching solution is too low, the chemical reactions in the two stages are slow, and even the chemical reactions are difficult to trigger, so that the etching rate is influenced. In this embodiment, the temperature of the etching solution is 25 ℃ to 50 ℃.
Referring to fig. 3, the invention also provides a semiconductor structure obtained by the forming method. The semiconductor structure includes: a substrate 100; a polysilicon layer 300 on the substrate 100.
In this embodiment, the substrate 100 includes a substrate 110 and a device layer 120, the device layer 120 covers the surface of the substrate 110, and the polysilicon layer 300 covers the surface of the device layer 120.
The substrate 110 is made of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the substrate 110 is made of silicon.
The material of the device layer 120 is silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the device layer 120 is silicon oxide.
The device layer 120 has transistors or passive devices therein.
The polysilicon layer 300 can protect the surface of the device layer 120 from being contaminated or damaged by the surface of the device layer 120.
In this embodiment, the thickness H2 of the polysilicon layer 300 is less than
Figure BDA0002111272290000061
The thickness of the polysilicon layer 300 is proper, so that on one hand, the protection effect of the polysilicon layer 300 on the surface of the device layer 120 can be ensured; on the other hand, the polysilicon layer 300 occupies a suitable space, thereby facilitating the subsequent processes.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a polysilicon film on the substrate;
and removing the polysilicon film with partial thickness by adopting an etching process to form a polysilicon layer, wherein the etching liquid is a mixed liquid of hydrofluoric acid and an ozone solution, and the volume ratio of the hydrofluoric acid to the ozone solution is 1: 4-4: 1.
2. The method of claim 1, wherein the HF and H in the hydrofluoric acid are2The volume ratio of O is 1: 200.
3. The method of forming of claim 1, wherein the ozone solution has a percent concentration of 30 ppm.
4. The method of forming of claim 1, wherein the base comprises a substrate and a device layer, the device layer overlying the substrate surface; in the process of forming the polysilicon film, the polysilicon film is formed on the surface of the device layer.
5. The forming method of claim 1, wherein a process time of the etching process is less than 30min and is greater than or equal to 1 min.
6. The method of claim 1, wherein the etching solution is at a temperature of 25 ℃ to 50 ℃.
7. The method of forming of claim 1, wherein the polysilicon layer has a thickness less than that of the polysilicon layer
Figure FDA0002111272280000011
Figure FDA0002111272280000012
8. The method according to claim 1, wherein in the process of forming the polysilicon film, the polysilicon film has a thickness of
Figure FDA0002111272280000013
9. A semiconductor structure, comprising:
a substrate;
and the polycrystalline silicon layer is positioned on the substrate.
10. The semiconductor structure of claim 9, wherein the base comprises a substrate and a device layer, the device layer covers the surface of the substrate, and the polysilicon layer covers the surface of the device layer.
CN201910572512.8A 2019-06-28 2019-06-28 Semiconductor structure and forming method thereof Pending CN112151369A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000040115A (en) * 1998-12-17 2000-07-05 김영환 Method for determining distribution of ozone
KR20000044907A (en) * 1998-12-30 2000-07-15 김영환 Fabrication method of gate word lines for semiconductor device
KR20070091396A (en) * 2006-03-06 2007-09-11 주식회사 하이닉스반도체 Method for forming patterns of semiconductor device
CN103295905A (en) * 2012-06-29 2013-09-11 上海天马微电子有限公司 Semiconductor device and forming method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000040115A (en) * 1998-12-17 2000-07-05 김영환 Method for determining distribution of ozone
KR20000044907A (en) * 1998-12-30 2000-07-15 김영환 Fabrication method of gate word lines for semiconductor device
KR20070091396A (en) * 2006-03-06 2007-09-11 주식회사 하이닉스반도체 Method for forming patterns of semiconductor device
CN103295905A (en) * 2012-06-29 2013-09-11 上海天马微电子有限公司 Semiconductor device and forming method thereof

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