CN112051963A - Data writing method, memory control circuit unit and memory storage device - Google Patents

Data writing method, memory control circuit unit and memory storage device Download PDF

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Publication number
CN112051963A
CN112051963A CN201910489531.4A CN201910489531A CN112051963A CN 112051963 A CN112051963 A CN 112051963A CN 201910489531 A CN201910489531 A CN 201910489531A CN 112051963 A CN112051963 A CN 112051963A
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data
memory
unit
physical
cells
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CN201910489531.4A
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CN112051963B (en
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林纬
许祐诚
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits

Abstract

A data writing method, a memory control circuit unit and a memory storage device. The method comprises the following steps: receiving a plurality of data; respectively writing the data into first entity erasing units by using a multi-page programming mode; writing at least one first data in the plurality of data into a second physically erased cell by using a single page programming mode; verifying data stored in the first physically erased cell; and performing a write operation on a third physically erased cell using a multi-page programming mode according to the first data and the plurality of data when the verification fails.

Description

Data writing method, memory control circuit unit and memory storage device
Technical Field
The invention relates to a data writing method, a memory control circuit unit and a memory storage device.
Background
Digital cameras, cell phones, and MP3 have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of non-volatility, power saving, small volume, no mechanical structure, high read-write speed and the like, the rewritable non-volatile memory is most suitable for portable electronic products such as notebook computers. A solid state disk is a memory storage device using a flash memory as a storage medium. Therefore, the flash memory industry has become a very popular part of the electronics industry in recent years.
The NAND flash memory is classified into a Single Level Cell (SLC) NAND flash memory, a Multi-Level Cell (MLC) NAND flash memory, and a Triple Level Cell (TLC) NAND flash memory according to the number of bits that each memory Cell can store, wherein each memory Cell of the SLC NAND flash memory can store 1 bit of data (i.e., "1" and "0"), each memory Cell of the MLC NAND flash memory can store 2 bits of data, and each memory Cell of the TLC NAND flash memory can store 3 bits of data.
The memory management circuit can write to the rewritable nonvolatile memory module by using a single-page programming mode or a multi-page programming mode. The memory cell programmed in the single page program mode is used to store 1 bit of data. Memory cells programmed in a page program mode are used to store multiple bits of data.
Assume that the memory management circuit is programmed to write data of a write command to the rewritable nonvolatile memory module using the multi-page programming mode. However, the reliability of data written using the multi-page program mode is lower compared to the single-page program mode. In other words, data written using the multi-page programming mode may have write failures, which may result in the written data having uncorrectable error bits. Therefore, in the conventional method, when the memory management circuit is preset to write the data of the write command to the rewritable non-volatile memory module using the multi-page programming mode, the memory management circuit also writes all the data corresponding to the write command to at least one physical erase unit in the rewritable non-volatile memory module using the single-page programming mode. Thereafter, the memory management circuit verifies all data of the write command written in the multi-page programming mode to determine whether a write failure occurs while writing to one (or some) of the physical program cells. Assuming that a physical programming unit is written with data using the multi-page programming mode, when the data stored in the physical programming unit has uncorrectable error bits (i.e., a write failure occurs), the memory management circuit performs data recovery using the data previously written using the single-page programming mode. That is, in the aforementioned example, the single page programming mode is used for restoring and backing up data.
It should be noted that the process of backing up data using the single page programming mode takes time and space for the rewritable nonvolatile memory module. In addition, it takes a lot of time for the memory management circuit to verify all the data of the write command written in the multi-page programming mode to determine whether a write failure occurs when writing to a certain (or some) physical program unit.
Disclosure of Invention
The invention provides a data writing method, a memory control circuit unit and a memory storage device, which can reduce the time required by data writing and verification.
The invention provides a data writing method, which is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units, and the data writing method comprises the following steps: receiving a plurality of data; writing the plurality of data to a first one of the plurality of physically-erased cells using a multi-page programming mode; writing at least one first datum of the plurality of data to a second physically erased cell of the plurality of physically erased cells using a single page programming mode; verifying the plurality of data stored in the first physically erased cell; and when the verification fails, performing a write operation on a third physically erased cell of the plurality of physically erased cells according to the first data and the plurality of data by using the multi-page programming mode.
In an embodiment of the invention, the probability of the write failure of at least one first physical program cell for storing the first data in the first physical erase cell is higher than the probability of the write failure of other physical program cells in the first physical erase cell.
In an embodiment of the invention, the method comprises: verifying data stored in the first physical programming cell; when the data in the first entity programming unit has no bits which can not be corrected, marking at least one second entity programming unit for storing the first data in the second entity erasing unit as invalid; and when a second data in the first physical programming unit has bits which cannot be corrected, writing the data in the other physical programming units in the first physical erasing unit and the data in the second physical programming unit in the second physical erasing unit into the third physical erasing unit by using the multi-page programming mode.
In an embodiment of the invention, the amount of the first data is thirty percent of the amount of the plurality of data.
In an embodiment of the invention, the rewritable nonvolatile memory module includes n word lines, the n word lines are arranged according to a sequence, and a plurality of memory cells on a same word line in the n word lines form at least one of the plurality of physical programming units. Wherein a plurality of first memory cells of the plurality of memory cells form the first physical programming unit, the plurality of first memory cells being located on at least one first word line of the n word lines, wherein n is a positive integer greater than zero.
In an embodiment of the present invention, the first word line is located in 0 th to i th word lines, j th to k th word lines or h th to n-1 th word lines of the n word lines. Wherein i, j, k and h are respectively positive integers which are larger than zero and are mutually discontinuous, i is smaller than j, j is smaller than k, k is smaller than h and h is smaller than n.
In an embodiment of the present invention, the step of receiving the plurality of data includes: receiving at least one writing instruction issued by the host system, wherein the writing instruction is used for indicating that the plurality of data are written into the rewritable nonvolatile memory module; and temporarily storing the data into a buffer memory.
The invention provides a memory control circuit unit, which is used for controlling a rewritable nonvolatile memory module and comprises: a host interface, a memory interface, and memory management circuitry. The host interface is used for electrically connecting to a host system. The memory interface is electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of entity erasing units, and each entity erasing unit in the plurality of entity erasing units has a plurality of entity programming units. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used for executing the following steps: receiving a plurality of data; writing the plurality of data to a first one of the plurality of physically-erased cells using a multi-page programming mode; writing at least one first datum of the plurality of data to a second physically erased cell of the plurality of physically erased cells using a single page programming mode; verifying the plurality of data stored in the first physically erased cell; and when the verification fails, performing a write operation on a third physically erased cell of the plurality of physically erased cells according to the first data and the plurality of data by using the multi-page programming mode.
In an embodiment of the invention, the probability of the write failure of at least one first physical program cell for storing the first data in the first physical erase cell is higher than the probability of the write failure of other physical program cells in the first physical erase cell.
In an embodiment of the invention, the memory management circuit is further configured to verify data stored in the first physical program unit. When the data in the first physical programming unit has no uncorrectable bits, the memory management circuit is further configured to mark at least one second physical programming unit in the second physical erasing unit for storing the first data as invalid. When there is an uncorrectable bit in a second datum of the first physical program cell, the memory management circuit is further configured to write the third physical erase cell in the multi-page programming mode according to the data in the other physical program cells of the first physical erase cell and the data in the second physical program cell of the second physical erase cell.
In an embodiment of the invention, the amount of the first data is thirty percent of the amount of the plurality of data.
In an embodiment of the invention, the rewritable nonvolatile memory module includes n word lines, the n word lines are arranged according to a sequence, and a plurality of memory cells on a same word line in the n word lines form at least one of the plurality of physical programming units. A plurality of first memory cells of the plurality of memory cells form the first physical programming unit, the plurality of first memory cells are located on at least one first word line of the n word lines, wherein n is a positive integer greater than zero.
In an embodiment of the present invention, the first word line is located in 0 th to i th word lines, j th to k th word lines or h th to n-1 th word lines of the n word lines. Wherein i, j, k and h are respectively positive integers which are larger than zero and are mutually discontinuous, i is smaller than j, j is smaller than k, k is smaller than h and h is smaller than n.
In an embodiment of the invention, in the operation of receiving the plurality of data, the memory management circuit is further configured to receive at least one write command issued by the host system, where the write command is used to instruct to write the plurality of data into the rewritable nonvolatile memory module. The memory management circuit is further configured to temporarily store the plurality of data into a buffer memory.
The invention provides a memory storage device, comprising: the interface unit, the rewritable nonvolatile memory module and the memory control circuit unit are connected. The connection interface unit is used for electrically connecting to a host system. The rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for executing the following operations: receiving a plurality of data; writing the plurality of data to a first one of the plurality of physically-erased cells using a multi-page programming mode; writing at least one first datum of the plurality of data to a second physically erased cell of the plurality of physically erased cells using a single page programming mode; verifying the plurality of data stored in the first physically erased cell; and when the verification fails, performing a write operation on a third physically erased cell of the plurality of physically erased cells according to the first data and the plurality of data by using the multi-page programming mode.
In an embodiment of the invention, the probability of the write failure of at least one first physical program cell for storing the first data in the first physical erase cell is higher than the probability of the write failure of other physical program cells in the first physical erase cell.
In an embodiment of the invention, the memory control circuit unit is further configured to verify data stored in the first physical programming unit. When there is no uncorrectable bit in the data in the first physical programming unit, the memory control circuit unit is further configured to mark at least one second physical programming unit in the second physical erasing unit for storing the first data as invalid. When there is an uncorrectable bit in a second data in the first physical program cell, the memory control circuit unit is further configured to write the third physical erase cell in the multi-page programming mode according to the data in the other physical program cells in the first physical erase cell and the data in the second physical program cell in the second physical erase cell.
In an embodiment of the invention, the amount of the first data is thirty percent of the amount of the plurality of data.
In an embodiment of the invention, the rewritable nonvolatile memory module includes n word lines, the n word lines are arranged according to a sequence, and a plurality of memory cells on a same word line in the n word lines form at least one of the plurality of physical programming units. A plurality of first memory cells of the plurality of memory cells form the first physical programming unit, the plurality of first memory cells are located on at least one first word line of the n word lines, wherein n is a positive integer greater than zero.
In an embodiment of the present invention, the first word line is located in 0 th to i th word lines, j th to k th word lines or h th to n-1 th word lines of the n word lines. Wherein i, j, k and h are respectively positive integers which are larger than zero and are mutually discontinuous, i is smaller than j, j is smaller than k, k is smaller than h and h is smaller than n.
In an embodiment of the invention, in the operation of receiving the plurality of data, the memory control circuit unit is further configured to receive at least one write command issued by the host system, where the write command is used to instruct to write the plurality of data into the rewritable nonvolatile memory module. The memory control circuit unit is further used for temporarily storing the data into a buffer memory.
Based on the above, the data writing method, the memory control circuit unit and the memory storage device of the invention can be used for only backing up a part of data when the preset is written by using the multi-page programming mode, and only verifying the data in a part of the entity programming units in the process of verifying the data written by using the multi-page programming mode, thereby reducing the time required by data writing and verification.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;
FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to another example embodiment of the present invention;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention;
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIGS. 5A and 5B are schematic diagrams of an example memory cell architecture and physically erased cells according to the example embodiment;
FIG. 6A is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention;
FIG. 6B is a diagram illustrating multi-frame coding in accordance with an exemplary embodiment of the present invention;
FIGS. 7 and 8 illustrate exemplary diagrams of managing physical erase units according to one exemplary embodiment;
FIG. 9 is a diagram illustrating writing data to a rewritable nonvolatile memory module using a single page programming mode according to an example;
FIG. 10 is a diagram illustrating writing data to a rewritable non-volatile memory module using a multi-page programming mode according to an example;
FIGS. 11 to 12 are diagrams illustrating an example of a data writing method according to an example of the present invention;
fig. 13 is a flowchart illustrating a data writing method according to an example of the present invention.
The reference numbers illustrate:
10: memory storage device
11: host system
110: system bus
111: processor with a memory having a plurality of memory cells
112: random access memory
113: read-only memory
114: data transmission interface
12: input/output (I/O) device
20: main machine board
201: portable disk
202: memory card
203: solid state disk
204: wireless memory storage device
205: global positioning system module
206: network interface card
207: wireless transmission device
208: keyboard with a keyboard body
209: screen
210: horn type loudspeaker
32: SD card
33: CF card
34: embedded memory device
341: embedded multimedia card
342: embedded multi-chip packaging storage device
402: connection interface unit
WL 0-WL 127: word line
404: memory control circuit unit
406: rewritable nonvolatile memory module
702: memory management circuit
704: host interface
706: memory interface
708: error checking and correcting circuit
710: buffer memory
712: power management circuit
801(1) -801 (r): position of
820: encoding data
810(0) -810 (E): physical programming unit
502: data area
504: idle zone
506: temporary storage area
508: substitution zone
510(0) to 510 (N): physical erase unit
LBA (0) to LBA (h): logic unit
LZ (0) to LZ (M): logical area
D0-D255: data of
S1301: step of receiving a plurality of data
S1303: writing the plurality of data into the first physically erased cell using a multi-page programming mode
S1305: writing first data of the plurality of data into a second physically erased cell using a single page programming mode, wherein the probability of a write failure occurring in a first physically erased cell for storing the first data is higher than the probability of a write failure occurring in other physically erased cells of the first physically erased cell
S1307: verifying data stored in first physical programming cells
S1309: marking the second entity programmed unit for storing the first data in the second entity erasing unit as invalid
S1311: writing the third physical erase unit in the multi-page programming mode according to the data in the other physical program units in the first physical erase unit and the data in the second physical program unit in the second physical erase unit
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.
In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.
In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through the data transmission interface 114 in a wired or wireless manner. The memory storage device 10 may be, for example, a personal disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be a memory storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, Bluetooth (Bluetooth) memory storage device, or Bluetooth low energy memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded Multi-media cards (eMMC) 341 and/or embedded Multi-Chip Package memory devices (eMCP) 342, and various types of embedded memory devices electrically connecting the memory module to the substrate of the host system.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.
In the exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the Secure Digital (SD) interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the Multi-Chip Package (Multi-Package) interface standard, the Multimedia Memory Card (Multi, Embedded) interface standard, the Multimedia Card (MMC) interface standard, eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi-Chip Package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.
The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware, and performing operations such as writing, reading, erasing and merging of data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.
The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 has entity erasing units 510(0) -510 (N). For example, the physical erase units 510(0) -510 (N) may belong to the same memory die or to different memory dies. Each of the plurality of physically erased cells has a plurality of physically programmed cells, for example, in the exemplary embodiment of the present invention, each of the plurality of physically erased cells includes 258 physically programmed cells, and the physically programmed cells belonging to the same physically erased cell can be independently written and simultaneously erased. However, it should be understood that the invention is not limited thereto, and each of the plurality of physically erased cells may be composed of 64 physically programmed cells, 256 physically programmed cells, or any other number of physically programmed cells.
In more detail, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. The physical programming unit is a minimum unit for programming. That is, the physical programming unit is the minimum unit for writing data. Each physical programming cell typically includes a data bit region and a redundancy bit region. The data bit region includes a plurality of physical access addresses for storing user data, and the redundancy bit region stores system data (e.g., control information and error correction codes). In the exemplary embodiment, each physical program unit includes 4 physical access addresses in the data bit region, and one physical access address has a size of 512 bit group (byte). However, in other exemplary embodiments, the data bit region may include a greater or lesser number of physical access addresses, and the size and number of the physical access addresses are not limited in the present invention.
In an exemplary embodiment of the invention, the rewritable nonvolatile memory module 406 is a multi-Level Cell (TLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 3 bits of data in one memory Cell). However, the invention is not limited thereto, and the rewritable nonvolatile memory module 406 may also be a Multi-Level Cell (MLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 2 bits of data in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.
FIGS. 5A and 5B are schematic diagrams of memory cell architectures and physically erased cells according to the present example embodiment.
Referring to fig. 5A, the memory state of each memory cell of the rewritable nonvolatile memory module 406 can be identified as "111", "110", "101", "100", "011", "010", "001", or "000" (as shown in fig. 5A), wherein the 1 st bit from the left side is LSB, the 2 nd bit from the left side is CSB, and the 3 rd bit from the left side is MSB. In addition, the plurality of memory cells arranged on the same word line may constitute 3 physical program cells, wherein the physical program cell constituted by the LSB of the memory cells is referred to as a lower physical program cell, the physical program cell constituted by the CSB of the memory cells is referred to as a middle physical program cell, and the physical program cell constituted by the MSB of the memory cells is referred to as an upper physical program cell.
Referring to fig. 5B, a physical erase unit is composed of a plurality of physical program unit groups, wherein each of the physical program unit groups includes a lower physical program unit, a middle physical program unit and an upper physical program unit composed of a plurality of memory cells arranged on the same word line. For example, in the solid erase cell, the 0 th solid program cell belonging to the lower solid program cell, the 1 st solid program cell belonging to the middle solid program cell, and the 2 nd solid program cell belonging to the upper solid program cell are regarded as one solid program cell group. Similarly, the 3 rd, 4 th, and 5 th physical programming cells are considered as a physical programming cell group, and the other physical programming cells are classified into a plurality of physical programming cell groups according to the same manner.
FIG. 6A is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the invention.
Referring to FIG. 6A, the memory control circuit unit 404 includes a memory management circuit 702, a host interface 704, a memory interface 706, and an error checking and correcting circuit 708.
The memory management circuit 702 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 702 has a plurality of control commands, and the control commands are executed to write, read, and erase data during operation of the memory storage device 10. When the operation of the memory management circuit 702 or any circuit element included in the memory control circuit unit 404 is described below, the operation of the memory control circuit unit 404 is equivalently described.
In the exemplary embodiment, the control instructions of the memory management circuit 702 are implemented in firmware. For example, the memory management circuit 702 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In another exemplary embodiment, the control instructions of the memory management circuit 702 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 702 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 702. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In another exemplary embodiment, the control instructions of the memory management circuit 702 may also be implemented in a hardware format. For example, the memory management circuit 702 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 702 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.
The host interface 704 is electrically connected to the memory management circuit 702 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 702 through the host interface 704. In the exemplary embodiment, host interface 704 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 704 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.
The memory interface 706 is electrically connected to the memory management circuit 702 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written into the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 706. Specifically, if the memory management circuit 702 wants to access the rewritable nonvolatile memory module 406, the memory interface 706 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection procedures, etc.). The sequences of instructions are generated by, for example, the memory management circuit 702 and transferred to the rewritable non-volatile memory module 406 via the memory interface 706. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.
The error checking and correcting circuit 708 is electrically connected to the memory management circuit 702 and is used for performing an error checking and correcting process to ensure the correctness of data. Specifically, when the memory management circuit 702 receives a write command from the host system 11, the error checking and correcting circuit 708 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 702 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 702 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 708 performs an error checking and correcting process on the read data according to the error correction code and/or the error check code.
In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 710 and a power management circuit 712.
The buffer memory 710 is electrically connected to the memory management circuit 702 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 712 is electrically connected to the memory management circuit 702 and is used for controlling the power of the memory storage device 10.
In the exemplary embodiment, the error checking and correcting circuit 708 can perform single-frame (single-frame) coding on data stored in the same physical program unit, or perform multi-frame (multi-frame) coding on data stored in a plurality of physical program units. The single frame coding and the multi-frame coding may respectively use at least one of coding algorithms such as low density parity check code (LDPC), BCH code, convolutional code (convolutional code), turbo code, and the like. Alternatively, in an exemplary embodiment, the multi-frame coding may also use Reed-Solomon codes (RS codes) algorithms or exclusive OR (XOR) algorithms. In addition, in another exemplary embodiment, more coding algorithms not listed may also be employed, which is not described herein. Depending on the encoding algorithm employed, the ECC and correction circuit 708 encodes the data to be protected to generate corresponding ECC and/or ECC codes. For convenience of explanation, the error correction code and/or the error check code generated through encoding will be collectively referred to as encoded data hereinafter.
Fig. 6B is a diagram illustrating multi-frame coding according to an exemplary embodiment of the invention.
Referring to fig. 6B, taking the data stored in the encoded entity programming units 810(0) to 810(E) as an example to generate the corresponding encoded data 820, at least a portion of the data stored in each of the entity programming units 810(0) to 810(E) can be regarded as a frame. In multi-frame coding, data in the physical programming units 810(0) to 810(E) are coded according to the position of each bit (or bit group). For example, bit b at position 801(1)11、b21、…、bp1Will be encoded as bit b in the encoded data 820o1Bit b at position 801(2)12、b22、…、bp2Will be encoded as bit b in the encoded data 820o2(ii) a By analogy, bit b at position 801(r)1r、b2r、…、bprWill be encoded as bit b in the encoded data 820or. Thereafter, the data read from the physical programming units 810(0) -810 (E) can be decoded according to the encoded data 820 to attempt to correct errors that may exist in the read data.
In addition, in another exemplary embodiment of fig. 6B, the data for generating the encoded data 820 may also include redundant bits (redundancy bits) corresponding to data bits (data bits) in the data stored in the entity programming units 810(0) -810 (E). Take the data stored in the entity programming unit 810(0) as an example, wherein the redundant bits are generated by performing single frame encoding on the data bits stored in the entity programming unit 810(0), for example. In the present exemplary embodiment, it is assumed that when reading the data in the physical programming unit 810(0), the data read from the physical programming unit 810(0) can be decoded by using the redundancy bits (e.g., the single frame coded data) in the physical programming unit 810(0) for error detection and correction. However, when the decoding using the redundancy bits in the physical programming unit 810(0) fails (e.g., the number of bits error of the data stored in the decoded physical programming unit 810(0) is greater than a threshold), a Retry-Read mechanism may be used to attempt to Read the correct data from the physical programming unit 810 (0). Details about the re-reading mechanism will be described later. When the correct data cannot be Read from the physical programming units 810(0) by the Retry-Read mechanism, the encoded data 820 and the data of the physical programming units 810(1) to 810(E) can be Read, and the decoding is performed according to the encoded data 820 and the data of the physical programming units 810(1) to 810(E) to try to correct the errors in the data stored in the physical programming units 810 (0). That is, in the exemplary embodiment, when decoding using the encoded data generated by the single-frame encoding fails and reading using the re-Read (Retry-Read) mechanism fails, the encoded data generated by the multi-frame encoding is decoded instead.
FIGS. 7 and 8 illustrate exemplary diagrams of managing physically erased cells, according to an exemplary embodiment.
Referring to FIG. 7, the rewritable nonvolatile memory module 406 has physical erase units 510(0) -510 (N), and the memory management circuit 702 is logically divided (partitioned) into a data area 502, an idle area 504, a temporary area 506 and a replacement area 508.
The physically erased cells logically belonging to the data area 502 and the idle area 504 are used for storing data from the host system 11. Specifically, the physical erase units in the data area 502 are regarded as physical erase units with stored data, and the physical erase units in the idle area 504 are used to replace the physical erase units in the data area 502. That is, when receiving a write command and data to be written from the host system 11, the memory management circuit 702 extracts the physical erase unit from the idle region 504 and writes the data into the extracted physical erase unit to replace the physical erase unit of the data region 502.
The physical erase unit logically belonging to the register 506 is used for recording system data. For example, the system data includes a logical to physical address mapping table, a manufacturer and a model of the rewritable nonvolatile memory module, a number of physical erase units of the rewritable nonvolatile memory module, a number of physical program units of each physical erase unit, and the like.
The physically erased cells logically belonging to the replacement area 508 are used in the bad-physically-erased-cell replacement procedure to replace the damaged physically erased cells. Specifically, if there are still normal physically erased cells in the replacement area 508 and the physically erased cells in the data area 502 are damaged, the memory management circuit 302 extracts the normal physically erased cells from the replacement area 508 to replace the damaged physically erased cells.
In particular, the number of physically erased cells in the data area 502, the idle area 504, the temporary area 506 and the replacement area 508 may vary according to different memory specifications. Moreover, it should be appreciated that during operation of the memory storage device 10, the grouping relationship of the physically erased cells associated with the data area 502, the idle area 504, the temporary area 506 and the replacement area 508 will dynamically change. For example, when the physically erased cells in the idle area 504 are damaged and replaced by the physically erased cells in the replacement area 508, the physically erased cells in the replacement area 508 are associated with the idle area 504.
Referring to fig. 8, the memory management circuit 702 allocates logical units LBA (0) -LBA (h) to map the physical erase units of the data area 502, wherein each logical unit has a plurality of logical sub-units to map the physical program unit of the corresponding physical erase unit. Moreover, when the host system 11 wants to write data to the logical units or update the data stored in the logical units, the memory management circuit 702 extracts a physical erase unit from the idle area 504 to write data, so as to replace the physical erase unit in the data area 502. In the present exemplary embodiment, the logical subunit may be a logical page or a logical sector.
In order to identify the physical erase unit in which the data of each logical unit is stored, in the present exemplary embodiment, the memory management circuit 702 records the mapping between the logical units and the physical erase units. Moreover, when the host system 11 intends to access data in the logical sub-unit, the memory management circuit 702 identifies the logical unit to which the logical sub-unit belongs, and accesses data in the physical erase unit mapped by the logical unit. For example, in the exemplary embodiment, the memory management circuit 702 stores a logical-to-physical address mapping table in the rewritable non-volatile memory module 406 to record the physical erase unit mapped by each logical unit, and the memory management circuit 702 loads the logical-to-physical address mapping table into the buffer memory 710 for maintenance when data is to be accessed.
It should be noted that, since the capacity of the buffer memory 710 is limited and cannot store the mapping table for recording the mapping relationships of all the logic units, in the exemplary embodiment, the memory management circuit 702 groups the logic units LBA (0) to LBA (h) into a plurality of logic zones LZ (0) to LZ (m), and configures a logical-to-physical address mapping table for each logic zone. In particular, when the memory management circuit 702 wants to update the mapping of a logical unit, the logical-to-physical address mapping table corresponding to the logical area to which the logical unit belongs is loaded into the buffer memory 710 for updating.
It should be noted that the memory management circuit 702 can write to the rewritable nonvolatile memory module 406 in a single-page programming mode or a multi-page programming mode.
FIG. 9 is a diagram illustrating writing data to a rewritable nonvolatile memory module using a single page programming mode according to an example.
Referring to fig. 9, when the memory storage device 10 receives a write command (also referred to as a first write command) from the host system 11 indicating to store update data to the 0 th to 257 th logical sub-units of the logical unit LBA (0), it is assumed that in the present exemplary embodiment, the memory management circuit 702 extracts 3 physical erase units 510(F +1), 510(F +2), and 510(F +3) from the idle area 504 as a plurality of active physical erase units corresponding to the first write command. Assuming that the memory management circuit 702 is programmed in the single page programming mode, the memory management circuit 702 writes the data of the first write command from the buffer memory 710 to the physical program cells of the physical erase cells 510(F +1), 510(F +2), and 510(F +3) according to the first command sequence. Here, since the physical program cells of the physical erase cells 510(F +1), 510(F +2), and 510(F +3) are programmed in the single page program mode, the memory cells of the physical program cells constituting the physical erase cells 510(F +1), 510(F +2), and 510(F +3) are programmed to store 1 bit of data, as described above. That is, in the single page programming mode, the lower physical program cells of the physically erased cells 510(F +1), 510(F +2), and 510(F +3) are used to write data, and the middle and upper physical program cells of the physically erased cells 510(F +1), 510(F +2), and 510(F +3) are not used to write data.
In detail, as shown in FIG. 9, the memory management circuit 702 sequentially writes the data of 0 th to 257 th logical sub-units to be stored in the logical unit LBA (0) to the next physical program unit of the physical erase units 510(F +1), 510(F +2), and 510(F + 3). That is, the memory management circuit 702 uses the single-page programming mode to write the data corresponding to the first write command from the buffer memory 710 into the lower entity programming cells of the entity erased cells 510(F +1), 510(F +2), and 510(F +3) in the rewritable nonvolatile memory module 406, and the middle entity programming cells and the upper entity programming cells of the entity erased cells 510(F +1), 510(F +2), and 510(F +3) are not used to write the data.
After writing the data corresponding to the first write command from the buffer memory 710 to the next physical program unit of the physical erase units 510(F +1), 510(F +2), and 510(F +3) in the rewritable non-volatile memory module 406 using the single-page programming mode, the memory management circuit 702 associates the physical erase units 510(F +1), 510(F +2), and 510(F +3) with the data area 502, and returns the write completion information to the host system 11 in response to the first write command issued by the host system 11.
FIG. 10 is a diagram illustrating writing data to a rewritable nonvolatile memory module using a multi-page programming mode according to an example.
Assuming that the first write command indicates to store data to the 0 th to 257 th logical sub-units of the logical unit LBA (0), the memory management circuit 702 will first temporarily store the data of the first write command in the buffer memory 710. Then, referring to fig. 10, the memory management circuit 702 can extract 1 physical erase unit 510(F +4) from the idle area 504 as an active physical erase unit corresponding to the first write command. Assuming that the memory management circuit 702 is programmed in the multi-page programming mode, the memory management circuit 702 writes data of a first write command from the buffer memory 710 to the physical program cells of the physical erase cell 510(F +4) according to a first command sequence. Here, since the physically erased cell 510(F +4) is programmed in the multi-page program mode, the memory cell of the physically programmed cell constituting the physically erased cell 510(F +4) is programmed to store a plurality of bits of data, as described above. That is, in the multi-page program mode, the lower, middle, and upper physical program cells of the physical erase cell 510(F +4) are used to write data.
In detail, as shown in FIG. 10, the memory management circuit 702 sequentially writes the data of 0 th to 257 th logical sub-cells to be stored in the logical unit LBA (0) into the lower physical program unit, the middle physical program unit and the upper physical program unit of the physical erase unit 510(F + 4). That is, the memory management circuit 702 writes the data corresponding to the first write command from the buffer memory 710 to the lower, middle and upper physical program cells of the physical erase cell 510(F +2) in the rewritable non-volatile memory module 406 using the multi-page program mode.
After the data corresponding to the first write command is written from the buffer memory 710 to the lower, middle and upper physical program units of the physical erase unit 510(F +4) in the rewritable non-volatile memory module 406 using the multi-page programming mode, the memory management circuit 702 associates the physical erase unit 510(F +4) with the data area 502 and returns the write completion information to the host system 11 in response to the first write command issued by the host system 11.
It should be noted that, in one embodiment, it is assumed that the memory management circuit 702 is configured to write data of a write command to the rewritable nonvolatile memory module 406 using the multi-page programming mode. However, the reliability of data written using the multi-page program mode is lower compared to the single-page program mode. In other words, data written using the multi-page programming mode may have write failures, which may result in the written data having uncorrectable error bits. Therefore, in the conventional method, when the memory management circuit 702 is programmed to write the data of the write command to the rewritable non-volatile memory module 406 using the multi-page programming mode, the memory management circuit 702 also writes all the data corresponding to the write command to at least one physically erased cell of the rewritable non-volatile memory module 406 using the single-page programming mode. Thereafter, the memory management circuit 702 verifies all data of the write command written in the multi-page programming mode to determine whether a write failure occurs while writing to one (or some) of the physical program cells. Assuming that a physical programming unit is written with data using the multi-page programming mode, when the data stored in the physical programming unit has uncorrectable error bits (i.e., a write failure occurs), the memory management circuit 702 performs data recovery using the data previously written using the single-page programming mode. That is, in the aforementioned example, the single page programming mode is used for restoring and backing up data.
It is noted that the process of backing up data using the single page programming mode takes time and space in the rewritable nonvolatile memory module 406. In addition, the operation of verifying all the data of the write command written in the multi-page programming mode by the memory management circuit 702 to determine whether a write failure occurs when writing to a certain (or some) physical program unit(s) takes a lot of time.
Therefore, the present invention provides a data writing method, when the memory management circuit 702 is preset to be written using the multi-page programming mode, the memory management circuit 702 only needs to backup a part of the data, and only needs to verify the data in a part of the physical programming units during the process of verifying the data written using the multi-page programming mode, thereby reducing the time required for data writing and verification.
More specifically, fig. 11 to 12 are schematic diagrams illustrating an example of a data writing method according to an example of the present invention.
Assume that the memory management circuit 702 receives at least one write command issued by the host system 11, the write command is used to instruct writing a plurality of data (e.g., data D0-D257) into the rewritable nonvolatile memory module 406. The memory management circuit 702 receives the data D0-D257 corresponding to the write command. The memory management circuit 702 first buffers the data D0-D257 into the buffer memory 710. Then, referring to fig. 11, the memory management circuit 702 can extract 1 physical erase unit 510(F +5) from the idle area 504 as an active physical erase unit corresponding to the write command. Assuming that the memory management circuit 702 is programmed in the multi-page programming mode, the memory management circuit 702 writes the data D0-D257 from the buffer memory 710 into the 0 th to 257 th physical program cells of the physical erase cells 510(F + 5). In detail, as shown in FIG. 11, the memory management circuit 702 sequentially writes the data D0-D255 into the lower solid program cell, the middle solid program cell and the upper solid program cell of the solid erase cell 510(F + 5).
In particular, in the embodiment of the invention, the memory management circuit 702 may, for example, store a look-up table in advance to know which physical program unit composed of the memory cells on the word line 406 in the rewritable nonvolatile memory module has a higher probability of having a write failure (e.g., the probability of having a write failure is higher than that of other physical program units). More specifically, because the manufacturing process may cause a higher probability of a write failure in the physical programming unit composed of the memory cells on some word lines, the manufacturer of the rewritable nonvolatile memory module 406 may experimentally know the locations of the word lines (or the physical programming units) that are prone to the write failure before the rewritable nonvolatile memory module 406 leaves the factory, and then generate the lookup table.
Here, the physical program cell in which the probability of the occurrence of the write failure is higher than the threshold value is referred to as a "first physical program cell". Assume that the rewritable non-volatile memory module 406 includes n word lines in total, the n word lines are arranged in a sequence, and a plurality of memory cells on the same word line of the n word lines form at least one of the plurality of physically programmed cells. Assume that a plurality of memory cells (also referred to as first memory cells) in the rewritable non-volatile memory module 406 form the first physically programmable unit, and the first memory cell bit is located on at least one word line (also referred to as a first word line) of the n word lines, where n is a positive integer greater than zero. In particular, in one embodiment, the first word line is located in 0 th to i th word lines, j th to k th word lines, or h th to n-1 th word lines of the n word lines. Wherein i, j, k and h are respectively positive integers which are larger than zero and are discontinuous with each other. i is less than j, j is less than k, k is less than h and h is less than n.
For example, assuming that the rewritable nonvolatile memory module 406 includes 96 word lines in total, the first word line is located in the 0 th to 6 th word lines, the 46 th to 49 th word lines or the 89 th to 95 th word lines of the 96 word lines. That is, in this embodiment, i has a value of 6, j has a value of 46, k has a value of 49, h has a value of 89, and n has a value of 96. In other words, in the present embodiment, the probability of the write failures occurring at the first word lines, the middle word lines and the end word lines of the n word lines is higher than the threshold value.
Following the example of FIG. 11, after the data D0-D257 are sequentially written into the lower, middle and upper physical program cells of the physical erase cell 510(F +5), it is assumed that the memory management circuit 702 can know that the 3 rd to 5 th and 252 th to 254 th physical program cells of the physical erase cell 510(F +5) belong to the first physical program cell (i.e., the probability of the write failure is higher than that of the other physical program cells) according to the lookup table. The memory management circuit 702 extracts 1 physical erase cell 510(F +6) from the idle region 504, and writes the data D3-D5 and D252-D254 (also referred to as the first data) from the buffer memory 710 into the 0 th, 3 th, 6 th, 9 th, 12 th, and 15 th physical program cells (also referred to as the second physical program cells) of the physical erase cell 510(F +6) using the single page program mode. It is noted that the present invention is not limited to the number of the first data. In one embodiment, the amount of the first data may be thirty percent of the plurality of data corresponding to the write command received from the host system 11.
Next, the memory management circuit 702 verifies the data stored in the 3 rd to 5 th and 252 th to 254 th physical programming cells of the physical erase cell 510(F +5) to determine whether there are uncorrectable error bits in the data.
Assuming that there are no uncorrectable error bits in the data stored in the 3 rd to 5 th and 252 th to 254 th physical programming cells of the physical erase cell 510(F +5), the memory management circuit 702 marks the data stored in the 0 th, 3 rd, 6 th, 9 th, 12 th and 15 th physical programming cells of the physical erase cell 510(F +6) as invalid.
Assuming that data stored in 3 rd to 5 th and 252 th to 254 th physical programming cells of the physical erase cell 510(F +5) has uncorrectable error bits, referring to FIG. 11 and FIG. 12, in one embodiment, the memory management circuit 702 copies data D3D 5 from 0 th, 3 th and 6 th physical programming cells of the physical erase cell 510(F +6) and copies data D0D 2 and data D6D 257 from 0 th to 2 th and 6 to 257 th physical programming cells of the physical erase cell 510(F +5), in case that data D3D 5 (also called as second data) in the 3 rd to 5 th physical programming cells of the physical erase cell 510(F +5) has uncorrectable error bits. Thereafter, the memory management circuit 702 sequentially writes the data D0-D2 copied from the 0 th to 2 nd physical program cells of the physical erase cell 510(F +5), the data D3-D5 copied from the 0 th, 3 th and 6 th physical program cells of the physical erase cell 510(F +6), and the data D6-D257 copied from the 6 th to 257 th physical program cells of the physical erase cell 510(F +5) into the 0 th to 257 th physical program cells of the physical erase cell 510(F +7) (also referred to as a third physical erase cell) using the multi-page programming mode.
In addition, assuming that error bits that cannot be corrected exist in the data stored in the 3 rd to 5 th and 252 th to 254 th physical programming units of the physical erase unit 510(F +5), the memory management circuit 702 can also copy the data D3 to D5 and the data D252 to D254 from the 0 th, 3, 6, 9, 12 and 15 th physical programming units of the physical erase unit 510(F +6) and copy the data D0 to D2, the data D6 to D251 and the data D55 to D257 from the 0 th to 2, 6 to 251 and 255 to 257 th physical programming units of the physical erase unit 510(F +5), referring to FIG. 11 and FIG. 12 at the same time. Thereafter, the memory management circuit 702 sequentially writes the data D0-D2 copied from the 0 th to 2 nd physical program cells of the physical erase cell 510(F +5), the data D3-D5 copied from the 0 th, 3 th and 6 th physical program cells of the physical erase cell 510(F +6), the data D6-D251 copied from the 6 th to 251 th physical program cells of the physical erase cell 510(F +5), the data D252-D254 copied from the 9 th, 12 th and 15 th physical program cells of the physical erase cell 510(F +6) and the data D255-D257 copied from the 255 th to 257 th physical program cells of the physical erase cell 510(F +5) into the 0 th to 257 th physical program cells of the erase cell 510(F +7) using the multi-page program mode.
It should be noted that, the foregoing example is described with respect to a plural Level Cell (TLC) NAND-type flash memory module (i.e., a flash memory module that can store 3 bits of data in one memory Cell). However, the present invention is not limited thereto, and in other embodiments, the data writing method of the present invention may also be applied to a Multi-Level Cell (MLC) NAND type flash memory module, a Quad-Level Cell (QLC) NAND type flash memory module, or other memory modules with the same characteristics.
Fig. 13 is a flowchart illustrating a data writing method according to an example of the present invention.
Referring to fig. 13, in step S1301, the memory management circuit 702 receives a plurality of data. In step S1303, the memory management circuit 702 writes the data into the first physically erased cells using the multi-page programming mode. In step S1305, the memory management circuit 702 writes the first data of the plurality of data into the second physically erased cell using the single page programming mode. The probability of the write failure of the first entity programming unit for storing the first data in the first entity erasing unit is higher than the probability of the write failure of other entity programming units in the first entity erasing unit. Thereafter, in step S1307, the memory management circuit 702 verifies the data stored in the first entity program unit. When the verification is successful, in step S1309, the memory management circuit 702 marks the second physically erased unit of the second physically erased units for storing the first data as invalid. When the verification fails, in step S1311, the memory management circuit 702 writes the third physically erased cell in the multi-page programming mode according to the data in the other physically erased cells and the data in the second physically programmed cell in the first physically erased cell.
In summary, the data writing method, the memory control circuit unit and the memory storage device of the present invention can be used to only backup a portion of data when the default is to write using the multi-page programming mode, and only verify the data in a portion of the physical programming units during the verification of the data written using the multi-page programming mode, thereby reducing the time required for data writing and verification.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (21)

1. A data writing method is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the plurality of entity erasing units is provided with a plurality of entity programming units, and the data writing method comprises the following steps:
receiving a plurality of data;
writing the plurality of data to a first physically-erased cell of the plurality of physically-erased cells using a multi-page programming mode;
writing at least one first datum of the plurality of data to a second physically erased cell of the plurality of physically erased cells using a single page programming mode;
verifying the plurality of data stored in the first physically erased cell; and
when the verification fails, a write operation is performed on a third physically-erased cell of the plurality of physically-erased cells using the multi-page programming mode according to the first data and the plurality of data.
2. The data writing method according to claim 1, wherein
The probability of the write failure of at least one first entity programming unit for storing the first data in the first entity erasing unit is higher than the probability of the write failure of other entity programming units in the first entity erasing unit.
3. The data writing method of claim 2, the method comprising:
verifying data stored in the first physical programming cell;
when the data in the first entity programming unit has no bits which can not be corrected, marking at least one second entity programming unit for storing the first data in the second entity erasing unit as invalid;
and when the second data in the first entity programming unit has bits which cannot be corrected, writing the data in the other entity programming units in the first entity erasing unit and the data in the second entity programming unit in the second entity erasing unit into the third entity erasing unit by using the multi-page programming mode.
4. The data writing method according to claim 1, wherein the amount of the first data is thirty percent of the amount of the plurality of data.
5. The data writing method according to claim 2, wherein the rewritable non-volatile memory module comprises n word lines, the n word lines are arranged in sequence, and a plurality of memory cells on a same word line among the n word lines form at least one of the plurality of physical programming units, wherein
A plurality of first memory cells of the plurality of memory cells form the first physical programming unit, the plurality of first memory cells are located on at least one first word line of the n word lines, wherein n is a positive integer greater than zero.
6. The data writing method according to claim 5, wherein
The first word line is positioned in the 0 th to i th word lines, the j th to k th word lines or the h th to n-1 th word lines of the n word lines,
wherein i, j, k, h are respectively positive integers which are larger than zero and are discontinuous with each other,
wherein i is less than j, j is less than k, k is less than h and h is less than n.
7. The data writing method of claim 1, wherein the step of receiving the plurality of data comprises:
receiving at least one writing instruction issued by the host system, wherein the writing instruction is used for indicating that the plurality of data are written into the rewritable nonvolatile memory module; and
and temporarily storing the data into a buffer memory.
8. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:
the host interface is used for electrically connecting to a host system;
a memory interface electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of entity erasing units, and each entity erasing unit in the plurality of entity erasing units has a plurality of entity programming units;
a memory management circuit electrically connected to the host interface and the memory interface,
wherein the memory management circuitry is to receive a plurality of data,
wherein the memory management circuit is further configured to write the plurality of data to a first physically erased cell of the plurality of physically erased cells using a multi-page programming mode,
wherein the memory management circuitry is further configured to write at least a first datum of the plurality of data to a second physically erased cell of the plurality of physically erased cells using a single page programming mode,
wherein the memory management circuitry is further to verify the plurality of data stored in the first physically erased cell,
when the verification fails, the memory management circuit is further configured to perform a write operation on a third physically erased cell of the plurality of physically erased cells using the multi-page programming mode according to the first data and the plurality of data.
9. The memory control circuit unit of claim 8, wherein the probability of a write failure occurring in at least one first physically erased cell of the first physically erased cells for storing the first data is higher than the probability of a write failure occurring in other physically erased cells of the first physically erased cells.
10. The memory control circuit cell of claim 9, wherein
The memory management circuit is further configured to verify data stored in the first physical program cell,
when there are no uncorrectable bits in the data in the first physical programming unit, the memory management circuit is further configured to mark at least one second physical programming unit in the second physical erase unit for storing the first data as invalid,
when there is an uncorrectable bit in the second data in the first physical program cell, the memory management circuit is further configured to write the third physical erase cell in the multi-page programming mode according to the data in the other physical program cells in the first physical erase cell and the data in the second physical program cell in the second physical erase cell.
11. The memory control circuit unit of claim 8, wherein the amount of the first data is thirty percent of the amount of the plurality of data.
12. The memory control circuit unit of claim 9, wherein the rewritable non-volatile memory module comprises n word lines arranged in a sequence, a plurality of memory cells on a same one of the n word lines forming at least one of the plurality of physically programmed cells, wherein
A plurality of first memory cells of the plurality of memory cells form the first physical programming unit, the plurality of first memory cells are located on at least one first word line of the n word lines, wherein n is a positive integer greater than zero.
13. The memory control circuit cell of claim 12, wherein
The first word line is positioned in the 0 th to i th word lines, the j th to k th word lines or the h th to n-1 th word lines of the n word lines,
wherein i, j, k, h are respectively positive integers which are larger than zero and are discontinuous with each other,
wherein i is less than j, j is less than k, k is less than h and h is less than n.
14. The memory control circuit unit according to claim 8, wherein in the operation of receiving the plurality of data,
the memory management circuit is further configured to receive at least one write command issued by the host system, where the write command is used to instruct writing of the plurality of data into the rewritable nonvolatile memory module,
the memory management circuit is further configured to temporarily store the plurality of data into a buffer memory.
15. A memory storage device, comprising:
the connection interface unit is used for electrically connecting to a host system;
the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units; and
a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is configured to receive a plurality of data,
wherein the memory control circuit unit is further configured to write the plurality of data to a first physically-erased cell of the plurality of physically-erased cells using a multi-page programming mode,
wherein the memory control circuitry is further configured to write at least a first data of the plurality of data to a second physically erased cell of the plurality of physically erased cells using a single page programming mode,
wherein the memory control circuitry unit is further configured to verify the plurality of data stored in the first physically erased cell,
when the verification fails, the memory control circuit unit is further configured to perform a write operation on a third one of the plurality of physically-erased cells using the multi-page programming mode according to the first data and the plurality of data.
16. The memory storage device of claim 15, wherein the probability of a write failure occurring in at least one first physically erased cell of the first physically erased cells for storing the first data is higher than the probability of a write failure occurring in other physically erased cells of the first physically erased cells.
17. The memory storage device of claim 16, wherein
The memory control circuit unit is further configured to verify data stored in the first physical program unit,
the memory control circuit unit is further configured to mark at least one second physical programming unit of the second physical erase units for storing the first data as invalid when there is no uncorrectable bit in the data of the first physical programming unit,
when there is an uncorrectable bit in the second data in the first physical program cell, the memory control circuit unit is further configured to write the third physical erase cell in the multi-page programming mode according to the data in the other physical program cells in the first physical erase cell and the data in the second physical program cell in the second physical erase cell.
18. The memory storage device of claim 15, wherein the amount of the first data is thirty percent of the amount of the plurality of data.
19. The memory storage device of claim 16, wherein the rewritable non-volatile memory module comprises n word lines, the n word lines being arranged in a sequence, a plurality of memory cells on a same one of the n word lines forming at least one of the plurality of physical programming cells, wherein
A plurality of first memory cells of the plurality of memory cells form the first physical programming unit, the plurality of first memory cells are located on at least one first word line of the n word lines, wherein n is a positive integer greater than zero.
20. The memory storage device of claim 19, wherein
The first word line is positioned in the 0 th to i th word lines, the j th to k th word lines or the h th to n-1 th word lines of the n word lines,
wherein i, j, k, h are respectively positive integers which are larger than zero and are discontinuous with each other,
wherein i is less than j, j is less than k, k is less than h and h is less than n.
21. The memory storage device of claim 15, wherein in operation receiving the plurality of data,
the memory control circuit unit is further configured to receive at least one write command issued by the host system, where the write command is used to instruct writing of the plurality of data into the rewritable nonvolatile memory module,
the memory control circuit unit is further used for temporarily storing the data into a buffer memory.
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