CN107402716A

CN107402716A - Method for writing data, memory control circuit unit and internal storing memory

Info

Publication number: CN107402716A
Application number: CN201610356300.2A
Authority: CN
Inventors: 柯伯政
Original assignee: Hefei Core Electronics Co Ltd
Current assignee: Hefei Core Electronics Co Ltd
Priority date: 2016-05-20
Filing date: 2016-05-20
Publication date: 2017-11-28
Anticipated expiration: 2036-05-20
Also published as: CN107402716B

Abstract

The present invention proposes a kind of method for writing data, memory control circuit unit and internal storing memory.This method includes：The first write instruction is received, and the data of corresponding first write instruction are write into buffer storage；And when write caching function is closed and the data of the first write instruction are kept in buffer storage, the data of corresponding first write instruction are write from buffer storage into the first instance programmed cell of first instance erased cell using single page sequencing pattern, wherein first instance programmed cell is made up of multiple first memory cells and in single page sequencing pattern, and each first memory cell among the first memory cell of composition first instance programmed cell only stores 1 bit data.The present invention can be effectively prevented from because host computer system powers off caused Missing data singularly, and can effectively utilize the space of duplicative Nonvolatile memory.

Description

Method for writing data, memory control circuit unit and internal storing memory

Technical field

The present invention relates to a kind of method for writing data, memory control circuit unit and internal storing memory.

Background technology

Digital camera, mobile phone and MP3 are very rapid in growth over the years so that demand of the consumer to store media Also rapidly increase.Because duplicative Nonvolatile memory (rewritable non-volatile memory) has data non- Volatibility, power saving, small volume, without the characteristic such as mechanical structure, read or write speed be fast, be most suitable for portable electronic product, such as take down notes This computer.Solid state hard disc is exactly a kind of internal storing memory using flash memory as store media.Therefore, flash memory industry turns into recent years A ring quite popular in electronic industry.

According to the storable digit of each memory cell in duplicative Nonvolatile memory, anti-and (NAND) type flash memory can Divide into single-order storage element (Single Level Cell, SLC) NAND-type flash memory, multistage storage element (Multi Level Cell, MLC) NAND-type flash memory and three rank storage elements (Trinary Level Cell, TLC) NAND-type flash memory, wherein SLC Each memory cell of NAND-type flash memory can store the data (that is, " 1 " and " 0 ") of 1 position, each memory of MLC NAND-type flash memories Each memory cell that born of the same parents can store the data of 2 positions and TLC NAND-type flash memories can store the data of 3 positions.

In NAND-type flash memory, entity program unit is the several memory cell institutes group online by being arranged in same character Into.Because each memory cell of SLC NAND-type flash memories can store the data of 1 position, therefore, in SLC NAND-type flash memories, row It is a corresponding entity program unit to be listed in the online several memory cells of same character.

For SLC NAND-type flash memories, the floating gate storage layer of each memory cell of MLC NAND-type flash memories can store up The data of 2 positions are deposited, each of which storing state (that is, " 11 ", " 10 ", " 01 " and " 00 ") includes least significant bit (Least Significant Bit, LSB) and highest significant position (Most Significant Bit, MSB).For example, in storing state The value for the 1st position counted from left side is LSB, and the value for the 2nd position counted from left side is MSB.Therefore, it is arranged in same The online several memory cells of character can form 2 entity program units, wherein the entity that thus LSB of a little memory cells is formed Programmed cell is referred to as lower entity program unit (low physical programming unit), and thus a little memories The entity program unit that the MSB of born of the same parents is formed is referred to as upper entity program unit (upper physical programming unit).It is noted that made a mistake when entity program unit in sequencing or system exception power-off, lower entity journey Therefore data stored by sequence unit may also be lost.In addition, entity program unit is programmed and this lower entity instantly When upper entity program unit corresponding to programmed cell is not yet programmed, stored number in lower entity program unit Unsure state be presented because of the characteristic of MLC NAND-type flash memories according to meeting.In this case, institute in lower entity program unit The data of storage also have the risk lost or damaged.

In general, refer to when the Memory Controller Hub of duplicative Nonvolatile memory receives the write-in from host computer system When making, it will usually first keep in into buffer storage the data corresponding to this write instruction and immediately reply corresponding this and write The write-in for entering instruction completes information to host computer system to respond the write operation that host computer system is assigned.Afterwards, Memory Controller Hub It can be in due course, such as when the free space in host computer system idle a period of time or buffer storage is inadequate, just can will Data in buffer storage are write into duplicative Nonvolatile memory.

However, in general buffer storage is volatile memory.That is, when a pen data is stored in buffer-stored When being still not written to duplicative Nonvolatile memory in device, if now host computer system powers off singularly, then it is stored in Therefore data in buffer storage can be lost.

Therefore, in general can be by the mode that (disable write cache) instruction is closed using write caching Come avoid host computer system because power off singularly and caused by be stored in the losses of data in buffer storage.Specifically, when interior After memory controller receives the write caching out code from host computer system, when Memory Controller Hub is received from host computer system Write instruction when, corresponding to the data of this write instruction can be written into buffer storage, and Memory Controller Hub can be immediately The data of write instruction are write into duplicative Nonvolatile memory from buffer storage, to reduce the number of write instruction According to the time rested in buffer storage, and reduce the risk of Missing data.

It is to be noted that the data of write instruction possibly can not just fill up entity program unit simultaneously Lower entity program unit and upper entity program unit.Therefore, if when the data of write instruction are only write to lower entity journey When sequence unit and the upper entity program unit corresponding to lower entity program unit do not store data, then entity program is descended Stored data may be presented unsure state because of the characteristic of MLC NAND-type flash memories and have the wind of loss in unit Danger.

In commonly known method, in order to avoid the above situation causes the data stored by lower entity program unit Lose, Memory Controller Hub can write redundant data (dummy data) in supreme entity program unit so that lower entity Stable state is presented in programmed cell, to ensure that the data in lower entity program unit have stored completely and stably.So And after Memory Controller Hub receives the write caching out code from host computer system, it may refer to because of the write-in of more Order, and excessive redundant data is write into duplicative Nonvolatile memory, in turn result in those skilled in the art and be generally called " write-in amplification (write amplification) " the problem of, this problem causes the storage of duplicative Nonvolatile memory Deposit the low of efficiency.

Based on above-mentioned, how to avoid because host computer system powers off the loss of the data caused in buffer storage singularly, And ensure that the data of the write instruction before powering off singularly have all stably been stored into duplicative Nonvolatile memory And the space of duplicative Nonvolatile memory is effectively utilized, is the target that this art personnel are endeavoured.

The content of the invention

The present invention provides a kind of method for writing data, memory control circuit unit and internal storing memory, can be effectively Avoid because host computer system powers off caused Missing data singularly, and it is non-volatile to effectively utilize duplicative The space of internal memory.

The present invention proposes a kind of method for writing data, for duplicative Nonvolatile memory module, wherein duplicative Nonvolatile memory module has multiple entity erased cells, each entity erased cell among this little entity erased cell With multiple entity program units, this method for writing data includes：The first write instruction is received from host computer system, and will be right The data of this first write instruction are answered to keep in into buffer storage；And when write caching function be closed and first write-in When the data of instruction are kept in buffer storage, the data of corresponding first write instruction are postponed using single page sequencing pattern Rush in memory and write into the first instance programmed cell of the first instance erased cell among entity erased cell, wherein First instance programmed cell is made up of multiple first memory cells and in single page sequencing pattern, forms first instance journey Each first memory cell among first memory cell of sequence unit only stores 1 bit data.

In one embodiment of this invention, in addition to：Write caching out code is received from host computer system, and closes and writes Enter cache function to respond write caching out code.

In one embodiment of this invention, wherein before the step of host computer system reception write caching out code, also Including：The second write instruction is received from host computer system and keeps in the data of corresponding second write instruction to buffer storage In；And the data for being temporarily stored into corresponding second write instruction in buffer storage are write to entity using multipage sequencing pattern The second instance programmed cell of second instance erased cell among erased cell, wherein second instance programmed cell be by Multiple second memory cells form and in the multipage sequencing patterns, form the second memory cell of second instance programmed cell Among each second memory cell store more bit datas.

In one embodiment of this invention, wherein using single page sequencing pattern by the data of corresponding first write instruction from Write-in is into the first instance programmed cell of the first instance erased cell among entity erased cell in buffer storage After step, in addition to：Reply write-in and complete information to host computer system.

In one embodiment of this invention, above-mentioned method for writing data also includes：When write caching function has been closed And first data of write instruction when being kept in buffer storage, assign and bring down stocks instruction and perform above-mentioned to use single page sequencing mould Formula writes the data of corresponding first write instruction to the first instance program of first instance erased cell from buffer storage Change the step in unit.

In one embodiment of this invention, above-mentioned method for writing data also includes：In background execution pattern, execution has Data union operation is imitated, so that multiple valid data in first instance erased cell are copied into reality using multipage sequencing pattern In multiple 3rd entity program units of the 3rd entity erased cell among body erased cell, wherein the 3rd entity program Unit is made up of multiple 3rd memory cells and in multipage sequencing pattern, forms the 3rd of the 3rd entity program unit Each the 3rd memory cell among memory cell stores more bit datas.

In one embodiment of this invention, above-mentioned method for writing data also includes：Write caching open command is received, and And the write caching function is opened to respond write caching open command.

In one embodiment of this invention, wherein multipage sequencing pattern is that multistage memory cell sequencing pattern or three ranks are remembered Recall born of the same parents' sequencing pattern, and single page sequencing pattern is single-order memory cell sequencing pattern, lower entity program pattern, mixing Sequencing pattern or few rank memory cell sequencing pattern.

An exemplary embodiment of the invention provides a kind of Memory control for being used to control duplicative Nonvolatile memory module Circuit unit.This memory control circuit unit includes：It is electrically connected to the HPI of host computer system；It is for electrically connecting to To the memory interface of duplicative Nonvolatile memory module, wherein duplicative Nonvolatile memory module has multiple entities Erased cell, each entity erased cell among this little entity erased cell have multiple entity program units；Electrically It is connected to the buffer storage of HPI and memory interface；And it is electrically connected to HPI, memory interface and buffering and deposits The memory management circuit of reservoir.Memory management circuit to：Receive the first write instruction from host computer system, and will it is corresponding this The data of one write instruction are kept in into buffer storage；And when write caching function has been closed and first write instruction When data are kept in buffer storage, the first command sequence is assigned to refer to corresponding first write-in using single page sequencing pattern The data of order are write from buffer storage to the first instance program of the first instance erased cell among entity erased cell Change in unit, wherein first instance programmed cell is made up of multiple first memory cells and in single page sequencing pattern, Each first memory cell among first memory cell of composition first instance programmed cell only stores 1 bit data.

In one example of the present invention embodiment, wherein memory management circuit more to：It is fast that write-in is received from host computer system Out code is taken, and closes write caching function to respond write caching out code.

In one example of the present invention embodiment, wherein from host computer system receive write caching out code running it Before, memory management circuit more to：The second write instruction is received from host computer system and will correspond to the data of the second write instruction Keep in into buffer storage；And the second command sequence is assigned so that buffer storage will be temporarily stored into using multipage sequencing pattern The data of the middle write instruction of correspondence second are write to the second instance journey of the second instance erased cell among entity erased cell Sequence unit, wherein second instance programmed cell are made up of multiple second memory cells and in the multipage sequencing pattern In, form the more bit datas of each second memory cell storage among the second memory cell of second instance programmed cell.

In one example of the present invention embodiment, wherein the number of the first write instruction will be corresponded to using single page sequencing pattern According to from buffer storage write-in to the first instance erased cell among entity erased cell first instance programmed cell In running after, memory management circuit more to：Reply write-in and complete information to host computer system.

In one example of the present invention embodiment, wherein first command sequence brings down stocks to instruct for one, memory management circuit More to：When write caching function has been closed and the data of the first write instruction are kept in buffer storage, according to clear Storehouse instruction perform it is above-mentioned using single page sequencing pattern by the data of corresponding first write instruction write from buffer storage to Running in the first instance programmed cell of first instance erased cell.

In one example of the present invention embodiment, memory management circuit more to：In background execution pattern, perform effective Data union operation, so that multiple valid data in first instance erased cell are copied into entity using multipage sequencing pattern In multiple 3rd entity program units of the 3rd entity erased cell among erased cell, wherein the 3rd entity program list Member is made up of multiple 3rd memory cells and in multipage sequencing pattern, forms the 3rd note of the 3rd entity program unit Recall the more bit datas of each the 3rd memory cell storage among born of the same parents.

In one example of the present invention embodiment, memory management circuit more to：Write caching open command is received, and The write caching function is opened to respond write caching open command.

In one example of the present invention embodiment, wherein multipage sequencing pattern is multistage memory cell sequencing pattern or three Rank memory cell sequencing pattern, and single page sequencing pattern be single-order memory cell sequencing pattern, lower entity program pattern, Combination process pattern or few rank memory cell sequencing pattern.

An exemplary embodiment of the invention provides a kind of internal storing memory.It includes：It is electrically connected to host computer system Connecting interface unit, duplicative Nonvolatile memory module and be electrically connected to connecting interface unit and duplicative is non- The memory control circuit unit of volatile ram module.Wherein memory control circuit unit includes buffer storage, and can make carbon copies Formula Nonvolatile memory has multiple entity erased cells, each entity erased cell tool among this little entity erased cell There are multiple entity program units.Memory control circuit unit to：The first write instruction is received from host computer system, and will be right The data of this first write instruction are answered to keep in into buffer storage；And when write caching function be closed and first write-in When the data of instruction are kept in buffer storage, the first command sequence is assigned so that first will be corresponded to using single page sequencing pattern The data of write instruction are write from buffer storage to the first reality of the first instance erased cell among entity erased cell In body programmed cell, wherein first instance programmed cell is made up of multiple first memory cells and in single page sequencing mould In formula, each first memory cell among the first memory cell of composition first instance programmed cell only stores 1 bit data.

In one example of the present invention embodiment, wherein memory control circuit unit more to：Receive and write from host computer system Enter cache out code, and close write caching function to respond write caching out code.

In one example of the present invention embodiment, wherein from host computer system receive write caching out code running it Before, memory control circuit unit more to：The second write instruction is received from host computer system and will correspond to the second write instruction Data are kept in into buffer storage；And assign the second command sequence and deposited so that buffering will be temporarily stored into using multipage sequencing pattern Correspondingly the data of the second write instruction are write to the second reality of the second instance erased cell among entity erased cell in reservoir Body programmed cell, wherein second instance programmed cell are made up of multiple second memory cells and in the multipage sequencing mould In formula, the more bit datas of each second memory cell storage among the second memory cell of second instance programmed cell are formed.

In one example of the present invention embodiment, wherein the number of the first write instruction will be corresponded to using single page sequencing pattern According to from buffer storage write-in to the first instance erased cell among entity erased cell first instance programmed cell In running after, memory control circuit unit more to：Reply write-in and complete information to host computer system.

In one example of the present invention embodiment, wherein first command sequence brings down stocks to instruct for one, memory control circuit Unit more to：When write caching function has been closed and the data of the first write instruction are kept in buffer storage, root According to bringing down stocks, instruction execution is above-mentioned to be write the data of corresponding first write instruction using single page sequencing pattern from buffer storage Enter to the running in the first instance programmed cell of first instance erased cell.

In one example of the present invention embodiment, memory control circuit unit more to：In background execution pattern, perform Valid data union operation, to be copied to multiple valid data in first instance erased cell using multipage sequencing pattern In multiple 3rd entity program units of the 3rd entity erased cell among entity erased cell, wherein the 3rd entity program Changing unit is made up of multiple 3rd memory cells and in multipage sequencing pattern, the of the 3rd entity program unit of composition Each the 3rd memory cell among three memory cells stores more bit datas.

In one example of the present invention embodiment, memory control circuit unit more to：Write caching open command is received, And the write caching function is opened to respond write caching open command.

It can be effectively prevented from based on above-mentioned, of the invention method for writing data because host computer system powers off cause singularly The loss of data in buffer storage, and ensure that the data of the write instruction before powering off singularly have all stably stored Into duplicative Nonvolatile memory and effectively utilize the space of duplicative Nonvolatile memory.

For features described above of the invention and advantage can be become apparent, special embodiment below, and it is detailed to coordinate accompanying drawing to make Carefully it is described as follows.

Brief description of the drawings

Fig. 1 is host computer system, internal storing memory and input/output (I/O) dress according to an exemplary embodiment The schematic diagram put；

Fig. 2 is host computer system, internal storing memory and the input/output (I/O) according to another exemplary embodiment The schematic diagram of device；

Fig. 3 is the schematic diagram of the host computer system and internal storing memory according to another exemplary embodiment；

Fig. 4 is the summary block diagram of the host computer system and internal storing memory according to an exemplary embodiment；

Fig. 5 A and Fig. 5 B are the models of the memory cell storage framework and entity erased cell according to this exemplary embodiment Illustrate and be intended to；

Fig. 6 is the summary block diagram of the memory control circuit unit according to an exemplary embodiment；

Fig. 7 and Fig. 8 is the example schematic of the management entity erased cell according to an exemplary embodiment；

Fig. 9 be according to an example using single page sequencing pattern write data into duplicative it is non-volatile in The schematic diagram of storing module；

Figure 10 be according to an example using multipage sequencing pattern to the number that is write with single page sequencing pattern According to the schematic diagram for carrying out valid data union operation；

Figure 11 and Figure 12 is the flow chart of the data write-in method according to an exemplary embodiment.

Reference：

10：Internal storing memory

11：Host computer system

12：Input/output (I/O) device

110：System bus

111：Processor

112：Random access memory (RAM)

113：Read-only storage (ROM)

114：Data transmission interface

20：Mainboard

204：Wireless internal storing memory

205：GPS module

206：Network adapter

207：Radio transmitting device

208：Keyboard

209：Screen

210：Loudspeaker

30：Internal storing memory

31：Host computer system

32：SD card

33：CF cards

34：Embedded storage device

341：Embedded multi-media card

342：Embedded type multi-core piece encapsulates storage device

402：Connecting interface unit

404：Memory control circuit unit

406：Duplicative Nonvolatile memory module

410 (0)~410 (N)：Entity erased cell

WL0~WL127：Character line

502：Memory management circuit

504：HPI

506：Memory interface

508：Buffer storage

510：Electric power management circuit

512：Error checking and correcting circuit

602：Information data area

604：Idle area

606：System area

608：Substitute area

LBA (0)~LBA (H)：Logical address

LZ (0)~LZ (M)：Logic region

S1101：Judge whether to receive the step of write caching out code or write caching open command from host computer system Suddenly

S1103：If receive write caching out code from host computer system, close write caching function and write with responding The step of entering cache out code

S1105：If receive write caching open command from host computer system, open write caching function and write with responding The step of entering cache open command

S1201：Receive the first write instruction from host computer system, and by the data of this corresponding the first write instruction keep in Step in buffer storage

S1203：Judge write caching function whether pent step

S1205：When write caching function has been closed, the first write instruction will be corresponded to using single page sequencing pattern Data are write from buffer storage to the first instance sequencing list of the first instance erased cell among entity erased cell Step in member

S1207：When write caching function is not closed, the first write instruction will be corresponded to using multipage sequencing pattern Data are write from buffer storage to the first instance sequencing list of the first instance erased cell among entity erased cell Step in member

Embodiment

In general, internal storing memory (also known as, memory storage system) includes duplicative Nonvolatile memory module With controller (also known as, control circuit unit).Usual internal storing memory is used together with host computer system, so that host computer system It can write data into internal storing memory or data are read from internal storing memory.

Fig. 1 is host computer system, internal storing memory and input/output (I/O) dress according to an exemplary embodiment The schematic diagram put, and Fig. 2 is host computer system, internal storing memory and input according to another exemplary embodiment/defeated Go out the schematic diagram of (I/O) device.

Fig. 1 and Fig. 2 are refer to, host computer system 11 generally comprises processor 111, random access memory (random access Memory, RAM) 112, read-only storage (read only memory, ROM) 113 and data transmission interface 114.Processor 111st, random access memory 112, read-only storage 113 and data transmission interface 114 are all electrically connected to system bus (system bus)110。

In this exemplary embodiment, host computer system 11 is electrical by data transmission interface 114 and internal storing memory 10 Connection.For example, host computer system 11 can write data into internal storing memory 10 via data transmission interface 114 or from memory storage Data are read in cryopreservation device 10.In addition, host computer system 11 is electrically connected with by system bus 110 and I/O devices 12.For example, Output signal can be sent to I/O devices 12 via system bus 110 or receive input letter from I/O devices 12 by host computer system 11 Number.

In this exemplary embodiment, processor 111, random access memory 112, read-only storage 113 and data transfer connect Mouth 114 is on the mainboard 20 for may be provided at host computer system 11.The number of data transmission interface 114 can be one or more.It is logical Data transmission interface 114 is crossed, mainboard 20 can be electrically connected to internal storing memory 10 via wired or wireless way.Memory storage Cryopreservation device 10 can be for example Portable disk 201, memory card 202, solid state hard disc (Solid State Drive, SSD) 203 or wireless Internal storing memory 204.Wireless internal storing memory 204 can be for example wireless near field communication (Near Field Communication Storage, NFC) internal storing memory, radio facsimile (WiFi) internal storing memory, bluetooth (Bluetooth) internal storing memory or low-power consumption bluetooth internal storing memory (for example, iBeacon) etc. are with various radio communication Internal storing memory based on technology.In addition, mainboard 20 can also be electrically connected to global positioning system by system bus 110 System (Global Positioning System, GPS) module 205, network adapter 206, radio transmitting device 207, keyboard 208th, the various I/O devices such as screen 209, loudspeaker 210.For example, in an exemplary embodiment, mainboard 20 can be by being wirelessly transferred dress Put 207 access wireless internal storing memories 204.

In an exemplary embodiment, mentioned host computer system is substantially to coordinate with internal storing memory to store number According to any system.Although in above-mentioned exemplary embodiment, host computer system is explained with computer system, however, Fig. 3 is The schematic diagram of host computer system and internal storing memory according to another exemplary embodiment.Fig. 3 is refer to, in another example In embodiment, host computer system 31 can also be digital camera, video camera, communicator, audio player, video player or flat The systems such as plate computer, and internal storing memory 30 can be its used SD card 32, CF cards 33 or embedded storage device 34 etc. Various nonvolatile memory storage device.Embedded storage device 34 include embedded multi-media card (embedded MMC, EMMC) 341 and/or embedded type multi-core piece encapsulation storage device (embedded Multi Chip Package, eMCP) 342 etc. The all types of embedded storage devices being directly electrically connected at memory modules on the substrate of host computer system.

Fig. 4 is the summary block diagram of the host computer system and internal storing memory according to an exemplary embodiment.

Fig. 4 is refer to, internal storing memory 10 includes connecting interface unit 402, memory control circuit unit 404 with that can answer Write formula Nonvolatile memory module 406.

In this exemplary embodiment, connecting interface unit 402 is compatible with the advanced annex of sequence (Serial Advanced Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the invention is not restricted to this, connecting interface unit 402 can also meet advanced annex (Parallel Advanced Technology Attachment, PATA) mark side by side Accurate, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, USB (Universal Serial Bus, USB) standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) interface standard, the generation of ultrahigh speed two (Ultra High Speed-II, UHS-II) interface standard, peace Digital (Secure Digital, SD) interface standard, memory stick (Memory Stick, MS) interface standard, multi-chip package (Multi-Chip Package) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, insertion Formula Multi Media Card (Embedded Multimedia Card, eMMC) interface standard, Common Flash Memory (Universal Flash Storage, UFS) interface standard, embedded type multi-core piece encapsulation (embedded Multi Chip Package, eMCP) Interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other suitable standards.In this exemplary embodiment, connecting interface unit 402 It can be encapsulated in memory control circuit unit 404 in a chip, or connecting interface unit 402 is to be laid in one to include internal memory Outside the chip of control circuit unit.

Memory control circuit unit 404 is performing multiple gates or control with hardware pattern or firmware pattern implementation Instruct, and the write-in of data is carried out in duplicative Nonvolatile memory module 406 according to the instruction of host computer system 11, read The running such as take and erase.

Duplicative Nonvolatile memory module 406 is electrically connected to memory control circuit unit 404, and to store up Deposit the data that host computer system 11 is write.Duplicative Nonvolatile memory module 406 have entity erased cell 410 (0)~ 410(N).For example, entity erased cell 410 (0)~410 (N) can belong to same internal memory crystal grain (die) or belong to different Internal memory crystal grain.Each entity erased cell has a plurality of entity program units respectively, is erased wherein belonging to same entity The entity program unit of unit can be written independently and simultaneously be erased.However, it is necessary to be appreciated that, the present invention is unlimited In this, each entity erased cell is can be by 64 entity program units, 256 entity program units or other any Entity program unit is formed.

In more detail, entity erased cell is the least unit erased.That is, each entity erased cell contains minimum number The memory cell being erased in the lump of mesh.Entity program unit is the minimum unit of sequencing.That is, entity program unit is to write Enter the minimum unit of data.Each entity program unit generally includes data bit area and redundant digit area.Data bit area includes more Individual entity access address to store the data of user, and redundant digit area to stocking system data (for example, control information with Error correcting code).In this exemplary embodiment, it can be deposited in the data bit area of each entity program unit comprising 8 entities Address is taken, and the size of an entity access address is 512 bytes (byte).However, in other exemplary embodiments, data bit Also can include the more or less entity access addresses of number in area, the present invention be not intended to limit entity access address size and Number.For example, in an exemplary embodiment, entity erased cell is physical blocks, and entity program unit is physical page Face or entity sector, but the present invention is not limited.

In this exemplary embodiment, duplicative Nonvolatile memory module 406 is multistage memory cell (Multi Level Cell, MLC) NAND-type flash memory module (that is, the flash memory module that 2 data bit can be stored in a memory cell).It is however, of the invention Not limited to this, duplicative Nonvolatile memory module 406 also can be three rank memory cells (Trinary Level Cell, TLC) NAND-type flash memory module (that is, the flash memory module that 3 data bit can be stored in a memory cell) or other there is identical characteristic Memory modules.

Fig. 5 A and Fig. 5 B are the models of the memory cell storage framework and entity erased cell according to this exemplary embodiment Illustrate and be intended to.In this exemplary embodiment, illustrated using MLC NAND-type flash memories as example.

Fig. 5 A are refer to, each memory cell of duplicative Nonvolatile memory module 406 can store the data of 2 positions, And the storing state of each memory cell can be identified as " 11 ", " 10 ", " 01 " or " 00 ".Each of which storing state bag Include least significant bit (Least Significant Bit, LSB) and highest significant position (Most Significant Bit, MSB).For example, the value for the 1st position counted in storing state from left side is LSB, and the value for the 2nd position counted from left side is MSB.Therefore, 2 entity program units can be formed by being connected to the online several memory cells of same character, wherein thus a little notes Recall the referred to as lower entity program unit of entity program unit that the LSB of born of the same parents is formed, and the thus MSB institutes group of a little memory cells Into entity program unit be referred to as upper entity program unit.

Fig. 5 B are refer to, an entity erased cell is made up of multiple entity program unit groups, wherein each real Body programmed cell group includes the lower entity program unit formed by being arranged in the online several memory cells of same character With upper entity program unit.For example, in entity erased cell, belong to the 0th physical page of lower entity program unit What the 1st physical page with belonging to upper entity program unit was made up of the memory cell being arranged on character line WL0, because This can be considered as an entity program unit group.Similarly, the 2nd entity program unit, the 3rd entity program unit It is made up of the memory cell being arranged on character line WL1, therefore an entity program unit group can be considered as, and according to It is also to be divided into multiple entity program unit groups according to this mode that this, which analogizes other entity program units,.

Fig. 6 is the summary block diagram of the memory control circuit unit according to an exemplary embodiment.

Fig. 6 is refer to, memory control circuit unit 404 includes memory management circuit 502, HPI 504 connects with internal memory Mouth 506, buffer storage 508, electric power management circuit 510 and error checking and correcting circuit 512.

Memory management circuit 502 is controlling the overall operation of memory control circuit unit 404.Specifically, internal memory pipe Reason circuit 502 has multiple control instructions, and when internal storing memory 10 operates, this little control instruction can be performed to enter The write-in of row data, read and the running such as erase.

In this exemplary embodiment, the control instruction of memory management circuit 502 is to carry out implementation with firmware pattern.It is for example, interior Depositing management circuit 502 has microprocessor unit (not shown) and read-only storage (not shown), and this little control instruction is By in imprinting so far read-only storage.When internal storing memory 10 operates, this little control instruction can by microprocessor unit Lai Perform to carry out the write-in of data, read and the running such as erase.

Fig. 7 and Fig. 8 is the example schematic of the management entity erased cell according to an exemplary embodiment.

It will be appreciated that it is described herein the running of the entity erased cell of duplicative Nonvolatile memory module 406 When, it is concept in logic to carry out application entity erased cell with the word such as " extraction ", " packet ", " division ", " association ".Namely Say, the physical location of the entity erased cell of duplicative Nonvolatile memory module is not changed, but pair can be answered in logic The entity erased cell for writing formula Nonvolatile memory module is operated.

Fig. 7 is refer to, memory control circuit unit 404 (or memory management circuit 502) can be by entity erased cell 410 (0)~410 (N) is logically grouped into data field 602, idle area 604, system area 606 and substitution area 608.

The entity erased cell for logically belonging to data field 602 and idle area 604 is to store to come from host computer system 11 data.Specifically, the entity erased cell of data field 602 is regarded as having stored the entity erased cell of data, and The entity erased cell in idle area 604 is the entity erased cell to replacement data area 602.That is, work as from main frame system When system 11 receives write instruction with the data to be write, memory management circuit 502 can use extracts entity from idle area 604 Erased cell writes data, with the entity erased cell in replacement data area 602.

The entity erased cell for logically belonging to system area 606 is to record system data.For example, system data includes Erased on the manufacturer of duplicative Nonvolatile memory module and the entity of model, duplicative Nonvolatile memory module Unit number, entity program unit number of each entity erased cell etc..

It is to be used for bad entity erased cell substitution program to logically belong to substitute the entity erased cell in area 608, to take The entity erased cell of generation damage.Specifically, if still having normal entity erased cell and data in substitution area 608 During the entity erased cell damage in area 602, memory management circuit 502 can extract normal entity from substitution area 608 and erase list Member changes the entity erased cell of damage.

Particularly, the quantity meeting of data field 602, idle area 604, system area 606 and the entity erased cell in substitution area 608 It is different according to different memory standards.Further, it is necessary to be appreciated that, in the running of internal storing memory 10, entity Erased cell is associated to data field 602, idle area 604, system area 606 with substituting the packet relation in area 608 dynamically to change. For example, when the entity erased cell damage in idle area 604 is substituted the entity erased cell substitution in area 608, then originally The entity erased cell in substitution area 608 can be associated to idle area 604.

Fig. 8 is refer to, memory control circuit unit 404 (or memory management circuit 502) can configure logical address LBA (0) To map the entity erased cell of data field 602, there are each of which logical address~LBA (H) multiple logic units to map The entity program unit of corresponding entity erased cell.Also, when 11 logical address to be write data to of host computer system or more When being newly stored in the data in logical address, memory control circuit unit 404 (or memory management circuit 502) can be from idle area An entity erased cell is extracted in 604 as start entity erased cell to write data, with the entity for data field 602 of rotating Erased cell.Also, when this is fully written as the entity erased cell of start entity erased cell, memory control circuit unit The entity erased cell that 404 (or memory management circuits 502) can extract sky from idle area 604 again is erased list as start entity Member, to continue to write to updating the data for the corresponding write instruction for coming from host computer system 11.In addition, it can be used when in idle area 604 The number of entity erased cell when being less than default value, memory control circuit unit 404 (or memory management circuit 502) can perform Valid data union operation (being also known as, collecting garbage (garbage collection) operation) is come in the area 602 that arrays data Valid data, the entity erased cell without storage valid data in data field 602 is associated to idle area 604 again.

In order to identify which entity erased cell is the data of each logical address be stored in, in this exemplary embodiment, Memory control circuit unit 404 (or memory management circuit 502) can record the mapping between logical address and entity erased cell. For example, in this exemplary embodiment, memory control circuit unit 404 (or memory management circuit 502) can be non-easily in duplicative Stored logic-entity mapping records the entity erased cell that each logical address is mapped in the property lost memory modules 406.When Logic-entity mapping can be loaded onto slow by memory control circuit unit 404 (or memory management circuit 502) during data to be accessed Memory 508 is rushed to safeguard, and write or read data according to logic-entity mapping.

It is noted that record reflecting for all logical addresses because the finite capacity of buffer storage 508 can not store The mapping table of relation is penetrated, therefore, in this exemplary embodiment, memory control circuit unit 404 (or memory management circuit 502) meeting Logical address LBA (0)~LBA (H) is grouped into multiple logic region LZ (0)~LZ (M), and configured for each logic region One logic-entity mapping.Particularly, when memory control circuit unit 404 (or memory management circuit 502) is intended to update some During the mapping of logical address, buffering can be loaded on by corresponding to logic-entity mapping of the logic region belonging to this logical address Memory 508 is updated.

In another exemplary embodiment of the present invention, the control instruction of memory management circuit 502 can also program code pattern The specific region of duplicative Nonvolatile memory module 406 is stored in (for example, being exclusively used in storage system data in memory modules System area) in.In addition, memory management circuit 502 have microprocessor unit (not shown), read-only storage (not shown) and Random access memory (not shown).Particularly, this read-only storage has driving code, and works as memory control circuit unit 404 When being enabled, microprocessor unit, which can first carry out this driving code section, will be stored in duplicative Nonvolatile memory module 406 In control instruction be loaded onto in the random access memory of memory management circuit 502.Afterwards, it is a little to operate this for microprocessor unit Control instruction is to carry out the write-in of data, read and the running such as erase.

In addition, in another exemplary embodiment of the present invention, the control instruction of memory management circuit 502 can also a hardware-type Formula carrys out implementation.Read for example, memory management circuit 502 includes microcontroller, memory cell management circuit, internal memory write circuit, internal memory Sense circuit, internal memory are erased circuit and data processing circuit.It is memory cell management circuit, internal memory write circuit, internal memory reading circuit, interior Deposit circuit of erasing and be electrically connected to microcontroller with data processing circuit.Wherein, memory cell management circuit can answer to manage Write the entity erased cell of formula Nonvolatile memory module 406；Internal memory write circuit is to duplicative Nonvolatile memory Module 406 assigns write instruction to write data into duplicative Nonvolatile memory module 406；Internal memory reading circuit is used To assign reading instruction to duplicative Nonvolatile memory module 406 with from duplicative Nonvolatile memory module 406 Read data；Internal memory erase circuit to duplicative Nonvolatile memory module 406 is assigned erase instruction with by data from Erased in duplicative Nonvolatile memory module 406；And data processing circuit to handle be intended to write it is non-easily to duplicative The data of the property lost memory modules 406 and the data read from duplicative Nonvolatile memory module 406.

Referring again to Fig. 6, HPI 504 is electrically connected to memory management circuit 502 and is electrically connected to Connecting interface unit 402, to receive and identify instruction and data that host computer system 11 transmitted.That is, host computer system 11 The instruction transmitted can be sent to memory management circuit 502 with data by HPI 504.In this exemplary embodiment, HPI 504 is compatible with SATA standard.However, it is necessary to it is appreciated that HPI 504 can also the invention is not restricted to this PATA standards, the standards of IEEE 1394, PCI Express standards, USB standard, UHS-I interface standards, UHS-II is compatible with to connect Mouth standard, SD standards, MS standards, MMC standards, CF standards, IDE standards or other suitable data transmission standards.

Memory interface 506 be electrically connected to memory management circuit 502 and to access duplicative it is non-volatile in Storing module 406.That is, the data for being intended to write to duplicative Nonvolatile memory module 406 can be via memory interface 506 Be converted to the receptible form of the institute of duplicative Nonvolatile memory module 406.

Buffer storage 508 is electrically connected to memory management circuit 502 and is configured to temporarily store come from host computer system 11 Temporal data and instruction or come from the data of duplicative Nonvolatile memory module 406.

Electric power management circuit 510 is electrically connected to memory management circuit 502 and to control internal storing memory 10 Power supply.

Error checking is electrically connected to memory management circuit 502 and to perform error checking with correcting circuit 512 With correction program to ensure the correctness of data.For example, refer to when memory management circuit 502 receives write-in from host computer system 11 When making, error checking can be error checking and correcting code corresponding to the data generation of this corresponding write instruction with correcting circuit 512 (Error Checking and Correcting Code, ECC Code), and memory management circuit 502 can write corresponding this The data for entering instruction are write into duplicative Nonvolatile memory module 406 with corresponding error checking and correcting code.Afterwards, This data pair can be read simultaneously when memory management circuit 502 reads data from duplicative Nonvolatile memory module 406 The error checking answered and correcting code, and error checking is understood according to this error checking with correcting code to being read with correcting circuit 512 The data taken perform error checking and correction program.

Zhi get being, in this exemplary embodiment, memory control circuit unit 404 (memory management circuit 502) can be not With state using different sequencing patterns come by Data programming to duplicative Nonvolatile memory module 406.For example, Memory control circuit unit 404 (memory management circuit 502) can be used single page sequencing pattern or multipage sequencing pattern by Data programming is to entity erased cell.Here, based on single page sequencing pattern come the sequencing speed meeting of programmable memory cell Higher than based on multipage sequencing pattern come the sequencing speed of programmable memory cell (that is, using multipage sequencing pattern come program The required operating time for changing data is more than the required operating time for carrying out programming data using single page sequencing pattern), and be based on Single page sequencing pattern and the reliability of data that is stored is also often higher than the number being stored based on multipage sequencing pattern According to reliability.Single page sequencing pattern is, for example, single-order memory cell (single layer memory cell, SLC) sequencing Pattern, lower entity program (lower physical programming) pattern, combination process (mixture Programming) one of pattern and few rank memory cell (less layer memory cell) sequencing pattern.It is more detailed For thin, in single-order memory cell pattern, a memory cell only stores the data of a position.In lower entity program pattern, Entity program unit is only descended to be programmed, and the upper entity program unit corresponding to this lower entity program unit can It is not programmed.In combination process pattern, valid data (or, True Data) can be programmed in lower entity program list In member, and simultaneously virtual data (dummy data) can be programmed into storage valid data lower entity program unit institute it is right In the upper entity program unit answered.In few rank memory cell pattern, a memory cell stores the data of the position of one first number, For example, this first number can be set to " 1 ".Multipage sequencing pattern is, for example, multistage memory cell (MLC) sequencing pattern, three ranks (TLC) memory cell sequencing pattern or icotype.In multipage sequencing pattern, a memory cell stores one second number Position data, wherein this second number is equal to or more than " 2 ".For example, this second number can be set to 2 or 3.It is real in another example Apply in example, the first number in above-mentioned single page sequencing pattern all can be other with the second number in multipage sequencing pattern Number, as long as meeting that the second number is more than the first number.In other words, each of first kind entity erased cell is formed The number (i.e. the first number) of memory cell position data stored after using single page sequencing model program, which can be less than, to be formed Each memory cell of second class entity erased cell position data stored after using multipage sequencing model program Number (i.e. the second number).

In this exemplary embodiment, when host computer system 11 and duplicative Nonvolatile memory module 406 are on just During the state of electricity, memory control circuit unit 104 (or memory management circuit 502) can be defaulted as using multipage sequencing pattern To write data into duplicative Nonvolatile memory module 406.Specifically, it is assumed that host computer system 11 and can make carbon copies When formula Nonvolatile memory module 406 is in the just state of upper electricity, when (or the memory management circuit of memory control circuit unit 104 502) when receiving write instruction (below with reference to for the second write instruction) from host computer system 11, memory control circuit unit 104 Data corresponding to this write instruction can first be kept in into buffer storage 508 exist side by side first by (or memory management circuit 502) The write-in for replying this corresponding the second write instruction completes information to host computer system 11.Afterwards in due course machine when, it is such as interior Deposit control circuit unit 104 (or memory management circuit 502) receive from host computer system 11 bring down stocks instruct (flush Command when), data volume one threshold value of arrival in buffer storage 508 or the free time of host computer system 11 cross a threshold value, The second command sequence can just be assigned and correspond to the second write-in will be temporarily stored into buffer storage 508 using multipage sequencing pattern The data of instruction are write to the entity erased cell in duplicative Nonvolatile memory module 406 (below with reference to for second is real Body erased cell) at least one entity program unit (below with reference to for second instance programmed cell).Here, by It is that sequencing is come with multipage sequencing pattern in second instance erased cell, therefore, the list as described above, composition second instance is erased The memory cell of the entity program unit of member can be programmed to store more bit datas.That is, in multipage sequencing mould Under formula, the upper entity program of lower entity program unit and second instance erased cell in above-mentioned second instance erased cell Unit can be used to write data.

It is to be noted that in order to avoid host computer system because power off singularly and caused by be stored in buffer storage The loss of data, in this exemplary embodiment, user can assign write caching by host computer system 11 and close (disable Write cache) instruct to close the write caching function of internal storing memory 10.Wherein, closing write caching function can be with The data for reducing write instruction are temporarily stored in the time of buffer storage 508.In other words, when memory control circuit unit 104 (or Memory management circuit 502) closed according to write caching after closing write caching function, assign write-in when host computer system 11 and refer to When making, the data of this write instruction can be immediately written into after keeping in buffer storage 508 to duplicative it is non-volatile in In storing module 406.

In addition, when memory control circuit unit 104 (or memory management circuit 502) receives writing from host computer system 11 , may be because of the write instruction of more after entering cache out code, and write excessive redundant data and cause " write-in amplification The problem of (write amplification) ".The problem of amplifying in order to avoid write-in is simultaneously efficiently non-easily using duplicative Lose property memory modules 406 storage area, in this exemplary embodiment, when memory control circuit unit 104 (or memory management electricity Road 502) after host computer system 11 receives write caching out code, memory control circuit unit 104 (or memory management circuit 502) single page sequencing pattern can be used instead to be write to duplicative Nonvolatile memory module 406.

Specifically, Fig. 9 is to write data into duplicative using single page sequencing pattern according to an example The schematic diagram of Nonvolatile memory module.

Closed assuming that memory control circuit unit 104 (or memory management circuit 502) receives write caching from host computer system 11 Close instruction.After write caching out code is received, memory control circuit unit 104 (or memory management circuit 502) can close Write caching function is closed to respond write caching out code.Afterwards, when internal storing memory 10 receives from host computer system 11 To instruction by the write instruction of data storage to logic unit LBA (0) the 0th~255 logical subunit (below with reference to for, First write instruction) when, memory control circuit unit 104 (or memory management circuit 502) first can be by this first write instruction Data keep in into buffer storage 508.Now, because write caching function has been closed, memory control circuit unit 104 (or memory management circuit 502) can accordingly assign the first command sequence.In this exemplary embodiment, the first command sequence is clear Storehouse instructs (flush command), and memory control circuit unit 104 (or memory management circuit 502) can be according to bringing down stocks to instruct It is using single page sequencing pattern that the data of corresponding first write instruction are non-from the Program of buffer storage 508 to duplicative In volatile ram module 406.

For example, refer to Fig. 9, memory control circuit unit 104 (or memory management circuit 502) for example can be from idle area Extracted in 604 2 entity erased cells 510 (F), 510 (F+1) (below with reference to for first instance erased cell) respectively as Corresponding to multiple start entity erased cells of above-mentioned first write instruction.Memory control circuit unit 104 (or memory management electricity Road 502) data of the first write instruction can be used into single page sequencing pattern from buffer storage according to the first command sequence Write-in is (following into the entity program unit of entity erased cell 510 (F) and entity erased cell 510 (F+1) in 508 It is referenced as, first instance programmed cell).Here, due to entity erased cell 510 (F) and (F+ of entity erased cell 510 1) it is that sequencing is come with single page sequencing pattern, therefore, as described above, composition entity erased cell 510 (F) and entity are erased The memory cell of the entity program unit of unit 510 (F+1) can be programmed to store 1 bit data.That is, in single page Under sequencing pattern, the lower entity program unit of entity erased cell 510 (F) and entity erased cell 510 (F+1) can quilt Using writing data and the upper entity program unit of entity erased cell 510 (F) and entity erased cell 510 (F+1) It will not be used to write data.

Specifically, as shown in figure 9, memory control circuit unit 104 (or memory management circuit 502) can be intended to storage extremely The data of logic unit LBA (0) the 0th~127 logical subunit write to entity erased cell 510 (F) in order Entity program unit and be intended to storage to logic unit LBA (0) the 128th~255 logical subunit data sequentially Ground is write into the lower entity program unit of entity erased cell 510 (F+1).That is, memory control circuit unit 104 (or memory management circuit 502) is using single page sequencing pattern by the data of corresponding first write instruction from buffer storage 508 It is middle write-in into duplicative Nonvolatile memory module the lower entity program unit of 406 entity erased cells 510 (F) and In the lower entity program unit of entity erased cell 510 (F+1) and entity erased cell 510 (F) upper entity program list The upper entity program unit of member and entity erased cell 510 (F+1) will not be used to write data.

The data of corresponding first write instruction are being write from buffer storage 508 to can using single page sequencing pattern Lower the entity program unit and entity of entity erased cell 510 (F) in manifolding formula Nonvolatile memory module 406 are erased After the running of the lower entity program unit of unit 510 (F+1), memory control circuit unit 104 (or memory management circuit 502) can be by entity erased cell 510 (F) and entity erased cell 510 (F+1) association to data field 602, and reply and write Enter to complete information to host computer system 11 to respond the first write instruction that host computer system 11 is assigned.That is, in this example In embodiment, after write caching function is closed, when host computer system 11 assigns write instruction and receives corresponding to this write-in When information is completed in the write-in of instruction, the data for representing this write instruction have stably been stored to duplicative Nonvolatile memory In module 406.Compared to general write operation (that is, data memory control circuit unit after being kept in buffer storage 508 104 (or memory management circuits 502) reply write-in and complete information to host computer system 11 immediately), the memory storage of this exemplary embodiment Cryopreservation device 10 more can ensure that the data of write instruction be written into duplicative Nonvolatile memory module 406 and can reduce because Host computer system 11 powers off the loss for the data for causing to be temporarily stored in buffer storage 508 singularly.

It is noted that row write is entered to duplicative Nonvolatile memory module 406 when using single page sequencing pattern instead It is fashionable, by the upper entity program of start entity erased cell extracted from duplicative Nonvolatile memory module 406 Unit will not be used to write data, therefore the space that the start entity erased cell extracted can be written into only is left originally in fact The half in the space of body erased cell.In order to not reduce the duplicative Nonvolatile memory module under single page sequencing pattern 406 capacity that can be stored, in this exemplary embodiment, memory control circuit unit 104 (or memory management circuit 502) can make Valid data union operation is carried out to the data write with single page sequencing pattern with multipage sequencing pattern.

Figure 10 be according to an example using multipage sequencing pattern to the number that is write with single page sequencing pattern According to the schematic diagram for carrying out valid data union operation.

Assuming that counterlogic unit LBA (0) entity erased cell 510 (F), entity erased cell 510 (F+1) have stored The valid data (as shown in Figure 9) of logic unit LBA (0) all logical subunits, and when internal storing memory 10 is in one During background execution pattern, for example, internal storing memory 10 belong to idle state for a period of time (for example, 30 seconds not from host computer system 11 In receive instruction (for example, write instruction, read instruction, bring down stocks instruction, housekeeping instruction (trim command) etc.)) either When the number of the hollow entity erased cell in idle area 504 is less than acquiescence threshold value, memory control circuit unit 104 (or it is interior Deposit management circuit 502) valid data union operation can be performed.

Specifically, when internal storing memory 10 does not receive instruction for 30 seconds because idle from host computer system 11, or Be when the number of the hollow entity erased cell in idle area 504 is less than acquiescence threshold value, memory control circuit unit 104 (or Memory management circuit 502) valid data union operation can be performed.Figure 10 is refer to, it is (or interior in memory control circuit unit 104 Deposit management circuit 502) perform valid data union operation when, memory control circuit unit 104 (or memory management circuit 502) meeting Such as one entity erased cell of extraction is (following as the entity erased cell 510 (F+2) for rotating from idle area 604 It is referenced as, the 3rd entity erased cell).Specifically, memory control circuit unit 104 (or memory management circuit 502) can be from The entity erased cell of an empty entity erased cell or stored data for invalid data is selected in idle area 604. Particularly, if the entity erased cell extracted is when storing the entity erased cell of invalid data, memory control circuit list First 104 (or memory management circuits 502) first can perform operation of erasing to this entity erased cell.The list that is, entity is erased Invalid data in member must be first erased.

Afterwards, memory control circuit unit 104 (or memory management circuit 502) is smeared entity using multipage sequencing pattern Except multiple valid data in unit 510 (F) and entity erased cell 510 (F+1) are copied to duplicative Nonvolatile memory In the entity program unit in entity erased cell 510 (F+2) in module 406.Here, due to entity erased cell 510 (F+2) it is that sequencing is come with multipage sequencing pattern, therefore, as described above, forming the entity of entity erased cell 510 (F+2) The memory cell of programmed cell can be programmed to store more bit datas.That is, under multipage sequencing pattern, entity The upper entity program unit meeting of lower the entity program unit and entity erased cell 510 (F+2) of erased cell 510 (F+2) It is used to write data.

Specifically, memory control circuit unit 104 (or memory management circuit 502) can be from entity erased cell 510 (F) Lower entity program unit in will belong to logic unit LBA (0) the 0th~127 logical subunit valid data write-in (or Replicate) to entity erased cell 510 (F+2) corresponding page (for example, the 0th~127 entity program unit).Then, internal memory Control circuit unit 104 (or memory management circuit 502) can be from the lower entity program of temporary entity erased cell 510 (F+1) The valid data for the 128th~255 logical subunit for belonging to logic unit LBA (0) are copied to entity erased cell in unit 510 (F+2) corresponding page (for example, the 128th~255 entity program unit).That is, in multipage sequencing pattern Under, the 0th~255 entity program unit of entity erased cell 510 (F+2) is (below with reference to for the 3rd entity program list Member) it can all be used to write data.

That is, when performing valid data union operation, the entity erased cell of data field 602 to be associated to is Operated with multipage sequencing pattern, therefore, write to entity erased cell 510 (F+2) be using entity program unit group as Unit comes while or periodically sequencing.Specifically, in an exemplary embodiment, the of entity erased cell 510 (F+2) 0, the 1st entity program unit can simultaneously be programmed and belong to the 0th, the 1st of logic unit LBA (0) to write The data of logical subunit；The 2nd of entity erased cell 510 (F+2), the 3rd entity program unit can be simultaneously by journey Sequence is to write the data for the 2nd, the 3rd logical subunit for belonging to logic unit LBA (0)；And other are patrolled by that analogy The data for collecting subelement are written into units of entity program unit group into entity erased cell 510 (F+2).

Finally, memory control circuit unit 104 (or memory management circuit 502) be able to will patrol in logic-entity mapping Unit LBA (0) is collected to map to entity erased cell 510 (F+2) and perform entity erased cell 510 (F)~510 (F+1) Erase and operate and associate entity erased cell 510 (F)~510 (F+1) to idle area 604 again.That is, in execution During rear write instruction, the entity erased cell 510 (F)~510 (F+1) being erased can be selected as what is write again The start entity erased cell of logic unit.

By above-mentioned valid data union operation, it can be ensured that duplicative Nonvolatile memory module 406 can store Capacity will not be write and be reduced because of previously used single page sequencing pattern.

Opened it is noted that the user of internal storing memory 10 can also assign a write caching by host computer system 11 (enable write cache) instruction is opened, and memory control circuit unit 104 (or memory management circuit 502) is received and write Write caching function can be opened to respond write caching open command after entering cache open command, it is non-to recover original duplicative Volatile ram module 406 gives tacit consent to the function of with multipage sequencing pattern write data.

Specifically, memory control circuit unit 104 (or memory management circuit 502) can be received from host computer system 11 and used The write caching open command that family is assigned.When memory control circuit unit 104 (or memory management circuit 502) receives write caching After open command, memory control circuit unit 104 (or memory management circuit 502) can open write caching function and be write with responding Enter cache open command.Afterwards, when memory control circuit unit 104 (or memory management circuit 502) from host computer system 11 again When receiving write instruction, memory control circuit unit 104 (or memory management circuit 502) can be by the number of this corresponding write instruction Information is completed to host computer system according to the write-in kept in into buffer storage 508 and immediately reply this corresponding the 3rd write instruction 11.Afterwards in due course machine when, such as memory control circuit unit 104 (or memory management circuit 502) received from main frame The data volume brought down stocks in instruction, buffer storage 508 of system 11 reaches a threshold value or the free time of host computer system 11 crosses one During threshold value, the data being temporarily stored into buffer storage 508 can just be write using multipage sequencing pattern non-to duplicative At least one entity program unit at least one entity erased cell in volatile ram module 406.It is same as State, under multipage sequencing pattern, the above-mentioned lower entity program unit that be used to write in the entity program unit of data It can be used to write data with upper entity program unit.

That is, the user of internal storing memory 10 can be optionally fast using write caching out code or write-in Open command is taken accordingly to turn off or on write caching function.

Figure 11 is refer to, in step S1101, memory control circuit unit 104 (or memory management circuit 502) can judge Whether from host computer system 11 write caching out code or write caching open command are received.If memory control circuit unit 104 (or memory management circuits 502) from host computer system 11 receive write caching out code when, in step S1103, internal memory Control circuit unit 104 (or memory management circuit 502) can close write caching function to respond write caching out code.If If memory control circuit unit 104 (or memory management circuit 502) from host computer system 11 receive write caching open command when, In step S1105, memory control circuit unit 104 (or memory management circuit 502) can open write caching function to respond Write caching open command.

Figure 12 is refer to, in step S1201, memory control circuit unit 104 (or memory management circuit 502) is from main frame System 11 receives the first write instruction, and the data of this corresponding the first write instruction are kept in into buffer storage 508.Connect , in step S1203, whether memory control circuit unit 104 (or memory management circuit 502) can judge write caching function It has been closed.When write caching function has been closed, in step S1205, memory control circuit unit 104 (or internal memory pipe Reason circuit 502) the first command sequence can be assigned so that the data of corresponding first write instruction to be postponed using single page sequencing pattern Rush in memory 508 and write into the first instance programmed cell of the first instance erased cell among entity erased cell. For example, in an exemplary embodiment, memory control circuit unit 104 (or memory management circuit 502) can immediately be produced and brought down stocks Instruction, and according to this bring down stocks instruction using single page sequencing pattern by the data of corresponding first write instruction from buffer storage Write-in is into the first instance programmed cell of the first instance erased cell among entity erased cell in 508.

In addition, when write caching function is not closed, in step S1207, memory control circuit unit 104 (or it is interior Deposit management circuit 502) assign the second command sequence with using multipage sequencing pattern by the data of corresponding first write instruction from Write in buffer storage 508 to the first instance programmed cell of the first instance erased cell among entity erased cell In.It is to be noted, however, that when write caching function is not closed and the data of the first write instruction are kept in buffer-stored During device, memory control circuit unit 104 (or memory management circuit 502) can not have to immediately perform above-mentioned steps 1207.Tool For body, memory control circuit unit 104 (or memory management circuit 502) can machine, such as come from receiving in due course The data volume brought down stocks to instruct in (flush command) or buffer storage 508 of host computer system 11 reach a threshold value or During into background execution pattern, above-mentioned step S1207 is just performed.

In summary, method for writing data of the invention can be effectively prevented from because host computer system powers off cause singularly The loss of data in buffer storage, and ensure that the data of the write instruction before powering off singularly have all stably stored Into duplicative Nonvolatile memory.In addition, the method for writing data of the present invention can also avoid the problem of " write-in amplification " And the space of duplicative Nonvolatile memory can be effectively utilized.

Although the present invention is disclosed as above with embodiment, so it is not limited to the present invention, any art Middle those of ordinary skill, without departing from the spirit and scope of the present invention, when a little change and retouching can be made, in the present invention In protection domain.

Claims

A kind of 1. method for writing data, for a duplicative Nonvolatile memory module, it is characterised in that the duplicative Nonvolatile memory module has multiple entity erased cells, and each entity among the multiple entity erased cell is erased Unit has multiple entity program units, and the method for writing data includes：

One first write instruction is received from a host computer system, and a data of corresponding first write instruction are kept in one In buffer storage；And

When a write caching function has been closed and the data of first write instruction are kept in the buffer-stored During device, the data of corresponding first write instruction are write from the buffer storage using a single page sequencing pattern Enter into an at least first instance programmed cell for the first instance erased cell among the multiple entity erased cell,

A wherein described at least first instance programmed cell is made up of multiple first memory cells and in the single page program In change pattern, form described in an at least first instance programmed cell the multiple first memory cell among each first Memory cell only stores 1 bit data.
2. method for writing data according to claim 1, it is characterised in that also include：

A write caching out code is received from the host computer system, and closes said write cache function to respond described write Enter cache out code.
3. method for writing data according to claim 2, it is characterised in that it is fast to receive said write from the host computer system Before the step of taking out code, in addition to：

From the host computer system receive one second write instruction and by a data of corresponding second write instruction keep in In the buffer storage；And

The data that correspond to second write instruction in the buffer storage will be temporarily stored into using a multipage sequencing pattern to write Enter to an at least second instance programmed cell for the second instance erased cell among the multiple entity erased cell,

A wherein described at least second instance programmed cell is made up of multiple second memory cells and in the multipage program In change pattern, form described in an at least second instance programmed cell the multiple second memory cell among each second Memory cell stores more bit datas.
4. method for writing data according to claim 1, it is characterised in that will be corresponding using the single page sequencing pattern The data of first write instruction are write to the multiple entity erased cell from the buffer storage After step in an at least first instance programmed cell for the first instance erased cell, in addition to：

Reply a write-in and complete information to the host computer system.
5. method for writing data according to claim 1, it is characterised in that also include：

When said write cache function be closed and the data of first write instruction kept in it is described buffering deposit During reservoir, assign one and bring down stocks the above-mentioned institute that first write instruction will be corresponded to using the single page sequencing pattern of instruction execution Data are stated to write from the buffer storage to an at least first instance sequencing described in the first instance erased cell Step in unit.
6. method for writing data according to claim 1, it is characterised in that also include：

In a background execution pattern, a valid data union operation is performed, to use the multipage sequencing pattern by described in One the 3rd entity that multiple valid data in first instance erased cell are copied among the multiple entity erased cell is smeared Except in multiple 3rd entity program units of unit,

Wherein the multiple 3rd entity program unit is made up of multiple 3rd memory cells and in the multipage sequencing In pattern, each the 3rd memory among the multiple 3rd memory cell of the multiple 3rd entity program unit is formed Born of the same parents store more bit datas.
7. method for writing data according to claim 1, it is characterised in that also include：

A write caching open command is received, and opens said write cache function and is referred to responding said write cache and opening Order.
8. method for writing data according to claim 1, it is characterised in that

The multipage sequencing pattern is a multistage memory cell sequencing pattern or one or three rank memory cell sequencing patterns, and institute It is a single-order memory cell sequencing pattern, once entity program pattern, a combination process pattern to state single page sequencing pattern An or few rank memory cell sequencing pattern.
A kind of 9. memory control circuit unit, for controlling a duplicative Nonvolatile memory module, it is characterised in that described Memory control circuit unit includes：

One HPI, it is electrically connected to a host computer system；

One memory interface, the duplicative Nonvolatile memory module is electrically connected to, wherein the duplicative is non- Volatile ram module has multiple entity erased cells, and each entity among the multiple entity erased cell is erased list Member has multiple entity program units；

One buffer storage, it is electrically connected to the HPI and the memory interface；And

One memory management circuit, the HPI, the memory interface and the buffer storage are electrically connected to,

The memory management circuit is write to receive one first write instruction from the host computer system by corresponding described first The data for entering instruction are kept in into the buffer storage,

When a write caching function has been closed and the data of first write instruction are kept in the buffer-stored During device, the memory management circuit more to assign one first command sequence with using a single page sequencing pattern will it is corresponding described in The data of first write instruction are write from the buffer storage to 1 among the multiple entity erased cell In an at least first instance programmed cell for one entity erased cell,

A wherein described at least first instance programmed cell is made up of multiple first memory cells and in the single page program In change pattern, form described in an at least first instance programmed cell the multiple first memory cell among each first Memory cell only stores 1 bit data.
10. memory control circuit unit according to claim 9, it is characterised in that

The memory management circuit from the host computer system more to receive a write caching out code, and write described in closing Enter cache function to respond said write cache out code.
11. memory control circuit unit according to claim 10, it is characterised in that from described in host computer system reception Before the running of write caching out code,

The memory management circuit from the host computer system more receiving one second write instruction and will corresponding described second One data of write instruction are kept in into the buffer storage,

The memory management circuit is more assigning one second command sequence will be temporarily stored into institute using a multipage sequencing pattern State and the data of second write instruction are corresponded in buffer storage write to 1 among the multiple entity erased cell An at least second instance programmed cell for two entity erased cells,

A wherein described at least second instance programmed cell is made up of multiple second memory cells and in the multipage program In change pattern, form described in an at least second instance programmed cell the multiple second memory cell among each second Memory cell stores more bit datas.
12. memory control circuit unit according to claim 9, it is characterised in that use the single page sequencing pattern The data of corresponding first write instruction are write from the buffer storage to the multiple entity erased cell Among the first instance erased cell an at least first instance programmed cell in running after,

The memory management circuit more completes information to the host computer system to reply a write-in.
13. memory control circuit unit according to claim 9, it is characterised in that first command sequence is one clear Storehouse instructs,

When said write cache function be closed and the data of first write instruction kept in it is described buffering deposit During reservoir, more to be brought down stocks according to, instruction execution is above-mentioned to use the single page sequencing pattern will to the memory management circuit The data of corresponding first write instruction are write from the buffer storage to the first instance erased cell Running in an at least first instance programmed cell.
14. memory control circuit unit according to claim 9, it is characterised in that

In a background execution pattern, the memory management circuit is more to perform a valid data union operation, to use institute State multipage sequencing pattern multiple valid data in the first instance erased cell are copied to the multiple entity and erase In multiple 3rd entity program units of one the 3rd entity erased cell among unit,

Wherein the multiple 3rd entity program unit is made up of multiple 3rd memory cells and in the multipage sequencing In pattern, each the 3rd memory among the multiple 3rd memory cell of the multiple 3rd entity program unit is formed Born of the same parents store more bit datas.
15. memory control circuit unit according to claim 9, it is characterised in that

The memory management circuit opens said write cache function with sound more to receive a write caching open command Answer said write cache open command.
16. memory control circuit unit according to claim 9, it is characterised in that the multipage sequencing pattern is one Multistage memory cell sequencing pattern or one or three rank memory cell sequencing patterns, and the single page sequencing pattern is remembered for a single-order Recall born of the same parents' sequencing pattern, the once few rank memory cell sequencing pattern of entity program pattern, a combination process pattern or one.
A kind of 17. internal storing memory, it is characterised in that including：

One connecting interface unit, is electrically connected to a host computer system；

One duplicative Nonvolatile memory module, has multiple entity erased cells, among the multiple entity erased cell Each entity erased cell there are multiple entity program units；And

One memory control circuit unit, it is electrically connected to the connecting interface unit and the duplicative Nonvolatile memory mould Block, and including a buffer storage,

The memory control circuit unit, and will corresponding described the to receive one first write instruction from the host computer system One data of one write instruction are kept in into the buffer storage,

When a write caching function has been closed and the data of first write instruction are kept in the buffer-stored During device, the memory control circuit unit more will be corresponding with one single page sequencing pattern of use to assign one first command sequence The data of first write instruction are write to the multiple entity erased cell from the buffer storage In an at least first instance programmed cell for one first instance erased cell,

A wherein described at least first instance programmed cell is made up of multiple first memory cells and in the single page program In change pattern, form described in an at least first instance programmed cell the multiple first memory cell among each first Memory cell only stores 1 bit data.
18. internal storing memory according to claim 17, it is characterised in that

The memory control circuit unit from the host computer system more to receive a write caching out code, and close institute Write caching function is stated to respond said write cache out code.
19. internal storing memory according to claim 18, it is characterised in that receive said write from the host computer system Before the running of cache out code,

The memory control circuit unit is more to from the host computer system one second write instruction of reception and by described in correspondence One data of the second write instruction are kept in into the buffer storage,

The memory control circuit unit more will be temporary with one multipage sequencing pattern of use to assign one second command sequence The data that second write instruction is corresponded in the buffer storage are write to the multiple entity erased cell An at least second instance programmed cell for one second instance erased cell,

A wherein described at least second instance programmed cell is made up of multiple second memory cells and in the multipage program In change pattern, form described in an at least second instance programmed cell the multiple second memory cell among each second Memory cell stores more bit datas.
20. internal storing memory according to claim 17, it is characterised in that will be right using the single page sequencing pattern The data of first write instruction are answered to be write from the buffer storage to the multiple entity erased cell The first instance erased cell an at least first instance programmed cell in running after,

The memory control circuit unit more completes information to the host computer system to reply a write-in.
21. internal storing memory according to claim 17, it is characterised in that first command sequence brings down stocks to refer to for one Order,

When said write cache function be closed and the data of first write instruction kept in it is described buffering deposit During reservoir, more to be brought down stocks according to, instruction execution is above-mentioned to use the single page sequencing mould to the memory control circuit unit The data of corresponding first write instruction are write to the first instance and erased list by formula from the buffer storage Running in an at least first instance programmed cell for member.
22. internal storing memory according to claim 17, it is characterised in that

In a background execution pattern, the memory control circuit unit more to perform a valid data union operation so that Multiple valid data in the first instance erased cell are copied to the multiple entity with the multipage sequencing pattern In multiple 3rd entity program units of one the 3rd entity erased cell among erased cell,

Wherein the multiple 3rd entity program unit is made up of multiple 3rd memory cells and in the multipage sequencing In pattern, each the 3rd memory among the multiple 3rd memory cell of the multiple 3rd entity program unit is formed Born of the same parents store more bit datas.
23. internal storing memory according to claim 17, it is characterised in that

The memory control circuit unit opens said write cache function more to receive a write caching open command To respond said write cache open command.
24. internal storing memory according to claim 17, it is characterised in that the multipage sequencing pattern is one multistage Memory cell sequencing pattern or one or three rank memory cell sequencing patterns, and the single page sequencing pattern is a single-order memory cell The few rank memory cell sequencing pattern of sequencing pattern, once entity program pattern, a combination process pattern or one.