CN112014726B - DSP chip testing device and method - Google Patents
DSP chip testing device and method Download PDFInfo
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a device and a method for testing a Digital Signal Processor (DSP) chip, and provides a device for realizing automatic testing of the DSP chip, aiming at the problems of low testing efficiency and complicated testing process in the existing DSP chip testing method. Based on the device, the test parameters and the test instructions can be changed at any time in one test of powering on the DSP chip. Compared with the current common DSP chip testing method, the DSP chip testing device increases the data transmission channels of the FPGA and the server on the basis of completing the basic DSP chip testing function, so that the testing work and the configuration of each parameter are more flexible. Through the server operation interface, the test parameters can be configured in real time and the test instructions can be updated online in the test process without modifying FPGA test engineering codes.
Description
Technical Field
The present invention relates to the field of DSP chip testing technologies, and in particular, to a DSP chip testing apparatus and method.
Background
With the development of domestic digital signal processing chips, in the early stage of development of DSP chips, the DSP chip functions need to be tested before the complete DSP chip uses development tools, and often, the DSP chip needs to be tested by using an FPGA-based test platform. The current commonly used DSP chip test device is: the FPGA test circuit board is designed to be connected with corresponding pins of the DSP chip aiming at the characteristics of the DSP chip, and is communicated with the DSP chip, so that the functions of the DSP chip are tested.
The specific test steps in the related art are as follows: firstly, entering a working state after the FPGA is powered on and reset, and outputting configuration information of the initial state of the DSP chip according to a preset value after the FPGA is reset. Secondly, the FPGA is in a master mode in data transmission, and DSP test instruction data are sent to the DSP chip from a data ROM stored in advance in the FPGA according to a data sending time sequence. And thirdly, the FPGA is in a slave mode in data transmission, a DSP test result is received from the IO port according to a data receiving time sequence and stored in a corresponding result RAM, a tester accesses the test result data RAM in the FPGA through a serial data channel, and the correctness of the corresponding function of the DSP chip is judged according to the DSP test result data.
The DSP chip test method under the technical framework realizes the input of the test instruction of the DSP chip and the acquisition of the test result data, but only the test cases and the test parameters stored in the FPGA data ROM can be tested each time, the replacement of the test cases and the change of the test parameters need to revise the FPGA test engineering codes, and the test result needs to be extracted from the FPGA by using a serial port communication mode, so that the test efficiency is lower and the test process is complicated.
Disclosure of Invention
The invention aims to at least solve one of the technical problems in the prior art, provides a device and a method for testing a DSP chip, and solves the technical problems that in the testing of the DSP chip, only test cases and test parameters stored in an FPGA data ROM in advance can be tested at each time, so that the testing efficiency is low and the testing process is complicated.
In a first aspect, an embodiment of the present invention provides a DSP chip test apparatus, where the test apparatus includes a server and an FPGA chip, and the server is connected to the FPGA chip in a communication manner;
the FPGA chip is used for: receiving a DSP chip test instruction and a DSP chip test parameter from a server, inputting the DSP chip test instruction and the DSP chip test parameter into a DSP chip to be tested for testing, and after obtaining a DSP chip test result of the DSP chip to be tested, sending the DSP chip test result to the server; wherein, the DSP chip test result comprises a DSP chip operation result.
As a further improvement, the server and the FPGA chip implement communication connection through PCIE transmission protocol.
As a further improvement, the FPGA chip includes a DMA control logic module, a PCIE interface logic module, a test instruction data buffer module, a DSP parameter configuration processing module, and a DSP test result RAM module, where the PCIE interface logic module, the test instruction data buffer module, the DSP parameter configuration processing module, and the DSP test result RAM module are respectively connected with the DMA control logic module;
the PCIE interface logic module is used for realizing PCIE transmission protocol communication between the FPGA chip and the server;
the test instruction data buffer module is used for storing machine codes of the test instructions of the DSP chip;
the DSP parameter configuration processing module is used for storing the test parameters of the DSP chip;
the DSP test result RAM module is used for storing the operation result of the DSP chip;
and the DMA control logic module is used for coordinating the sending, processing and storage of the data of each module according to the instruction issued by the server.
As a further improvement, the FPGA chip further comprises a DSP data decoding module, and the DSP data decoding module is respectively connected with the DMA control logic module and the DSP test result RAM module;
the DSP data decoding module is used for: and decoding the operation result of the original DSP chip so as to extract operation data and store the operation data in a corresponding DSP test result RAM module.
As a further improvement, the testing device further comprises an FPGA testing board card, and the FPGA chip is arranged on the FPGA testing board card.
As a further improvement, the testing device further comprises a DSP test board, and the DSP chip to be tested is mounted on the DSP test board.
In a second aspect, an embodiment of the present invention provides a DSP chip testing method, provided with a server, an FPGA chip, and a DSP chip to be tested, where the server and the DSP chip to be tested are respectively connected to the FPGA chip in a communication manner, and the testing method includes:
receiving a DSP chip test instruction and a DSP chip test parameter from a server, and inputting the DSP chip test instruction and the DSP chip test parameter into a DSP chip to be tested for testing;
after a DSP chip test result of a DSP chip to be tested is obtained, the DSP chip test result is sent to the server; wherein, the DSP chip test result comprises a DSP chip operation result.
As a further improvement, the server and the FPGA chip implement communication connection through PCIE transmission protocol.
As a further improvement, the method for receiving the testing instruction and the testing parameter of the DSP chip from the server specifically comprises the following steps:
and the DMA control FPGA chip is used for receiving the DSP chip test instruction and the DSP chip test parameter from the server through the PCIE transmission protocol.
As a further improvement, after the DSP chip test result of the DSP chip to be tested is obtained, the DSP chip test result is sent to the server, which specifically includes the following steps:
after the DSP chip test result of the DSP chip to be tested is obtained, decoding the operation result of the original DSP chip, and sending the decoded DSP chip test result to the server.
The beneficial effects are that: the device and the method for testing the DSP chip provide an automatic testing device for the DSP chip, aiming at the problems of low testing efficiency and complicated testing process in the current testing method for the DSP chip. Based on the device, the test parameters and the test instructions can be changed at any time in one test of powering on the DSP chip. Compared with the current common DSP chip testing method, the DSP chip testing device increases the data transmission channels of the FPGA and the server on the basis of completing the basic DSP chip testing function, so that the testing work and the configuration of each parameter are more flexible. Through the server operation interface, the test parameters can be configured in real time and the test instructions can be updated online in the test process without modifying FPGA test engineering codes. In the test process, a tester only needs to write a digital text type DSP test instruction into a test instruction data buffer module of the FPGA development board through a server, input a test starting instruction, and then start the function test of the DSP chip, and after the test is completed, the server reads the FPGA test result RAM module to acquire the digital text type DSP return operation data, so that the DS chip developer can judge the test result.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The invention is further described below with reference to the drawings and examples;
FIG. 1 is a block diagram of a DSP chip testing environment for a DSP chip testing apparatus in one embodiment.
FIG. 2 is a flow chart of a method for testing a DSP chip in one embodiment.
FIG. 3 is a flow chart of a method for testing a DSP chip in another embodiment.
FIG. 4 is a schematic diagram of a decoding process for decoding the operation result of the original DSP chip in one embodiment.
Detailed Description
Reference will now be made in detail to the present embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the accompanying drawings are used to supplement the description of the written description so that one can intuitively and intuitively understand each technical feature and overall technical scheme of the present invention, but not to limit the scope of the present invention.
In the prior art, in each DSP chip test, only test cases and test parameters stored in the FPGA data ROM in advance can be tested, so that the test efficiency is low and the test process is complex.
In order to solve the technical problems, the design concept of the invention is as follows: the block diagram of the DSP chip testing device is shown in fig. 1, and the DSP chip automatic testing realizing device mainly comprises an X86 testing server, an FPGA testing console and a DSP chip testing circuit board. The X86 test server takes the machine code file as a test instruction of the DSP chip, the instruction is stored on the test server in the form of hexadecimal files, the instruction file is DMA-stored into an instruction cache in the FPGA test console through the PCIE interface, the FPGA starts to test the test instruction in the instruction cache of the DSP chip according to the working time sequence of the DSP, after the DSP operation is completed, the FPGA test console stores test result data into the internal cache first, and then the test result is sent to the chip test server for storage in a DMA mode through the PCIE interface and is compared with the standard result of the test example.
The X86 server is responsible for loading the parameter configuration information of the DSP chip, testing instruction codes, controlling the testing flow of the FPGA console and the output of the testing operation result, and printing the testing operation result. The FPGA test console is responsible for processing the test instruction of the X86 server and sending the test instruction to the DSP chip test board for operation, collecting the operation result and sending the operation result back to the X86 test server. In the test process, a tester writes a test instruction in the form of hexadecimal data into an FPGA test board through a test server, then the test server controls the FPGA test board to write the test instruction into a DSP chip for operation, the operation result of the DSP chip is stored in a cache of the FPGA test board, and the test server is responsible for controlling the test result everywhere and analyzing.
In order to facilitate understanding of the present invention by those skilled in the art, technical terms related to the present invention are described below.
FPGA (Field Programmable Gate Array, chinese name: field programmable gate array) is a product of further development based on programmable devices such as PAL, GAL, etc. The programmable device is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), which not only solves the defect of custom circuits, but also overcomes the defect of limited gate circuits of the original programmable device.
DSP (Digital Signal Processing, chinese name: digital signal processing) is an emerging discipline that involves many disciplines and is widely used in many fields. Since the 60 s of the 20 th century, digital signal processing technology has been developed and developed rapidly with the rapid development of computer and information technologies.
DMA (Direct Memory Access ) is an important feature of all modern computers that allows hardware devices of different speeds to communicate without relying on the massive interrupt load of the CPU. Otherwise, the CPU needs to copy each piece of data from the source to the register and then write them back to the new place again.
RAM (English: random Access Memory, chinese: random Access memory), also called main memory, is an internal memory that exchanges data directly with the CPU. It can be read and written at any time (except when refreshed) and is fast, often as a temporary data storage medium for an operating system or other program in operation. RAM can write (store) or read (retrieve) information from any designated address at any time during operation. The biggest difference from ROM is the volatility of the data, i.e. the stored data will be lost upon power down. RAM is used in computer and digital systems to temporarily store programs, data, and intermediate results.
The board card is a printed circuit board, called PCB for short, and has a core insert when being manufactured, and can be inserted into a slot of a main circuit board (main board) of a computer to control the operation of hardware, such as a display, a collection card and other devices, and after a driver is installed, the corresponding hardware function can be realized.
The DSP chip testing apparatus provided by the embodiment of the present invention will be described and illustrated in detail by means of several specific embodiments.
As shown in fig. 1, in one embodiment, a DSP chip test apparatus is provided. The testing device comprises a server and an FPGA chip, and the server is in communication connection with the FPGA chip; the FPGA chip is used for: receiving a DSP chip test instruction and a DSP chip test parameter from a server, inputting the DSP chip test instruction and the DSP chip test parameter into a DSP chip to be tested for testing, and after obtaining a DSP chip test result of the DSP chip to be tested, sending the DSP chip test result to the server; the DSP chip test result comprises a DSP chip operation result.
It can be understood that the data transmission channels of the FPGA and the server added by the DSP chip testing device are loaded with related drivers, and then related testing instructions are input through the server, so that the DSP chip testing parameters, the testing instructions and the reading of the testing result files can be configured. The flexibility of the adjustment of the testing parameters, the testing instructions and the transmission of the testing results of the DSP chip is realized. Under the condition that the configuration parameters and the test instructions of the DSP chip are not required to be changed, only one test instruction is required to be input, one test of the DSP chip can be completed, and the DSP chip can be tested repeatedly in an automatic mode very conveniently, flexibly and quickly.
Specifically, the server and the FPGA chip implement communication connection through PCIE transmission protocol. The transmission channels of the DSP chip test configuration parameters, test instructions and test results are based on PCIE transmission protocol, and compared with serial port data transmission in the traditional test method, the data transmission speed is greatly improved.
Referring to fig. 1, in some embodiments, the FPGA chip includes a DMA control logic module, a PCIE interface logic module, a test instruction data buffer module, a DSP parameter configuration processing module, and a DSP test result RAM module, where the PCIE interface logic module, the test instruction data buffer module, the DSP parameter configuration processing module, and the DSP test result RAM module are respectively connected to the DMA control logic module; the PCIE interface logic module is used for realizing PCIE transmission protocol communication between the FPGA chip and the server; the test instruction data buffer module is used for storing machine codes of the test instructions of the DSP chip; the DSP parameter configuration processing module is used for storing the test parameters of the DSP chip; the DSP test result RAM module is used for storing the operation result of the DSP chip; and the DMA control logic module is used for coordinating the sending, processing and storage of the data of each module according to the instruction issued by the server.
It can be understood that the DMA control logic function in the FPGA test board card, the DMA control logic module controls the test flow of the DSP chip in the whole process, is a control center of the whole DSP chip test device, controls the time sequence among the signals and the time window for the cooperative work of the modules, and ensures the smooth operation of the whole test process.
Referring to fig. 1, in some embodiments, the FPGA chip further includes a DSP data decoding module, which is connected to the DMA control logic module and the DSP test result RAM module, respectively; the DSP data decoding module is used for: and decoding the operation result of the original DSP chip so as to extract operation data and store the operation data in a corresponding DSP test result RAM module.
It can be understood that according to the data processing characteristics of the DSP chip, the corresponding data decoding module is developed in the FPGA chip to decode the received DSP chip operation result and then extract the effective data for storage, thereby reducing the storage of redundant data and saving the data storage space.
Specifically, the testing device further comprises an FPGA testing board card, and the FPGA chip is arranged on the FPGA testing board card. The testing device also comprises a DSP testing board card, and the DSP chip to be tested is arranged on the DSP testing board card.
It can be understood that the installation of the FPGA chip and the DSP chip is facilitated by arranging the FPGA test board and the DSP test board, so that the test efficiency is accelerated.
Referring to fig. 2, the DSP chip testing method is provided with a server, an FPGA chip, and a DSP chip to be tested, where the server and the DSP chip to be tested are respectively connected with the FPGA chip in a communication manner. Specifically, the server and the FPGA chip implement communication connection through PCIE transmission protocol.
It can be understood that the transmission channels of the DSP chip test configuration parameters, test instructions and test results are based on PCIE transmission protocol, and compared with serial port data transmission in the conventional test method, the data transmission speed is greatly improved.
The DSP chip testing method specifically comprises the following steps:
step S102: and receiving the DSP chip test instruction and the DSP chip test parameter from the server, and inputting the DSP chip test instruction and the DSP chip test parameter into the DSP chip to be tested for testing.
It should be noted that, receiving the DSP chip test instruction and the DSP chip test parameter from the server specifically includes the following steps:
step S1021: and the DMA control FPGA chip is used for receiving the DSP chip test instruction and the DSP chip test parameter from the server through the PCIE transmission protocol.
Step S104: after a DSP chip test result of a DSP chip to be tested is obtained, the DSP chip test result is sent to a server; the DSP chip test result comprises a DSP chip operation result.
It should be noted that, after obtaining the DSP chip test result of the DSP chip to be tested, the DSP chip test result is sent to the server, which specifically includes the following steps:
step S1041: after the DSP chip test result of the DSP chip to be tested is obtained, decoding the operation result of the original DSP chip, and sending the decoded DSP chip test result to the server.
It can be understood that according to the data processing characteristics of the DSP chip, the corresponding data decoding module is developed in the FPGA chip to decode the received DSP chip operation result and then extract the effective data for storage, thereby reducing the storage of redundant data and saving the data storage space.
As shown in fig. 1, the operation provided by the method is mainly that the special test software and related drivers for the whole set of DSP chip test hardware platform are developed at the server side, and the control of the test parameter configuration, DSP test instruction input and DSP test result return of the DSP chip can be realized only by inputting related instructions at the server side, so that the test flow of the whole DSP chip can be controlled at the server side. The FPGA test board card mainly comprises a test hardware circuit based on an FPGA chip, and a PCIE interface logic module in the internal logic of the FPGA chip mainly plays a role in information interaction with a server; the test instruction data buffer module stores the machine code of the test instruction of the DSP chip for the system to call in real time; the DSP parameter configuration processing module stores the DSP chip test parameters to be configured and controls the configuration of the DSP chip parameters; the DMA control logic module is a top-level module of the FPGA engineering, and coordinates the sending, processing and storage of data of each module according to the instruction issued by the server; the DSP data decoding module is responsible for decoding an original DSP chip operation result, so that effective operation data are extracted and stored in the corresponding storage module; the DSP test result RAM module is responsible for storing the operation result of the DSP chip.
Referring to FIG. 3, a preferred embodiment of the DSP test method of the present invention is provided, comprising the following operational steps:
step 1: the DSP chip test preparation, before the chip test starts, software package deployment needs to be carried out on the system, and the software package deployment comprises the following steps: the FPGA configuration file is solidified and PCIE drivers are deployed, and because the DSP chip test instruction and the configuration parameters are changed without changing the FPGA test engineering codes, the developed FPGA configuration file is stored on a flash chip on an FPGA test board card and can be automatically loaded after being electrified, so that the test efficiency of the DSP chip is greatly improved, the pcie_driver file is uploaded to a test server, and the deployment of the PCIE drivers can be completed by compiling the files under the xdma and tools files.
Step 2: writing a DSP chip test instruction into a DSP instruction cache in an FPGA, firstly storing a manufactured 256-bit form test instruction machine code file into a server designated directory (under any storage directory of a server hard disk), inputting a DSP chip test instruction loading command into the server, and importing the test instruction file into the FPGA instruction cache through a PCIE channel for real-time calling in the DSP chip test process.
Step 3: writing the test parameters of the DSP chip into an FPGA parameter configuration buffer, after the test instruction file is imported into the FPGA instruction buffer, configuring various parameters in a test program according to the test requirement of the imported test instruction before testing the DSP chip, wherein the specific parameters comprise: the method comprises the steps of configuring a PLL (phase locked loop) of a DSP chip and basic parameters, configuring a base address of a DSP test instruction, and configuring the quantity of DSP test instruction data and the quantity of instructions.
Step 4: inputting a start test instruction to start testing a DSP chip, after inputting the start test instruction, the FPGA firstly calls configuration parameters in a configuration parameter module, allocates relevant pins of the DSP chip, configures the relevant parameters in the DSP chip into values required by testing, then switches to a master mode, sends the test instruction in a test instruction data buffer module to the DSP chip according to the time sequence of a wishbone bus protocol, switches to a slave mode after the instruction is sent, waits for the DSP chip to receive a DSP operation result on the wishbone bus after the operation is completed, decodes the operation result and stores the operation result in a corresponding storage module, and the decoding and storing process is shown in figure 4.
Step 5: acquiring a DSP chip test result, wherein the acquisition of the DSP test result is completed in two steps: firstly, writing result cache data received by the FPGA into a server cache: after the DSP test is finished, the content in the FPGA result cache can be sent to the server cache by inputting a read result command in a command window; then, the server cache data is generated into a result file: after the data in the FPGA result cache is sent to the server, a command for generating a result file is input in a command window, and then a DSP operation result file can be generated.
Step 6: and after the test is completed, comparing the output operation result file with a correct value to judge the error alignment and related performance of the DSP chip operation. So far, one-time testing of the DSP chip is completed.
The key module and the technical description related to the embodiment of the invention are as follows:
1. PCIE channel driving program and control instruction between server and FPGA test board card
The PCIE protocol-based channel driver and control instructions are key parts for realizing automatic test, and the driver in service and the PCIE interface logic control module in the FPGA jointly build a channel for real-time information interaction of the whole DSP chip testing device.
2. DMA control logic module
In the implementation of the method, a DMA control logic module plays a crucial role, and the module controls the transmission interaction of test data between a server and a DSP chip and the access of test instructions and related data issued by the execution server in an FPGA cache.
3. Decoding and storing module for DSP operation result
The design of the DSP chip generally supports data operation with the width of 64 bits, 32 bits, 16 bits and 8 bits, and the DSP operation result decoding module decodes the data according to the DSP chip test instruction issued by the server and the related parameter information of the operation result returned by the DSP chip, only stores effective data into the storage RAM, avoids the storage of invalid data, effectively improves the utilization rate of the storage space, and further enables the system to support the DSP chip test instruction with larger operation amount.
In summary, the device and the method for testing the DSP chip provided by the embodiment of the invention have the following advantages:
1. the DSP chip is automatically tested and the test parameters are configured in real time, the test cases and the test parameters are supported to be changed in real time, and the DSP chip can work in different working modes and working frequencies by configuring the test parameters on the premise of not changing the test, so that the flexibility of testing the DSP chip is greatly enhanced.
2. The development and use of the functional module enable a tester to realize man-machine interaction in the DSP test process through a computer screen, thereby greatly improving the working environment of the tester.
3. The DMA control logic module is used for controlling the test flow of the DSP chip in the whole course, is a control center of the whole DSP chip test device, controls the time sequence among the signals and the time window of the cooperative work of the modules, and ensures the smooth operation of the test process.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
Claims (8)
1. The DSP chip testing device is characterized by comprising a server and an FPGA chip, wherein the server is in communication connection with the FPGA chip;
the FPGA chip is used for: receiving a DSP chip test instruction and a DSP chip test parameter from a server, inputting the DSP chip test instruction and the DSP chip test parameter into a DSP chip to be tested for testing, and after obtaining a DSP chip test result of the DSP chip to be tested, sending the DSP chip test result to the server; wherein, the DSP chip test result comprises a DSP chip operation result;
the FPGA chip comprises a DMA control logic module, a PCIE interface logic module, a test instruction data cache module, a DSP parameter configuration processing module and a DSP test result RAM module, wherein the PCIE interface logic module, the test instruction data cache module, the DSP parameter configuration processing module and the DSP test result RAM module are respectively connected with the DMA control logic module;
the PCIE interface logic module is used for realizing PCIE transmission protocol communication between the FPGA chip and the server;
the test instruction data buffer module is used for storing machine codes of the test instructions of the DSP chip;
the DSP parameter configuration processing module is used for storing the test parameters of the DSP chip;
the DSP test result RAM module is used for storing the operation result of the DSP chip;
the DMA control logic module is used for coordinating the sending, processing and storage of data of each module according to the instruction issued by the server;
through the server operation interface, the test parameters can be configured in real time and the test instructions can be updated online in the test process without modifying FPGA test engineering codes.
2. The DSP chip testing apparatus of claim 1, wherein the server and the FPGA chip are communicatively coupled via PCIE transport protocol.
3. The DSP chip testing apparatus according to claim 1, wherein the FPGA chip further comprises a DSP data decoding module, the DSP data decoding module being connected to the DMA control logic module and the DSP test result RAM module, respectively;
the DSP data decoding module is used for: and decoding the operation result of the original DSP chip so as to extract operation data and store the operation data in a corresponding DSP test result RAM module.
4. The DSP chip testing apparatus of claim 1, wherein the testing apparatus further comprises an FPGA test board on which the FPGA chip is mounted.
5. The DSP chip testing apparatus according to claim 1, wherein the testing apparatus further comprises a DSP test board on which the DSP chip to be tested is mounted.
6. The DSP chip testing method is characterized by comprising a server, an FPGA chip and a DSP chip to be tested, wherein the server and the DSP chip to be tested are respectively in communication connection with the FPGA chip, and the testing method comprises the following steps:
receiving a DSP chip test instruction and a DSP chip test parameter from a server, and inputting the DSP chip test instruction and the DSP chip test parameter into a DSP chip to be tested for testing;
after a DSP chip test result of a DSP chip to be tested is obtained, the DSP chip test result is sent to the server; wherein, the DSP chip test result comprises a DSP chip operation result;
the method for receiving the DSP chip test instruction and the DSP chip test parameter from the server specifically comprises the following steps:
the method comprises the steps that a DMA control FPGA chip is used for receiving a DSP chip test instruction and a DSP chip test parameter from a server through a PCIE transmission protocol;
through the server operation interface, the test parameters can be configured in real time and the test instructions can be updated online in the test process without modifying FPGA test engineering codes.
7. The method of claim 6, wherein the server and the FPGA chip are communicatively coupled via PCIE transport protocol.
8. The method for testing a DSP chip according to claim 6, wherein after obtaining the DSP chip test result of the DSP chip to be tested, the DSP chip test result is sent to the server, and specifically includes the following steps:
after the DSP chip test result of the DSP chip to be tested is obtained, decoding the operation result of the original DSP chip, and sending the decoded DSP chip test result to the server.
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| CN112804443A (en) * | 2020-12-29 | 2021-05-14 | 中国科学院半导体研究所 | Image processing method and high-speed intelligent camera applying same |
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