CN111985174A - RT latch and latch method - Google Patents
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- CN111985174A CN111985174A CN202010914490.1A CN202010914490A CN111985174A CN 111985174 A CN111985174 A CN 111985174A CN 202010914490 A CN202010914490 A CN 202010914490A CN 111985174 A CN111985174 A CN 111985174A
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Abstract
The invention relates to an RT latch and a latching method, wherein the RT latch comprises: the NAND gate circuit comprises a NOT gate, a three-input NAND gate, an AND gate, a first SR latch and a second SR latch. The output end of the three-input NAND gate is connected with the other input end of the first SR latch, the other input end of the second SR latch and the data path of the latches, so that the RT latches send response signals to the previous RT latch and send request signals to the next RT latch at the same time, and the high-speed parallel operation of the RT latches is guaranteed. Meanwhile, the invention only uses two SR latches, one NOT gate, one three-input NAND gate and one AND gate, only uses 7 gate units, can realize signal latch by 30 transistors, and has simple circuit and low production cost.
Description
Technical Field
The invention relates to the technical field of circuit design, in particular to an RT latch and a latch method.
Background
With the introduction of many-core architectures, in order to solve the problem of multiple clock domains in the system and the problem of reusability of IP core module updates, researchers have introduced Globally Asynchronous Locally Synchronous (GALS) systems. The asynchronous mode can well solve the problem of clock synchronization among single modules. Meanwhile, the sampling period can be adjusted among the modules according to the clock frequency of the modules, and the power consumption of the system can be greatly reduced. The asynchronous controller mainly realizes the functions of communication and coordination circuits through a handshake protocol. The method is generally applied to a common data path structure-micro-pipeline structure in an SoC network.
In the prior art, considering that a handshake protocol is required for communication, a latch circuit designed based on a C unit is mainly used, and the latch circuit has many transistors, generally large circuit scale, high cost, complex circuit design and low energy efficiency. The other is a circuit designed based on delay matching, such as a click controller used in Loihi (first-generation neurostimulation computing chip released by Intel) of Intel, but this method needs to consider delay matching between a control path and a data path, and a trigger is used to ensure normal operation of the circuit, so that the circuit design is complex, and circuit overhead and power consumption need to be further optimized.
Disclosure of Invention
The invention aims to provide a latch and a latch method so as to reduce the production cost and improve the running speed.
In order to achieve the purpose, the invention provides the following scheme:
an RT latch comprising: the NAND gate, the three-input NAND gate, the AND gate, the first SR latch and the second SR latch;
the input end of the NOT gate is connected with one output end of a second SR latch in the next stage of the RT latch, and the output end of the NOT gate is connected with the first input end of the three-input NAND gate and one input end of the first SR latch;
the second input end of the three-input NAND gate is connected with the output end of the AND gate, and the third input end of the three-input NAND gate is connected with one input end of the second SR latch and one output end of the first SR latch in the previous stage of the RT latch; the output end of the three-input NAND gate is connected with the other input end of the first SR latch, the other input end of the second SR latch and the data path of the RT latch;
one output end of the first SR latch is connected with a third input end of a three-input NAND gate in the next stage of the RT latch, and the other output end of the first SR latch is connected with one input end of the AND gate;
one output end of the second SR latch is connected with the input end of a NOT gate in the RT latch at the upper stage, and the other output end of the second SR latch is connected with the other input end of the AND gate.
Optionally, the first SR latch includes a first nand gate and a second nand gate, and the second SR latch includes a third nand gate and a fourth nand gate;
the input end of the NOT gate is connected with the output end of a third NAND gate in the RT latch of the next stage; the output end of the NOT gate is connected with one input end of the second NAND gate;
the third input end of the three-input NAND gate is connected with one input end of the fourth NAND gate and the output end of the first NAND gate in the RT latch at the previous stage; the output end of the three-input NAND gate is connected with one input end of the first NAND gate and one input end of the third NAND gate;
the other input end of the first NAND gate is connected with the output end of the second NAND gate and one input end of the AND gate; the output end of the first NAND gate is connected with the other input end of the second NAND gate and the third input end of the three-input NAND gate in the next stage of the RT latch;
the other input end of the third NAND gate is connected with the output end of the fourth NAND gate and the other input end of the AND gate; and the output end of the third NAND gate is connected with the other input end of the fourth NAND gate and the input end of the NOT gate in the RT latch of the previous stage.
Optionally, the first nand gate, the second nand gate, the third nand gate and the fourth nand gate are all two-input nand gates.
Optionally, the RT latches communicate using a 4-phase bundled data protocol.
A latch method is applied to the latch and comprises the following steps:
acquiring a request signal sent by a previous stage RT latch;
sending a latch signal according to the request signal sent by the upper stage RT latch, and latching data;
after data latching, the former stage RT latch sends out answer signal, and at the same time, the latter stage RT latch sends out request signal.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses an RT latch and a latching method, wherein the RT latch comprises a NOT gate, a three-input NAND gate, an AND gate, a first SR latch and a second SR latch; the input end of the NOT gate is connected with one output end of a second SR latch in the next stage of the RT latch, and the output end of the NOT gate is connected with the first input end of the three-input NAND gate and one input end of the first SR latch; the second input end of the three-input NAND gate is connected with the output end of the AND gate, and the third input end of the three-input NAND gate is connected with one input end of the second SR latch and one output end of the first SR latch in the previous stage of the RT latch; the output end of the three-input NAND gate is connected with the other input end of the first SR latch, the other input end of the second SR latch and the data path of the latches; one output end of the first SR latch is connected with a third input end of a three-input NAND gate in the next stage of the RT latch, and the other output end of the first SR latch is connected with one input end of the AND gate; one output end of the second SR latch is connected with the input end of a NOT gate in the RT latch at the upper stage, and the other output end of the second SR latch is connected with the other input end of the AND gate.
In the invention, the output end of the three-input NAND gate is connected with the other input end of the first SR latch, the other input end of the second SR latch and the data path of the latches, so that the RT latches send response signals to the previous RT latch and send request signals to the next RT latch at the same time, and the high-speed parallel operation of the RT latches is ensured.
The invention only uses two SR latches, one NOT gate, one three-input NAND gate and one AND gate, only uses 7 gate units, can realize signal latch by 30 transistors, and has simple circuit and low production cost.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a circuit diagram of an RT latch according to an embodiment of the present invention;
FIG. 2 is a simplified diagram of an RT latch according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating an application example of an RT latch according to an embodiment of the present invention;
FIG. 4 is a diagram of an STG of handshake protocol signals in a conventional C-cell control latch according to an embodiment of the present invention;
FIG. 5 is a diagram of an STG of conventional RT control latch handshake protocol signals provided by an embodiment of the present invention;
fig. 6 is a diagram of an STG of an RT control latch according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a latch and a latch method so as to reduce the production cost and improve the running speed.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
The internal circuit of the latch is designed based on Relative Timing (RT). Fig. 1 is a circuit diagram of an RT latch according to an embodiment of the present invention, and as shown in fig. 1, the circuit includes: the NAND gate circuit comprises a NOT gate, a three-input NAND gate, an AND gate, a first SR latch and a second SR latch. The input end of the NOT gate is connected with one output end of the second SR latch in the next stage RT latch, and the output end of the NOT gate is connected with the first input end of the three-input NAND gate and one input end of the first SR latch. The second input end of the three-input NAND gate is connected with the output end of the AND gate, and the third input end of the three-input NAND gate is connected with one input end of the second SR latch and one output end of the first SR latch in the upper stage RT latch. The output end of the three-input NAND gate is connected with the other input end of the first SR latch, the other input end of the second SR latch and the data path of the RT latch. One output end of the first SR latch is connected with the third input end of the three-input NAND gate in the next stage RT latch, and the other output end of the first SR latch is connected with one input end of the AND gate. One output end of the second SR latch is connected with the input end of the NOT gate in the first-stage RT latch, and the other output end of the second SR latch is connected with the other input end of the AND gate.
In this embodiment, the first SR latch includes a first nand gate and a second nand gate, and the second SR latch includes a third nand gate and a fourth nand gate. The first NAND gate, the second NAND gate, the third NAND gate and the fourth NAND gate are all two-input NAND gates. The input end of the NOT gate is connected with the output end of a third NAND gate in the next stage of RT latch, and the output end of the NOT gate is connected with one input end of a second NAND gate. The third input end of the three-input NAND gate is connected with one input end of the fourth NAND gate and the output end of the first NAND gate in the previous stage RT latch. The output end of the three-input NAND gate is connected with one input end of the first NAND gate and one input end of the third NAND gate. The other input end of the first NAND gate is connected with the output end of the second NAND gate and one input end of the AND gate. The output end of the first NAND gate is connected with the other input end of the second NAND gate and the third input end of the three-input NAND gate in the next stage of RT latch. The other input end of the third NAND gate is connected with the output end of the fourth NAND gate and the other input end of the AND gate. The output end of the third NAND gate is connected with the other input end of the fourth NAND gate and the input end of the NOT gate in the previous stage RT latch. Two SR latches in the latch are used for transmitting the handshake signals, and the AND gate, the NOT gate and the three-input NAND gate are used for realizing correct circuit logic, which is equivalent to adding constraint to the triggering of the handshake signals.
Fig. 2 is a simplified diagram of the RT latch according to the embodiment of the present invention, as shown in fig. 2, Rin is an input RT latch request signal of the RT latch circuit of the previous stage, Ain is a response signal of the RT latch responding to the RT latch circuit of the previous stage, Rout is an output request signal of the RT latch to the RT latch circuit of the next stage, and Aout is a response signal of the RT latch responding to the RT latch circuit of the next stage. Lt represents a control signal generated by the RT latch for controlling the transmission of signals in the data path.
The RT latch provided by this embodiment specifically works as follows:
assuming that the initial states of all signals (Rin, Ain, Rout, Aout) are (0000), the initial states of the internal signals (a, b, X1, X2, and X3) are all 1. When Lt is 0, the control signal is active and the initial control signal is inactive, X1 indicates the initial state of 1. When the data of the previous stage RT latch is ready, Rin of the RT control latch is pulled high, and after a 3 input nand gate, the X1 signal is pulled low, causing Ain signal to be pulled high, i.e. a response signal is generated to the previous stage RT latch, and the left hand handshake is completed. Meanwhile, the Rout signal is also pulled high, because the Rout signal is a request signal output to the next stage of RT latch, the data is ready in this stage, and then a handshake cycle is completed as long as the Lt signal is set to be invalid as long as the Aout signal returned by the next stage of RT latch is set to be 1.
Since the input Rin signal is passed from X1 to the output of two identical 2-input nand gates at the same time, the RT latch will simultaneously issue acknowledge signal Ain to the previous RT latch and request signal to the next RT latch. That is, the RT latch, while latching data (Lt is asserted), notifies the next RT latch to be ready to accept data (Rout pulled high to 1), instead of issuing the Rout request signal after waiting for the circuit of that stage to latch good data (Ain pulled high to 1). This design enables the RT latches to operate in parallel at high speed.
The RT latches provided in this embodiment communicate using a 4-phase bundled data protocol. Fig. 3 is a diagram illustrating an application example of the RT latch according to the embodiment of the present invention, as shown in fig. 3. The working principle (data latch method) of the RT latch is as follows when in application:
with the middle stage of the RT latch as a reference, when the data of the previous stage of the RT latch is ready, the previous stage of the RT latch will send a request req to the current RT latch. The RT latch then issues a latch signal Lt to latch the data into the current RT latch. After the data is locked, the current RT latch issues an acknowledge signal ack again, and at the same time, the current RT latch issues a request req to the next stage to inform that the data of the current stage is ready and that the next stage RT latch can collect. After the next stage RT latch collects the data, it will send an acknowledge signal ack to inform the current stage.
The following describes the basic principles of RT latch circuits, conventional RT latches:
the operation of the RT latch circuit obeys a certain Relative Timing relationship, i.e. signals are prioritized with respect to their occurrence. Assuming that event a has priority before event B, event B must occur after event a occurs. This event trigger mechanism, similar to the clock in synchronous circuits, triggers a register at the arrival of the clock, simply replacing the clock trigger with an event trigger, and is referred to as relative timing. The timing constraint is guaranteed by the RT circuit and is a constraint relation existing in the RT circuit.
An STG diagram (signal Transition Graph) is used to describe the concurrency and sequence of asynchronous signals, i.e. the relative timing relationship between signals. Fig. 4 is an STG diagram of handshake protocol signals in a conventional C-cell control latch according to an embodiment of the present invention, where a signal Rin + represents a transition of Rin from 0 to 1, and Rin-represents a transition of Rin from 1 to 0. The arrow points from Rin + to Ain +, indicating that Rin + must occur before Ain + occurs. As can be seen from the STG graph, to ensure that the next stage receives data (Aout +), the previous stage new data can arrive (Rin +), the conventional C-cell latch uses the relationship chain constraint of Aout + to Ain-. When the constraint of the stage is cancelled, two pairs of handshake signals (Rin, Ain) and (Rout, Aout) in the STG diagram in fig. 5 are obtained and are completely independent of each other, so that the parallelism and the operation speed of the system operation can be greatly improved. However, there is a problem that before the (Rout, Aout) pair handshake is completed, the next group (RIn, Ain) may occur again, that is, new data comes in case the current data has not been received, which may cause data transmission errors.
The RT latch provided by this embodiment avoids this problem because the circuit logic of the RT latch circuit itself can guarantee this timing assumption: aout + precedes Ain-.
The present invention separates the timing assumptions (signaling logic) into two types, one for ensuring that data moves correctly between stages, as in the traditional asynchronous design in the bundled data protocol. The other is used inside the latch. For example, for the timing sequence in FIG. 1, Rout + must be earlier than X1+, b-, and Rin-, while Ain + must be earlier than X1+, a-, and Aout-. The Aout + to Ain-relationship chain constraint is warranted. From the circuit point of view, 8 gates are passed from Rin + to Aout + in sequence, and 13 gates are passed from Rin + to Ain + and Aout + occurs before Ain + in terms of the number of signal propagation gates. Fig. 6 is a diagram of an STG of an RT control latch according to an embodiment of the present invention.
Since the time delay of each gate electrode has difference, the time sequence test is carried out to measure the delay time of each gate electrode circuit. The results show that the signal transmission time T (Rin + to Aout +) is always greater than T1(Rin + to Ain-), proving that the RT latch circuit provided by the present embodiment can operate normally without adding additional delay units or other circuit logic.
Meanwhile, a MonteCarlo method is adopted, research is carried out under the process angle (tt, ff, ss, sf, fs), Vdd is gradually reduced from 1.2V, and the performance of each circuit is tested. The minimum operating voltage at which each latch controller circuit can maintain correct logic functions can be obtained through experiments, and table 1 shows the minimum operating voltage satisfying each process corner condition. As can be seen from table 1, the supply voltage of other circuits such as the long hold control latch circuit can only be as low as 0.7V at the lowest, and the supply voltage of the semi-decoupled control latch circuit can only be above 0.75V. The RT latch controller circuit in the present application can work normally in all process corners as low as Vdd ═ 0.275V, and has good power supply voltage robustness.
TABLE 1
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
(1) the RT latch provided by the invention introduces a time sequence hypothesis and enables the control signals to work in parallel. Meanwhile, the sequence of signal generation is ensured by using a timing hypothesis generated by the gate-level delay attribute (the number of gates and different delays on different gates) of the circuit, rather than adding extra circuit logic design, so that the hardware cost can be reduced better.
(2) The RT latch in the invention can be realized in a standard library without being designed based on the traditional C unit, and is better suitable for the traditional EDA design flow.
(3) Compared with a traditional control latch circuit (27-36 transistors) based on a C unit design and a click circuit (84 transistors), the RT latch only uses 7 gates (30 transistors), the number of the transistors is reduced by about 2 times on average, the circuit is simpler, and the production cost is lower.
(4) The RT latch circuit can normally work in all process corners (tt, ss, ff, sf and fs) based on the working voltage of 0.275V, normally processes data and has good power supply voltage robustness.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to assist in understanding the core concepts of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (5)
1. An RT latch, comprising: the NAND gate, the three-input NAND gate, the AND gate, the first SR latch and the second SR latch;
the input end of the NOT gate is connected with one output end of a second SR latch in the next stage of the RT latch, and the output end of the NOT gate is connected with the first input end of the three-input NAND gate and one input end of the first SR latch;
the second input end of the three-input NAND gate is connected with the output end of the AND gate, and the third input end of the three-input NAND gate is connected with one input end of the second SR latch and one output end of the first SR latch in the previous stage of the RT latch; the output end of the three-input NAND gate is connected with the other input end of the first SR latch, the other input end of the second SR latch and the data path of the RT latch;
one output end of the first SR latch is connected with a third input end of a three-input NAND gate in the next stage of the RT latch, and the other output end of the first SR latch is connected with one input end of the AND gate;
one output end of the second SR latch is connected with the input end of a NOT gate in the RT latch at the upper stage, and the other output end of the second SR latch is connected with the other input end of the AND gate.
2. The RT latch of claim 1, wherein the first SR latch comprises a first nand gate and a second nand gate, the second SR latch comprising a third nand gate and a fourth nand gate;
the input end of the NOT gate is connected with the output end of a third NAND gate in the RT latch of the next stage; the output end of the NOT gate is connected with one input end of the second NAND gate;
the third input end of the three-input NAND gate is connected with one input end of the fourth NAND gate and the output end of the first NAND gate in the RT latch at the previous stage; the output end of the three-input NAND gate is connected with one input end of the first NAND gate and one input end of the third NAND gate;
the other input end of the first NAND gate is connected with the output end of the second NAND gate and one input end of the AND gate; the output end of the first NAND gate is connected with the other input end of the second NAND gate and the third input end of the three-input NAND gate in the next stage of the RT latch;
the other input end of the third NAND gate is connected with the output end of the fourth NAND gate and the other input end of the AND gate; and the output end of the third NAND gate is connected with the other input end of the fourth NAND gate and the input end of the NOT gate in the RT latch of the previous stage.
3. The RT latch of claim 2, wherein the first nand gate, the second nand gate, the third nand gate, and the fourth nand gate are two-input nand gates.
4. The RT latch of claim 1, wherein the RT latch communicates using a 4-phase bundled data protocol.
5. A method of latching, when applied to the latch of any one of claims 1 to 4, comprising:
acquiring a request signal sent by a previous stage RT latch;
sending a latch signal according to the request signal sent by the upper stage RT latch, and latching data;
after data latching, the former stage RT latch sends out answer signal, and at the same time, the latter stage RT latch sends out request signal.
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| CN113489482A (en) * | 2021-07-06 | 2021-10-08 | 北京中科芯蕊科技有限公司 | Asynchronous micro-pipeline data flow controller based on Mousetrap |
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