CN111949108B

CN111949108B - Power management device, method and equipment

Info

Publication number: CN111949108B
Application number: CN202010899293.7A
Authority: CN
Inventors: 刘君
Original assignee: Zeku Technology Beijing Corp Ltd
Current assignee: Zeku Technology Beijing Corp Ltd
Priority date: 2020-08-31
Filing date: 2020-08-31
Publication date: 2022-07-15
Anticipated expiration: 2040-08-31
Also published as: CN111949108A

Abstract

The embodiment of the application discloses a power management device, a method and equipment, wherein the power management device comprises: a first storage unit; a second storage unit configured to receive and store first information from outside the power management apparatus, the first information including at least one of: first configuration information of the first storage unit, a first starting time sequence of the power management device and a first control time sequence of the power management device; the processing unit is used for reading the first information in the second storage unit and writing the first information into the first storage unit; and the operation unit is used for reading the first information in the first storage unit so as to control the self start and/or operation.

Description

Power management device, method and equipment

Technical Field

The embodiments of the present application relate to, but not limited to, electronic technologies, and in particular, to a power management apparatus, method, and device.

Background

As the functions that can be realized by the electronic device system are more and more, higher requirements are also put forward on the power management device, and how to design the power management device to meet various requirements on the power management device is a problem to be solved in the art.

Disclosure of Invention

The embodiment of the application provides a power management device, method and equipment.

In a first aspect, a power management device is provided, including:

a first storage unit;

a second storage unit configured to receive and store first information from outside the power management apparatus, the first information including at least one of: first configuration information of the first storage unit, a first starting time sequence of the power management device and a first control time sequence of the power management device;

the processing unit is used for reading the first information in the second storage unit and writing the first information into the first storage unit;

and the operation unit is used for reading the first information in the first storage unit so as to control the self starting and/or operation.

In a second aspect, a power management method is provided, including:

the second storage unit receives and stores first information from outside the power management apparatus, the first information including at least one of: first configuration information of the first storage unit, a first starting time sequence of the power management device and a first control time sequence of the power management device;

the processing unit reads the first information in the second storage unit and writes the first information into the first storage unit;

and the running unit reads the first information in the first storage unit to control the self starting and/or running.

In a third aspect, a power management device is provided, which includes the above power management apparatus.

In an embodiment of the present application, a power management apparatus includes: a first storage unit; a second storage unit for receiving and storing first information from outside the power management apparatus, the first information including at least one of: the method comprises the steps that first configuration information of a first storage unit, a first starting time sequence of a power management device and a first control time sequence of the power management device are obtained; the processing unit is used for reading the first information in the second storage unit and writing the first information into the first storage unit; and the operation unit is used for reading the first information in the first storage unit so as to control the self starting and/or operation. In this way, since the first information that the operation unit can operate is transmitted through the outside of the power management device, the register configuration and/or the start timing and/or the control timing of the power management device after leaving the factory can be optimized, so that the flexibility of the power management device during operation is improved, and various requirements on the power device are met.

Drawings

Fig. 1 is a schematic diagram illustrating a power management apparatus provided in the related art;

fig. 2 is a schematic diagram illustrating an architecture of a power management device according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram illustrating an architecture of another power management apparatus according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of another power management apparatus according to an embodiment of the present application;

fig. 5 is a schematic diagram illustrating an architecture of another power management apparatus according to an embodiment of the present application;

fig. 6 is a schematic diagram illustrating an operation process of a power management apparatus according to an embodiment of the present application;

fig. 7 is a schematic flowchart of a power management method according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a power management device according to an embodiment of the present application.

Detailed Description

The technical solution of the present application will be specifically described below by way of examples with reference to the accompanying drawings. These several specific embodiments may be combined with each other below, and details of the same or similar concepts or processes may not be repeated in some embodiments.

It should be noted that: in the present examples, "first", "second", etc. are used for distinguishing similar objects and are not necessarily used for describing a particular order or sequence.

The technical means described in the embodiments of the present application may be arbitrarily combined without conflict.

It should be noted that the Power Management device in any embodiment of the present application may be a Power Management Integrated Circuits (PMIC), or may be a combination of partial hardware in the Power Management chip.

In a certain device or various large-scale electrical systems, a power management device dedicated to managing power of the device or the electrical system is indispensable, but is also increasingly complex. The requirements of each device or each system for the power management device are increasing, and this includes the integration of digital and analog parts, low and high frequency parts, flexible and changeable register setting and internal and external timing adjustment, etc. for the power management device. All of these requirements add complexity to the power management device and also present difficulties in the design of the power management device.

Through various registers, state machines and task sequences, each part or module of the power management device can be configured, and meanwhile, the external output, the time sequence and the like of the power management device can be set. Based on this principle, the current power management apparatus adds various registers to each module, and is equipped with a One Time Programmable (OTP) Memory or a Non-Volatile Memory (NVM) with different small capacities for post optimization.

A state machine is a type of digital logic circuit, which is a mathematical model that represents a finite number of states and the behavior of transitions and actions between these states. The registers, state machines, and task sequences in the embodiments of the present application are configurable. Each part or module of the power management apparatus may be an operation unit in the embodiment of the present application. Registers, state machines and task sequences may configure one of the execution units in the embodiments of the present application. In some embodiments, different execution units may be configured according to at least one of a register, a state machine, and a task sequence.

In some embodiments, the power management apparatus may include one or at least two operation units, and one or at least two operation units may correspond to one register, so that the one or at least two operation units corresponding to the register may perform self-starting and/or operation according to the control information stored in the register.

In some embodiments, the execution unit corresponding to a register is immutable. In other embodiments, the execution units corresponding to a register may be changed, for example, information stored at a first time may be read by a first execution unit, and information stored at a second time may be read by a second execution unit.

Fig. 1 is a schematic diagram of an architecture of a power management device provided in the related art, and as shown in fig. 1, a power management device 10 includes an access port 11, an internal bus 12, an OTP/NVM memory 13, an internal processor 14, and an internal register 15.

The device manufacturer may rewrite the OTP/NVM memory 13 through some hardware interface, through the access port 11 and the internal bus 12, and the internal processor 14 may pick up the contents of the OTP/NVM to configure the internal analog and digital circuits through the internal register 15. Internal registers may be understood the same as the registers described above.

Based on the architecture of the power management device shown in fig. 1, there are applications of backend and product. One way is to match the various requirements of product pre-research or mass production by the manufacturer's method of modifying the contents of the OTP/NVM memory 13. This way of modifying the contents of the OTP/NVM memory 13 is written once by the manufacturer of the power management device 10, and the backend development or product developer makes a request and waits for the production output of the manufacturer, which often takes a minimum of three to four months. Another way is that the back-end developer needs to equip the OTP/NVM write device as the same as the manufacturer and equip the device connector of the power management device 10 in terms of hardware design to facilitate the replacement of a new device newly written to OTP/NVM, in this case, any small modification needs to replace a new device, which is very unsuitable for the development and differentiation requirements of the power management device 10 that needs to be frequently rewritten, and meanwhile, the hardware cost is high and the reliability is low.

Fig. 2 is a schematic diagram of an architecture of a power management device according to an embodiment of the present application, and as shown in fig. 2, the power management device 20 includes: a first storage unit 21, a second storage unit 22, a processing unit 23 and an execution unit 24.

The first storage unit 21 may be an internal register 15 in the related art. In some embodiments, the first storage unit 21 may include a register unit, which may include one or at least two registers, and the configuration information corresponding to different registers may be the same or different.

In some embodiments, the second storage unit 22 may be a random access memory RAM, which may include non-volatile memory or volatile memory. When the RAM is a nonvolatile memory, it is not necessary to write information (for example, first information and/or second information described below) relating to the startup and/or operation of the power management apparatus 20 into the RAM each time the power management apparatus 20 is started up. When the RAM is a volatile memory, it is necessary to write information related to the startup and/or operation of the power management device 20 into the RAM each time the power management device 20 is started up, so that the power management device 20 can control the startup and/or operation based on the information related to the startup and/or operation. In other embodiments, the second storage unit 22 may include at least two memories, and at least one random access memory RAM may be present in the at least two memories.

And a second storage unit 22 for receiving and storing the first information from outside the power management apparatus 20. For example, in the case where the power management apparatus 20 is applied to a power management device, the second storage unit 22 may receive first information of a control unit external to the power management apparatus 20. For another example, in the case where the power management device 20 is produced and sold separately, the second storage unit 22 may receive first information of a control unit capable of inputting data to the second storage unit in a manufacturer. Wherein, regardless of the embodiment, the control unit is external to the power management device 20. The first information may include at least one of: configuration information of the first storage unit 21, a first start-up timing of the power management apparatus 20, and a first control timing of the power management apparatus 20.

In some embodiments, the first information sent by the control unit to the second storage unit 22 may be sent after the control unit is started, and the control unit is started after the power management device 20 is started because the control unit is started depending on the start of the power management device 20. After the control unit is started, the first information may be sent to the second storage unit 22 as the user's needs change. For example, when the control unit starts to start, first information may be sent to the second storage unit 22, and the first information may be first information stored in advance, or may be first information when the user has powered off last time.

In some embodiments, when at least one of the original configuration information of the first storage unit 21, the original start-up timing sequence, and the original control timing sequence exists in the power management apparatus 20, the first information may be a supplement and/or modification of the configuration information of the original first storage unit 21 of the power management apparatus 20, and/or the first information may be a supplement and/or modification of the original start-up timing sequence of the power management apparatus 20, and/or the first information may be a supplement and/or modification of the original control timing sequence of the power management apparatus 20.

The configuration information of the first storage unit 21 may include: the configuration information of each register in at least one register included in the first storage unit 21 includes one of the following information or a combination of at least any two of the following information: register name, register address, default values, field configuration, access rights, and register interface information.

The first start-up timing of the power management device 20 may be a start-up timing of each module in the power management device 20, and the first control timing of the power management device 20 may be a control timing of each module in the power management device 20. Each module in the power management device 20 may be each execution unit 24 in the power management device 20, one module may correspond to one or at least two execution units 24, or one execution unit 24 may correspond to one or more modules.

In some embodiments, the execution unit 24 may be one or at least two hardware modules of the power management unit, other than the first storage unit, the second storage unit, and the processing unit, which may be hardware modules having processing functions. For example, the operation unit 24 may include at least one of a non-isolated conversion device, an offline/isolated conversion device, a linear power supply, power management, a synchronous rectification control device, a voltage reduction device, a voltage boost device, a linear control device, an electronic switching device, and the like. In other embodiments, the operation unit may be specifically divided according to implementation functions, for example, the operation unit 24 may be a unit for controlling power supply to the display device, or may be a unit for supplying power to a radio frequency device, or the like.

The processing unit 23 may be the internal processor 14 in the related art. One or at least two processing units 23 may be included in the power management apparatus 20, and one processing unit 23 may correspond to one or at least two registers, that is, one processing unit 23 may read data in the one or at least two registers or write data to the one or at least two registers.

And a processing unit 23, configured to read the first information in the second storage unit 22 and write the first information in the first storage unit 21.

And the operation unit 24 is used for reading the first information in the first storage unit 21 so as to control the self starting and/or operation.

In some embodiments, when reading the first information, the processing unit 23 may read a part or a small amount of the first information at a time and store the part of the first information in the relevant one or more registers, so that the execution unit 24 corresponding to the one or more registers reads and controls the operation of the execution unit 24.

The operation unit 24 in the embodiment of the present application may also be referred to as a functional unit to implement different power supply functions.

Fig. 3 is a schematic structural diagram of another power management apparatus according to an embodiment of the present application, and as shown in fig. 3, the power management apparatus 20 includes: a first storage unit 21, a second storage unit 22, a processing unit 23 and an execution unit 24.

In some embodiments, the second storage unit 22, further stores second information; the second information comprises initial starting information, or the second information comprises the initial starting information and initial configuration information; the initial startup information includes information necessary for startup of the power management device 20, and the initial configuration information includes at least one of: second configuration information of the first storage unit 21, a second start-up timing of the power management apparatus 20, and a second control timing of the power management apparatus 20.

The second configuration information and/or the second start timing and/or the second control timing may be the original configuration information and/or the start timing and/or the control timing in the second storage unit 22, and before the processing unit 23 of the power management device 20 obtains the first information, the power management device 20 may start and/or operate according to the second configuration information and/or the second start timing and/or the second control timing. After the processing unit 23 obtains the first information, the power management device may start and/or operate no longer or partially according to the first configuration information and/or the first start timing and/or the first control timing, and start and/or operate according to the second configuration information and/or the second start timing and/or the second control timing

The second information stored in the second storage unit 22 may be information that may not be modified, for example, the second information may be burned in the second storage unit 22.

In the case that the start-up timing and/or the operation timing and/or the register configuration of each operation unit 24 in the power management apparatus 20 are not required, the second information may not include the second start-up timing and/or the second operation timing and/or the second configuration information of the power management apparatus 20, that is, the power management apparatus may be executed according to the default setting corresponding to the initial start-up information.

The initial startup information may include at least one of: an instruction set, an initial value of the first storage unit, data necessary for starting the power management device, and data necessary for the respective operation units 24 to cooperate with each other.

The instruction set may include at least one of an addressing mode, a data format, a deposit type, and an execution type. Addressing may include immediate addressing, direct addressing, base addressing, or indexed addressing, etc., and the data format may include instruction operand types such as at least one of address, number, character, logical number, etc., and the deposit type may include, for example, store word length and/or whether to deposit aligned, etc. The instruction types may include: at least one of data transfer, arithmetic logic operation, shift operation, transfer operation, input and output, and the like.

The initial value of the first storage unit is used to perform initialization configuration on the first storage unit 21 in the power management device 20. The initial value of the first storage unit may include: the first storage unit 21 includes an initial value of each of one or at least two registers.

The power management device 20 may perform the startup by data required to start up the power management device 20. And the operation units 24 in the power management device 20 can be operated in cooperation with each other according to data required by the cooperation of the operation units 24 with each other to realize corresponding functions.

The processing unit 23 is further configured to read at least a portion of the second information in the second storage unit 22, and write at least a portion of the second information in the first storage unit 21.

In some embodiments, the processing unit 23 may read all the second information in the second storage unit 22 and write the second information into the first storage unit 21, that is, all the second information in the second storage unit 22 is stored into the first storage unit 21 by the processor. In other embodiments, the second storage unit 22 may directly write the first portion of the second information into the first storage unit 21, and the processor reads the second portion of the second information from the second storage unit 22 and stores the second portion of the second information into the first storage unit 21.

It should be noted that, when the processing unit 23 writes data (for example, the first information or the second information) to the first storage unit 21, or when the second storage unit 22 writes data to the first storage unit 21, the data size written to the first storage unit 21 each time may be smaller than or equal to the data size that the first storage unit 21 can store. After writing data to the first storage unit 21 once, the data may be read by the execution unit 24, and when writing data to the first storage unit 21 next time, the data written next time may overwrite the data already written, or the register may perform reset (reset) first to empty the data stored in the register, and then write the data next time. Wherein the execution unit 24 can perform the corresponding function according to the data read at one time or at least two times.

And the operation unit 24 is used for reading at least part of the second information in the first storage unit 21 so as to control the self starting and/or operation.

For example, the initial value of the first storage unit in the initial startup information and/or the data required to start up the power management device may be used to control the startup of the power management device 20, and the instruction set and/or the data required to cooperate with each other by each of the operation units 24 may be used to control the operation of the power management device 20.

The execution unit 24 may also read the second information of the second portion written in the first storage unit 21 by the second storage unit 22 to perform self-starting and/or execution. The second information of the first portion and the second information of the second portion are different, and a data amount of a combination of the second information of the first portion and the second information of the second portion may be less than or equal to a data amount of the second information.

In some embodiments, the power management device 20 further includes: a bus 25 and an access port 26 connected to the bus; the first storage unit 21 and the second storage unit 22 are both connected to the bus 25; the second storage unit 22 is further configured to receive and store the first information from outside the power management apparatus through the access port and the bus.

The bus 25 may be an internal bus 12 in the related art.

In the embodiment of the application, the operation unit can read the second information in the first storage unit, so that the start and/or operation corresponding to the second information can be executed, after the start and/or operation is executed by the second information, the operation unit then executes the operation corresponding to the first information, and the start and/or operation corresponding to the second information creates a precondition for the operation corresponding to the first information.

Fig. 4 is a schematic architecture diagram of another power management apparatus provided in an embodiment of the present application, and as shown in fig. 2 and fig. 4, the power management apparatus 20 includes: a first storage unit 21, a second storage unit 22, a processing unit 23 and an execution unit 24. Wherein the first memory unit 21 and the second memory unit 22 are both connected to the bus 25.

In some embodiments, the first information in the first storage unit 21 can be used for reading and/or rewriting through the access port and the bus outside the power management device 20.

In some embodiments, the first information in the second storage unit 22 can be used for reading and/or rewriting outside the power management device 20 through the access port and the bus.

In some embodiments, the processing unit 23 is further configured to write the first control data to the second storage unit 22; the first control data in the second memory unit 22 is used for reading and/or rewriting by the processing unit 23 and/or for reading and/or rewriting by the power management device 20 via the access port 26 and the bus 25 externally.

In some embodiments, the processing unit 23 is further configured to read the first information in the first storage unit 21 to control self-start and/or self-operation.

The control unit 30 in the embodiment of the present application may be a System Controller (System Controller), the control unit 30 may include an access interface, and the access interface in the control unit 30 may be connected to the access port 26 in the power management device 20 through a wire, where the wire may be a Circuit on a Printed Circuit Board (PCB). The processing unit 23 in the embodiment of the present application may be replaced with a Controlled Hardware module (Controlled Hardware Blocks). The access interface matches the access port 26.

In the embodiment of the present application, the system controller reads and writes the second storage unit 22 and the first storage unit 21 in the power management device 20 through the bus 25, and each controlled hardware module is controlled by the internal program and the first storage unit 21 to operate. The second storage unit 22 inside the power management device 20 may be further optimized to be a storage mode that is convenient for access and can be read and written many times, and meanwhile, the operation habits of the original OTP/NVM memory and the first storage unit 21 may be retained.

In the embodiment of the application, the second storage unit is used for replacing an OTP/NVM memory in the related art, so that the second storage unit can receive and store data sent outside the power management device, and the data can guide the operation of the power management device, thereby improving the flexibility of the power management device in operation.

Fig. 5 is a schematic structural diagram of another power management apparatus according to an embodiment of the present application, and as shown in fig. 2 and fig. 5, the power management apparatus 20 includes: a first storage unit 21, a second storage unit 22, a processing unit 23 and an execution unit 24. Wherein the first memory unit 21 and the second memory unit 22 are both connected to the bus 25.

In some embodiments, the second storage unit 22 may include: a first memory 221 and a memory controller 222.

A first memory (OTP)221 for storing initial start-up information; the initial startup information includes information necessary for the startup of the power management device 20.

For example, the initial startup information may include: at least one of data required to start up the power management device 20, an initial value of the first storage unit, and an instruction set.

The first memory 221 may include an OTP/NVM memory therein. In the embodiment of the present application, the first memory 221 is an OTP memory. In another embodiment, the first memory 221 may be an NVM memory. In other embodiments, the first memory 221 may be a non-erasable memory, or a read-only memory, or a non-programmable memory, or a magnetic surface memory, etc.

The memory controller 222 in the embodiment of the present application may be an NVM controller. A memory controller (NVM controller) 222 for reading a first part of the initial boot information in the first memory (OTP)221 and writing the first part of the initial boot information to the first memory unit 21. The memory controller may not modify the data in the read first memory. In this embodiment, the first part of the initial boot information may be information directly written into the first storage unit 21 through the storage controller 222.

In some embodiments, the second storage unit 22 may further include: a second memory 223.

The second Memory 223 in the embodiment of the present application may be a volatile Memory, for example, the second Memory 223 may be a Random Access Memory (RAM). The RAM may include a magnetic Random Access Memory (FRAM) or a Flash Memory (Flash Memory).

A memory controller (NVM controller) 222 for reading a second part of the initial boot information in the first memory (OTP)221 and writing the second part of the information to the second memory (RAM) 223.

The memory controller 222 in the embodiment of the present application is capable of reading data in the first memory 221 and writing the data in the first memory 221 into the first storage unit 21 and/or the second memory 223.

The processing unit 23 is further configured to read the second part of information from the second memory (RAM)223 and write the second part of information into the first storage unit 21.

In this embodiment, the second part of the initial startup information may be written into the second memory 223 through the memory controller 222, and then read from the second memory 223 and written into the first storage unit 21 through the processing unit 23. How to select the first part information in the initial starting information and the second part information in the initial starting information is determined according to the actual operating condition.

The first part information and the second part information may be different information in the initial startup information, and the data amount of the combination of the first part information and the second part information may be smaller than or equal to the data amount of the initial startup information.

In some embodiments, a second memory (RAM)223, also used to receive and store the transmitted first information from outside the power management device 20 through the access port 26 and the bus 25; the processing unit 23 is further configured to read the first information in the second memory (RAM)223 and write the first information into the first storage unit 21.

In some embodiments, the second storage unit 22 further includes: a third memory 224.

A third memory (ROM)224 for storing initial configuration information; the initial configuration information includes at least one of: second configuration information of the first storage unit 21, a second start-up timing of the power management apparatus 20, and a second control timing of the power management apparatus 20.

The processing unit 23 is further configured to read the initial configuration information in the third memory 224 and write the initial configuration information into the first storage unit 21.

And the operation unit 24 is further configured to read the initial configuration information in the first storage unit 21 to control self start-up and/or operation.

The third Memory 224 may comprise a non-volatile Memory, for example, the third Memory 224 may comprise a Read-Only Memory (ROM). In the present embodiment, the ROM may be a non-erasable memory. In other embodiments, the ROM may include a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), or an Electrically Erasable Programmable Read-Only Memory (EEPROM).

The first storage unit 21, in some embodiments, is further configured to receive second control data from outside the power management device 20 via the access port 26 and the bus 25; the second control data in the first storage unit are used for the operation unit to read and control the operation of the operation unit; the operation unit 24 is further configured to read the second control data in the first storage unit 21 to control self start and/or operation.

In some embodiments, the processing unit 23 is further configured to receive third control data from outside the power management apparatus through the access port 26 and the bus 25 to control self-start and/or operation, or write the third control data into the first storage unit 21; third control data in the first storage unit 21, which is used for the operation unit 24 to read and control the operation unit to operate; the operation unit 24 may be further configured to read the third control data in the first storage unit 21 to control the self-start and/or operation.

The first control data, the second control data, or the third control data in the embodiment of the present application may be data that controls the operation of the operation unit 24 that reads the first control data, the second control data, or the third control data, and the first control data, the second control data, or the third control data may be data different from the first information and the second information described above.

It should be understood that fig. 4 and 5 correspond to architectures in which the data flow is different, but the corresponding functions of each unit may be the same.

In the embodiment of the application, the first memory (OTP) is used for storing initial startup information, the second memory (RAM) is used for receiving and storing first information sent by the outside of the power management device, and the third memory (ROM) is used for storing initial configuration information, so that different memories store different contents, the processing unit can read the contents more quickly and conveniently, the reading and writing speed of the time sequence of the power management device is improved, and the operating efficiency of the power management device is further improved.

The following further describes the embodiments of the present application based on fig. 2 and 5:

in the architecture of the power management device 20 in the embodiment of the present application, a ROM memory and a RAM memory are added. And the topological structures of each other are improved so as to achieve the aim of optimizing the register, the state machine and the task sequence. The ROM memory and the RAM memory correspond to the third memory (ROM)224 and the second memory (RAM)223, respectively.

As can be seen from fig. 5, the OTP memory (corresponding to the first memory 221 described above) and the NVM controller (corresponding to the memory controller 222 described above) in the embodiment of the present application are not directly connected to the internal processor (corresponding to the processing unit 23 described above) of the power management device 20, while the OTP memory and the NVM controller are connected together, or the OTP memory and the NVM controller are integrated together, and the connection of the OTP memory and the NVM controller to the bus 25 is not changed, but its output is directly connected to the RAM memory at the back end and the internal register or registers (the internal register or registers correspond to the first memory unit 21 described above) of the power management device 20. Correspondingly, the internal registers retain input connections to bus 25 in addition to adding inputs to the OTP memory and NVM controller. Also, the newly added RAM memory has inputs to bus 25 in addition to the OTP memory and NVM controller. In this regard, the input topology to the RAM memory and the internal registers is the same, and the content input to the RAM memory and the internal registers may be different. The added ROM memory is connected only to the input of the bus 25.

In the embodiment of the present application, the OTP memory and the NVM controller and the ROM memory are written once by the manufacturer before shipment through the bus 25 and the access port 26, and after writing, they cannot be modified by the above-mentioned control unit (or outside the power management device 20), and are power-down non-volatile. In addition, there may be a portion of the contents in the core space inside the OTP memory, which is unchangeable, that is, the contents in the core space are unchangeable no matter how the version of the power management device 20 is iterated, or how the version of the OTP memory in the power management device 20 is iterated, while a portion of the memory space outside the core space is left for subsequent optimization, and the portion of the memory space outside the core space may be updated continuously with the versions of the power management device 20 or the versions of the OTP memory in the power management device 20 during iteration, and the portion of the memory space outside the core space is written once by the manufacturer of the power management device 20 during the later production process along with the previous unchangeable portion. The RAM memory or the register is written by system software (corresponding to the control unit) or the NVM controller through different mechanisms during the system startup process, for example, the content written into the RAM memory or the register by the system software can be written only after the control unit is started, while the content written into the RAM memory or the register by the NVM controller only needs to wait until the NVM controller is started, and after the power management device including the power management apparatus 20 is started, the NVM controller is started before the control unit is started; the outputs of the ROM memory, the RAM memory, and the internal registers are internal processors of the power management device 20, except that the internal registers may receive data inputs from the system controller (corresponding to the control unit described above), the NVM controller, and the internal processors of the power management device 20.

The following description relates to ROM memory and RAM memory:

the ROM memory may be used to store a start-up sequence for internal modules of the power management device 20 (which may correspond to the operating units 24 described above), which may be a start-up sequence that includes many parts, but may not be all, of the operating units 24. The RAM memory is used for opening the modification requirements of register configuration and control time sequence in the later period of various products, and the content of the RAM memory is complementary to the ROM memory and the OTP memory. The difference is that the ROM memory is written before leaving the factory by the manufacturer of the power management device 20, like the OTP memory; the RAM memory may then be written to by the system controller and the NVM controller during each system boot. It is obvious that the register as the final execution controller of the power management device 20 can receive the output contents or instructions of the system controller, ROM memory and RAM memory (read and written by the internal processor of the power management device 20) respectively, and then control the different analog and digital parts to operate according to the schedule or according to the output contents or instructions.

Based on the architectures shown in fig. 2 and 5, the general user can select an appropriate OTP memory size using the OTP memory and NVM controller and register portions according to the related art, which can address all setting requirements of the power management device 20 start-up process. In the starting process, a general user does not need to consider the existence of a ROM memory/a RAM memory at all, because the RAM memory is only used as a data transmission bridge between the OTP memory and the internal processor; in addition, if the user has no particular need for the start-up sequence, it may be sufficient to follow the default settings of the OTP memory entirely, at which time the contents of the ROM memory are indeed bypassed.

For a large-scale power management device 20, it is impossible for a device or system developer to design reliable register settings (which may correspond to the configuration information of the first storage unit 21), state machines, and startup sequences at one time or in a short period of time, and often during the development process, it is necessary to modify various register settings and system startup sequences many times or countless times, it is also possible that automatic sequences and register contents need to be dynamically configured, and different products may have different sequence and register configuration requirements. Based on the requirement, in the system starting process, the system software updates the RAM memory and the register in a patching mode, and the patch can be changed and burned at any time, so that strong supplement and flexibility are provided, and the risk of redevelopment of the later power management device 20 is greatly reduced. Of course, this approach also increases the cost of part of the ROM memory and the RAM memory, but for a large-scale power management device 20, the later cost can be well avoided by considering the later secondary development cost or the cost of re-streaming.

It should be noted that although the control unit is not shown in fig. 2, 3, and 5, the connection manner of the power management device 20 and the control unit is the same as that of the power management device 20 and the control unit 30 corresponding to fig. 4. Although fig. 4 and 5 do not show an operating unit, the operating unit is connected to the first storage unit, corresponding to fig. 2 and 3.

Fig. 6 is a schematic diagram of an operation process of a power management apparatus according to an embodiment of the present application. As shown in fig. 6, shown in fig. 6 is a combination process of software and hardware inside the power management device 20 based on the power management device 20 of fig. 5 at the time of starting. The software/hardware operation steps in the power management device 20 are as follows:

first, the system power is turned on by external hardware or software. For example, the power of the power management apparatus including the power management device 20 may be turned on by external hardware or software.

Secondly, the first memory 221(OTP memory) and the memory controller (NVM controller) 222 are activated, and may operate according to the predetermined content of the OTP memory, and at the same time, the NVM controller may transmit a part of the content in the OTP memory to the second memory 223(RAM memory) and the first storage unit 21, the content transmitted to the register may control the hardware operation in the power management device 20 (e.g. the operation of the operation unit 24), and the content transmitted to the RAM memory may be picked up by the internal processor of the power management device 20, written into the register, and finally also controlled the hardware operation.

This portion of the contents of the OTP memory that the NVM controller handles may be a correction or supplement to the initial OTP memory contents. Next, during the startup of the system software (corresponding to the control unit 30 described above), the system controller writes the relevant register patch and RAM patch (e.g., register configuration patch and/or startup timing patch and/or control timing patch) into the corresponding areas of the register and RAM memory through the data port (corresponding to the access port described above), respectively. During or after these steps are performed, the internal processor of the power management device 20 may pick up the register control or start and/or control sequence information from the RAM memory and the third memory 224(ROM memory), and write the register control or start and/or control sequence information to the register as planned, thereby controlling or correcting the start and operation of the power management device 20. With the optimization of the registers of the power management device 20, the operation state of the modules outside the power management device 20 may be changed.

In the embodiment of the application, the hardware sequence generated by the first storage unit 21 is changed by software stored in the ROM/RAM.

To save costs, the architecture shown in fig. 5 may be designed in a mode in which ROM memory and RAM memory can be removed. After the system is mature and stable, the device without ROM memory or RAM memory can be produced, and the mature register control value and sequence are completely written into the OTP memory, and the prior art scheme is recovered. But this may require a larger capacity of OTP memory.

Through the framework of the power management device provided by the embodiment of the application, the following technical effects can be achieved:

through the optimized internal memory architecture, the system can change and optimize the internal registers, the state machine or the starting sequence of the power management device at any time. With an optimized internal memory architecture, the design flexibility of the device and product is greatly improved, while providing design possibilities for product customization. By optimizing the architecture of the power management device, the later cost reduction of the device and the product is replaced by limited cost, and meanwhile, the product success possibility of the power management device is greatly improved. By means of a flexible and cullable architecture, a better choice is provided in terms of cost and development progress.

The embodiment of the application provides an optimized architecture thought, and aims at the register, the state machine and the task sequence of the power management device, and solves the design problem caused by early stage uncertainty by using software, so that the success probability of the power management device and the design flexibility of subsequent products are improved. Due to the integration of the internal ROM memory and the RAM memory, the system can flexibly configure any register, state machine and task sequence, efficiently complete the system optimization in real time and configure corresponding configuration items according to the requirements of projects, products or use cases. The method has the advantages that the capacity of the OTP memory is large, the partition mode is flexible, the flexibility of design of the OTP memory is provided, and meanwhile, the feasibility and the flexibility are provided for avoiding the content design flaw of the OTP memory and the differentiation of the content of the OTP memory in the later period. The optimized framework considers the cost and the development period. On the basis of limited cost increase, the success probability of device research and development is greatly improved. In combination, the scheme saves the late development cost and accelerates the marketing process of the product.

The embodiment of the application provides a flexible architecture, and realizes flexible configuration and optimization of a register, a state machine and a task sequence of a power management device. In the implementation process of the scheme, on one hand, the architecture requirement that the ROM memory and the RAM memory can be flexibly eliminated is realized, and new innovation points can be generated; on the other hand, whether the ROM memory and the RAM memory need to be increased or not can be flexibly determined according to the requirements of the scheme, so that a new memory architecture is generated, and the technical scheme is further enriched. In addition, the requirement of large capacity OTP memory may further optimize the technical solution, resulting in new innovation points.

Fig. 7 is a schematic flowchart of a power management method provided in an embodiment of the present application, and as shown in fig. 7, the method is applied to a power management device, and the method includes:

s701, the second storage unit receives and stores first information from outside the power management apparatus, where the first information includes at least one of: the first configuration information of the first storage unit, a first starting time sequence of the power management device and a first control time sequence of the power management device.

S703, the processing unit reads the first information in the second storage unit and writes the first information into the first storage unit.

S705, the running unit reads the first information in the first storage unit to control self starting and/or running.

In some embodiments, the method further comprises:

the processing unit reads at least part of the second information in the second storage unit and writes at least part of the second information into the first storage unit; the second information comprises initial starting information, or the second information comprises the initial starting information and initial configuration information; the initial start-up information includes information required for the power management device to start up, and the initial configuration information includes at least one of: the second configuration information of the first storage unit, a second starting time sequence of the power management device and a second control time sequence of the power management device;

the operation unit reads at least part of the second information in the first storage unit to control self starting and/or operation.

In some embodiments, the second storage unit receives and stores the first information from outside the power management device through the access port and the bus.

In some embodiments, the second storage unit receives and stores first information external to the power management device through the access port and the bus; and/or

The processing unit writes the first control data into the second storage unit; the first control data in the second storage unit is used for the processing unit to read and/or rewrite and/or is used for the external part of the power management device to read and/or rewrite through the access port and the bus; and/or the presence of a gas in the gas,

the processing unit reads the first information in the first storage unit to control the self starting and/or running.

In some embodiments, the method further comprises:

and a memory controller (NVM controller) for reading a first part of information in the initial start-up information in the first memory (OTP) and writing the first part of information to the first memory cell. The initial startup information includes information required for starting the power management device.

In some embodiments, the method further comprises:

the memory controller (NVM controller) reads a second part of information in the initial starting information in the first memory (OTP), and writes the second part of information into the second memory (RAM);

the processing unit reads the second part of information from the second memory (RAM) and writes the second part of information into the first memory unit.

In some embodiments, the method further comprises:

a second memory (RAM) receiving and storing first information from outside the power management apparatus through the access port and the bus;

the processing unit reads the first information in the second memory (RAM) and writes the first information into the first storage unit.

In some embodiments, the method further comprises:

the processing unit reads the initial configuration information in the third memory and writes the initial configuration information into the first memory unit; the initial configuration information includes at least one of: the second configuration information of the first storage unit, a second starting time sequence of the power management device and a second control time sequence of the power management device;

the operation unit reads the initial configuration information in the first storage unit to control the self starting and/or operation.

In some embodiments, the first storage unit comprises a register unit, the first memory comprises a one-time programmable OTP memory, the second memory comprises a random access memory RAM, and the third memory comprises: a read only memory ROM.

In some embodiments, the method further comprises:

the first storage unit receives and stores second control data from the outside of the power management device through the access port and the bus; the second control data in the first storage unit are used for the operation unit to read and control the operation unit to operate; and/or

The processing unit receives third control data from the outside of the power management device through the access port and the bus so as to control the self start and/or operation, or writes the third control data into the first storage unit; and the third control data in the first storage unit is used for the operation unit to read and control the operation of the operation unit.

Fig. 8 is a schematic structural diagram of a power management apparatus according to an embodiment of the present application, and as shown in fig. 8, the power management apparatus 80 includes any one of the power management devices 20 corresponding to fig. 2 to 5.

The power management device 80 may include a terminal, a network device, or a core network device.

A terminal can refer to an access terminal, subscriber unit, subscriber station, mobile, remote station, remote terminal, mobile device, User Equipment (UE), wireless communication device, User agent, or User Equipment. Alternatively, the terminal may be a server, a mobile phone, a tablet computer, a laptop computer, a palmtop computer, a personal digital assistant, a portable media player, a smart speaker, a navigation device, a display device, a wearable device such as a smart band, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a pedometer, a digital TV, a desktop computer, or the like.

The network device may be a network side device that performs Wireless communication with the terminal, for example, an access point of Wireless-Fidelity (Wi-Fi), an evolved node b, a base station of next generation communication, such as a gNB or a small station of 5G, a micro station or a Transmission Reception Point (TRP), and may also be a relay station, an access point, a vehicle-mounted device or a wearable device.

The core network device may be an Access and Mobility Management Function (AMF) device, a Session Management Function (SMF) or a User Plane Function (UPF), and the like.

The power management device may also be a device in the internet of things, such as a vehicle or a smart appliance.

In some embodiments, the control unit in the embodiments of the present application may include: a Central Processing Unit (CPU).

In other embodiments, a processing unit, a control unit, or a memory controller may include: at least one of an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a Programmable Logic Device (PLD), a Field Programmable Gate Array (FPGA), a controller, a microcontroller, and a microprocessor. It is understood that the electronic device implementing the above-described processor function may be other electronic devices, and the embodiments of the present application are not limited in particular.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment of the present application" or "a previous embodiment" or "some embodiments" or "some implementations" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" or "an embodiment of the present application" or "the preceding embodiments" or "some implementations" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the implementation of the present application, in the corresponding architecture diagrams in fig. 1 to 5, there may be a connection relationship (for example, connection through a data line or a wire) between two units with data transmission, or between a unit and a device, or between a device and a device, so that data can be transmitted through the connection relationship.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "connected" and "connected" are to be interpreted broadly, e.g., as being fixed or detachable or integrally connected; may be mechanically connected, may be electrically connected or may be in communication with each other; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only one logical function division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units; can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit may be implemented in the form of hardware, or in the form of hardware plus a software functional unit.

The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to arrive at new method embodiments. Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict.

The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.

Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as a removable Memory device, a Read Only Memory (ROM), a magnetic disk, or an optical disk.

Alternatively, the integrated units described above in the present application may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or portions thereof contributing to the related art may be embodied in the form of a software product stored in a storage medium, and including several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media that can store program code, such as removable storage devices, ROMs, magnetic or optical disks, etc.

It should be noted that the drawings in the embodiments of the present application are only for illustrating schematic positions of the respective devices on the terminal device, and do not represent actual positions in the terminal device, actual positions of the respective devices or the respective areas may be changed or shifted according to actual conditions (for example, a structure of the terminal device), and a scale of different parts in the terminal device in the drawings does not represent an actual scale.

The above description is only for the embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A power management device, comprising:

a first storage unit;

2. The power management device of claim 1,

the second storage unit is also used for storing second information; the second information comprises initial starting information, or the second information comprises the initial starting information and initial configuration information; the initial startup information includes information required for startup of the power management device, and the initial configuration information includes at least one of: second configuration information of the first storage unit, a second starting sequence of the power management device and a second control sequence of the power management device;

the processing unit is further configured to read at least a portion of the second information in the second storage unit, and write the at least a portion of the second information into the first storage unit;

the operation unit is further used for reading at least part of the second information in the first storage unit so as to control self starting and/or operation.

3. The power management device of claim 1, further comprising: a bus and an access port connected to the bus;

the first storage unit and the second storage unit are both connected with the bus;

the second storage unit is further configured to receive and store the first information from outside the power management apparatus through the access port and the bus.

4. The power management device of claim 3,

the first information in the first storage unit and/or the second storage unit is used for being read and/or rewritten outside the power management device through the access port and the bus; and/or the presence of a gas in the atmosphere,

the processing unit is further used for writing first control data into the second storage unit; the first control data in the second storage unit is used for the processing unit to read and/or rewrite, and/or is used for the power management device to read and/or rewrite through the access port and the bus; and/or the presence of a gas in the atmosphere,

the processing unit is further used for reading the first information in the first storage unit so as to control the self starting and/or running.

5. The power management device of claim 3, wherein the second storage unit comprises: a first memory and a memory controller;

the first memory is used for storing initial starting information; the initial starting information comprises information required by starting the power management device;

the storage controller is configured to read a first part of information in the initial startup information in the first storage, and write the first part of information into the first storage unit.

6. The power management device according to any one of claims 3 to 5, wherein the second storage unit includes: a first memory, a memory controller, and a second memory;

the memory controller is used for reading a second part of information in the initial starting information in the first memory and writing the second part of information into the second memory;

the processing unit is further configured to read the second part of information from the second memory, and write the second part of information into the first storage unit.

7. The power management device of claim 6,

the second memory is also used for receiving and storing the first information from the outside of the power management device through the access port and the bus;

the processing unit is further configured to read the first information in the second memory, and write the first information into the first storage unit.

8. The power management device of claim 6, wherein the second storage unit further comprises:

a third memory for storing initial configuration information; the initial configuration information includes at least one of: second configuration information of the first storage unit, a second starting time sequence of the power management device and a second control time sequence of the power management device;

the processing unit is further configured to read the initial configuration information in the third memory, and write the initial configuration information into the first storage unit;

the operation unit is further configured to read the initial configuration information in the first storage unit to control self start and/or operation.

9. The power management device of claim 8, wherein the first storage unit comprises a register unit, the first memory comprises a one-time programmable (OTP) memory, the second memory comprises a Random Access Memory (RAM), and the third memory comprises: a read only memory ROM.

10. The power management device of claim 3 or 5,

the first storage unit is also used for receiving and storing second control data from the outside of the power management device through the access port and the bus; the second control data in the first storage unit is used for the operation unit to read and control the operation of the operation unit; and/or

The processing unit is further configured to receive third control data from the outside of the power management device through the access port and the bus to control self start and/or operation, or write the third control data into the first storage unit; and the third control data in the first storage unit is used for the operation unit to read and control the operation of the operation unit.

11. A method of power management, comprising:

the second storage unit receives and stores first information from outside the power management apparatus, the first information including at least one of: the method comprises the steps that first configuration information of a first storage unit, a first starting time sequence of the power management device and a first control time sequence of the power management device are stored;

12. A power management apparatus comprising the power management device of any one of claims 1 to 10.